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* Add log_checkpoint function and use it in opt_muxtreeClifford Wolf2019-07-153-0/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix first divergence in #1178Eddie Hung2019-07-091-1/+5
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* synth_ecp5: Fix typo in copyright headerDavid Shah2019-07-091-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1174 from YosysHQ/eddie/fix1173Clifford Wolf2019-07-091-0/+3
|\ | | | | Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
| * Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zeroEddie Hung2019-07-091-0/+3
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* | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-positionClifford Wolf2019-07-091-3/+2
|\ \ | | | | | | write_verilog: fix placement of case attributes
| * | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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* | | Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdcEddie Hung2019-07-093-15/+3
|\ \ \ | |_|/ |/| | Revert "Add "synth -keepdc" option"
| * | Revert "Add "synth -keepdc" option"Eddie Hung2019-07-093-15/+3
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* | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscoreEddie Hung2019-07-091-4/+6
|\ \ | |/ |/| Rename __builtin_bswap32 -> bswap32
| * Rename __builtin_bswap32 -> bswap32Eddie Hung2019-07-091-4/+6
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* | Merge pull request #1168 from whitequark/bugpoint-processesClifford Wolf2019-07-092-17/+105
|\ \ | | | | | | Add support for processes in bugpoint
| * | bugpoint: add -assigns and -updates options.whitequark2019-07-091-9/+81
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| * | proc_clean: add -quiet option.whitequark2019-07-091-8/+24
| | | | | | | | | | | | This is useful for other passes that call it often, like bugpoint.
* | | Merge pull request #1169 from whitequark/more-proc-cleanupsClifford Wolf2019-07-095-22/+168
|\ \ \ | | | | | | | | A new proc_prune pass
| * | | proc_prune: promote assigns to module connections when legal.whitequark2019-07-093-33/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can pave the way for further transformations by exposing identities that were previously hidden in a process to any pass that uses SigMap. Indeed, this commit removes some ad-hoc logic from proc_init that appears to have been tailored to the output of genrtlil in favor of using `SigMap.apply()`. (This removal is not optional, as the ad-hoc logic cannot cope with the result of running proc_prune; a similar issue was fixed in proc_arst.)
| * | | proc_prune: new pass.whitequark2019-07-093-1/+138
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The proc_prune pass is similar in nature to proc_rmdead pass: while proc_rmdead removes branches that never become active because another branch preempts it, proc_prune removes assignments that never become active because another assignment preempts them. Genrtlil contains logic similar to the proc_prune pass, but their purpose is different: genrtlil has to prune assignments to adapt the semantics of blocking assignments in HDLs (latest assignment wins) to semantics of assignments in RTLIL processes (assignment in the most specific case wins). On the other hand proc_prune is a general purpose RTLIL simplification that benefits all frontends, even those not using the Yosys AST library. The proc_prune pass is added to the proc script after proc_rmdead, since it gives better results with fewer branches.
* | | Merge pull request #1163 from whitequark/more-case-attrsClifford Wolf2019-07-093-16/+28
|\ \ \ | | | | | | | | More support for case rule attributes
| * | | verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
| | | | | | | | | | | | | | | | This appears to be an omission.
| * | | proc_mux: consider \src attribute on CaseRule.whitequark2019-07-081-10/+16
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| * | | verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
| | | | | | | | | | | | | | | | Attributes are not permitted in that position by Verilog grammar.
| * | | genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
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* | | | Merge pull request #1162 from whitequark/rtlil-case-attrsClifford Wolf2019-07-093-5/+15
|\| | | | | | | | | | | Allow attributes on individual switch cases in RTLIL
| * | | Allow attributes on individual switch cases in RTLIL.whitequark2019-07-083-5/+15
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places.
* | | Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanupClifford Wolf2019-07-091-19/+25
|\ \ \ | | | | | | | | Cleanup synth_xilinx SRL inference, make more consistent
| * \ \ Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanupEddie Hung2019-07-026-15/+20
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| * | | | Cleanup SRL inference/make more consistentEddie Hung2019-06-291-19/+25
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* | | | | Merge pull request #1166 from YosysHQ/eddie/synth_keepdcEddie Hung2019-07-083-3/+15
|\ \ \ \ \ | |_|_|_|/ |/| | | | Add "synth -keepdc" option
| * | | | Add synth -keepdc to CHANGELOGEddie Hung2019-07-081-0/+1
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| * | | | Clarify 'wreduce -keepdc' docEddie Hung2019-07-081-1/+1
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| * | | | Add synth -keepdc optionEddie Hung2019-07-081-2/+13
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* | | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-07-082-8/+22
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| * | | | | Merge pull request #1164 from YosysHQ/eddie/muxcover_mux2Eddie Hung2019-07-081-8/+19
| |\| | | | | | | | | | | | | | | | Add muxcover -mux2=cost option
| | * | | | Update muxcover doc as per @ZirconiumXEddie Hung2019-07-081-5/+10
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| | * | | | atoi -> stoiEddie Hung2019-07-081-5/+5
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| | * | | | Add muxcover -mux2=cost optionEddie Hung2019-07-081-1/+7
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| * | | | Merge pull request #1160 from ZirconiumX/cyclone_vDavid Shah2019-07-081-0/+3
| |\ \ \ \ | | |/ / / | |/| | | synth_intel: Warn about untested Quartus backend
| | * | | synth_intel: Warn about untested Quartus backendDan Ravensloft2019-07-071-0/+3
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* / / / Clarify script -scriptwire docEddie Hung2019-07-081-0/+4
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* | | Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wireClifford Wolf2019-07-051-0/+3
|\ \ \ | | | | | | | | Throw runtime exception when trying to convert inexistend C++ object to Python
| * | | Throw runtime exception when trying to convert a c++-pointer to aBenedikt Tutzer2019-07-041-0/+3
|/ / / | | | | | | | | | | | | | | | python-object in case the pointer is a nullptr to avoid a segfault. Fixes #1090
* | | Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cellEddie Hung2019-07-033-6/+28
|\ \ \ | | | | | | | | write_xaiger to treat unknown cell connections as keep-s
| * | | write_xaiger to treat unknown cell connections as keep-sEddie Hung2019-07-021-6/+14
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| * | | Add testEddie Hung2019-07-022-0/+14
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* | | | Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-033-82/+26
|\ \ \ \ | | | | | | | | | | Improve specify dummy parser
| * | | | Fix tests/various/specify.vClifford Wolf2019-07-032-8/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Some cleanups in "ignore specify parser"Clifford Wolf2019-07-032-80/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Comment out invalid syntaxEddie Hung2019-06-301-2/+2
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| * | | | Add test from #1144, and try reading without '-specify' flagEddie Hung2019-06-282-0/+16
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| * | | | Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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