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author | Clifford Wolf <clifford@clifford.at> | 2015-12-22 13:25:00 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-12-22 13:25:00 +0100 |
commit | 1d62f8710f04fec405ef79b9e9a4a031afcf7d42 (patch) | |
tree | 9ff5424d3432949fc9a1cfca383c443f93f60aba | |
parent | 2ee608246fd3dc284ff5fd864c7690b42fa45387 (diff) | |
download | yosys-1d62f8710f04fec405ef79b9e9a4a031afcf7d42.tar.gz yosys-1d62f8710f04fec405ef79b9e9a4a031afcf7d42.tar.bz2 yosys-1d62f8710f04fec405ef79b9e9a4a031afcf7d42.zip |
Fixed "splitnets -ports" for hierarchical designs
-rw-r--r-- | passes/cmds/splitnets.cc | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index a64c48791..0d7892d71 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -130,6 +130,9 @@ struct SplitnetsPass : public Pass { } extra_args(args, argidx, design); + // module_ports_db[module_name][old_port_name] = new_port_name_list + dict<IdString, dict<IdString, vector<IdString>>> module_ports_db; + for (auto module : design->selected_modules()) { SplitnetsWorker worker; @@ -199,6 +202,26 @@ struct SplitnetsPass : public Pass { module->rewrite_sigspecs(worker); + if (flag_ports) + { + for (auto wire : module->wires()) + { + if (wire->port_id == 0) + continue; + + SigSpec sig(wire); + worker(sig); + + if (sig == wire) + continue; + + vector<IdString> &new_ports = module_ports_db[module->name][wire->name]; + + for (SigSpec c : sig.chunks()) + new_ports.push_back(c.as_wire()->name); + } + } + pool<RTLIL::Wire*> delete_wires; for (auto &it : worker.splitmap) delete_wires.insert(it.first); @@ -207,6 +230,40 @@ struct SplitnetsPass : public Pass { if (flag_ports) module->fixup_ports(); } + + if (!module_ports_db.empty()) + { + for (auto module : design->modules()) + for (auto cell : module->cells()) + { + if (module_ports_db.count(cell->type) == 0) + continue; + + for (auto &it : module_ports_db.at(cell->type)) + { + IdString port_id = it.first; + const auto &new_port_ids = it.second; + + if (!cell->hasPort(port_id)) + continue; + + int offset = 0; + SigSpec sig = cell->getPort(port_id); + + for (auto nid : new_port_ids) + { + int nlen = GetSize(design->module(cell->type)->wire(nid)); + if (offset + nlen > GetSize(sig)) + nlen = GetSize(sig) - offset; + if (nlen > 0) + cell->setPort(nid, sig.extract(offset, nlen)); + offset += nlen; + } + + cell->unsetPort(port_id); + } + } + } } } SplitnetsPass; |