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* Fix xilinx_dsp index castEddie Hung2019-07-181-2/+2
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* Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
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* Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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* Working for unsignedEddie Hung2019-07-181-52/+28
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* CleanupEddie Hung2019-07-181-70/+58
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* Wrong wildcard symbolEddie Hung2019-07-181-1/+1
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* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| * mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Make all operands signedEddie Hung2019-07-171-1/+1
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* | Update commentEddie Hung2019-07-171-5/+3
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* Pattern matcher to check pool of bits, not exactlyEddie Hung2019-07-172-5/+11
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* Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
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* A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
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* SigSpec::remove_const() to return SigSpec&Eddie Hung2019-07-172-2/+3
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* Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
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* SignednessEddie Hung2019-07-162-8/+8
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* Signed extensionEddie Hung2019-07-162-6/+6
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* Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| * xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
| * mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add support {A,B,P}REG packingEddie Hung2019-07-162-55/+94
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* | SigSpec::extract to allow negative lengthEddie Hung2019-07-161-1/+1
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* | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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* | Do not swap if equalsEddie Hung2019-07-151-1/+1
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* | SigSpec::extend_u0() to return *thisEddie Hung2019-07-152-2/+3
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* | Oops forgot these filesEddie Hung2019-07-153-2/+12
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* | Add xilinx_dsp for register packingEddie Hung2019-07-153-2/+192
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* | OUT port to Y in generic DSPEddie Hung2019-07-152-3/+3
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* | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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* Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
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* Tidy upEddie Hung2019-07-151-39/+26
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* Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1516-30/+639
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| * Merge pull request #1194 from cr1901/miss-semiEddie Hung2019-07-141-2/+2
| |\ | | | | | | Fix missing semicolon in Windows-specific code in aigerparse.cc.
| | * Fix missing semicolon in Windows-specific code in aigerparse.cc.William D. Jones2019-07-141-2/+2
| | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net>
| * | Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
| |\ \ | | | | | | | | synth_ice40: switch -relut to be always on
| | * | synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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| | * | synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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| * | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
| |\ \ | | | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| | * | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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| * | Merge pull request #1185 from koriakin/xc-ff-init-valsEddie Hung2019-07-112-6/+6
| |\ \ | | | | | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
| | * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| | |/ | | | | | | | | | ISE/Vivado.
| * / Enable &mfs for abc9, even if it only currently works for ice40Eddie Hung2019-07-111-1/+1
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| * Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
| |\ | | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| | * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
| * | Merge pull request #1179 from whitequark/attrmap-procClifford Wolf2019-07-111-0/+19
| |\ \ | | | | | | | | attrmap: also consider process, switch and case attributes
| | * | attrmap: also consider process, switch and case attributes.whitequark2019-07-101-0/+19
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