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-rw-r--r--tests/verilog/for_decl_no_sv.ys9
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/verilog/for_decl_no_sv.ys b/tests/verilog/for_decl_no_sv.ys
new file mode 100644
index 000000000..34edddff7
--- /dev/null
+++ b/tests/verilog/for_decl_no_sv.ys
@@ -0,0 +1,9 @@
+logger -expect error "For loop inline variable declaration is only supported in SystemVerilog mode!" 1
+read_verilog <<EOT
+module top;
+ integer z;
+ initial
+ for (integer i = 1; i < 10; i = i + 1)
+ z = i;
+endmodule
+EOT