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| author | Zachary Snow <zach@zachjs.com> | 2021-08-30 11:35:36 -0600 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-08-30 15:19:21 -0600 |
| commit | f0a52e3dd275ee57a1b3ffd0a734b591bf21f668 (patch) | |
| tree | 3c0c7883cf1e5045701ee5c739cfd6a6a6fbbc2c /tests/verilog/for_decl_no_sv.ys | |
| parent | 1dbf91a8ef3109d6573ae64fc3fd08aedc0a690d (diff) | |
| download | yosys-f0a52e3dd275ee57a1b3ffd0a734b591bf21f668.tar.gz yosys-f0a52e3dd275ee57a1b3ffd0a734b591bf21f668.tar.bz2 yosys-f0a52e3dd275ee57a1b3ffd0a734b591bf21f668.zip | |
sv: support declaration in procedural for initialization
In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
Diffstat (limited to 'tests/verilog/for_decl_no_sv.ys')
| -rw-r--r-- | tests/verilog/for_decl_no_sv.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/verilog/for_decl_no_sv.ys b/tests/verilog/for_decl_no_sv.ys new file mode 100644 index 000000000..34edddff7 --- /dev/null +++ b/tests/verilog/for_decl_no_sv.ys @@ -0,0 +1,9 @@ +logger -expect error "For loop inline variable declaration is only supported in SystemVerilog mode!" 1 +read_verilog <<EOT +module top; + integer z; + initial + for (integer i = 1; i < 10; i = i + 1) + z = i; +endmodule +EOT |