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-rw-r--r--tests/svtypes/.gitignore3
-rwxr-xr-xtests/svtypes/run-test.sh20
-rw-r--r--tests/svtypes/typedef_memory.sv10
-rw-r--r--tests/svtypes/typedef_memory.ys3
-rw-r--r--tests/svtypes/typedef_memory_2.sv10
-rw-r--r--tests/svtypes/typedef_memory_2.ys4
-rw-r--r--tests/svtypes/typedef_package.sv11
-rw-r--r--tests/svtypes/typedef_param.sv22
-rw-r--r--tests/svtypes/typedef_scopes.sv23
-rw-r--r--tests/svtypes/typedef_simple.sv19
10 files changed, 125 insertions, 0 deletions
diff --git a/tests/svtypes/.gitignore b/tests/svtypes/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/svtypes/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/svtypes/run-test.sh b/tests/svtypes/run-test.sh
new file mode 100755
index 000000000..09a30eed1
--- /dev/null
+++ b/tests/svtypes/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+ echo "all:: run-$x"
+ echo "run-$x:"
+ echo " @echo 'Running $x..'"
+ echo " @../../yosys -ql ${x%.ys}.log $x"
+done
+for x in *.sv; do
+ if [ ! -f "${x%.sv}.ys" ]; then
+ echo "all:: check-$x"
+ echo "check-$x:"
+ echo " @echo 'Checking $x..'"
+ echo " @../../yosys -ql ${x%.sv}.log -p \"prep -top top; sat -verify -prove-asserts\" $x"
+ fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv
new file mode 100644
index 000000000..577e484ad
--- /dev/null
+++ b/tests/svtypes/typedef_memory.sv
@@ -0,0 +1,10 @@
+module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
+ typedef logic [3:0] ram16x4_t[0:15];
+
+ (ram16x4_t) mem;
+
+ always @(posedge clk) begin
+ if (wen) mem[addr] <= wdata;
+ rdata <= mem[addr];
+ end
+endmodule
diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys
new file mode 100644
index 000000000..93cf47bbe
--- /dev/null
+++ b/tests/svtypes/typedef_memory.ys
@@ -0,0 +1,3 @@
+read_verilog -sv typedef_memory.sv
+prep -top top
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv
new file mode 100644
index 000000000..f3089bf55
--- /dev/null
+++ b/tests/svtypes/typedef_memory_2.sv
@@ -0,0 +1,10 @@
+module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
+ typedef logic [3:0] nibble;
+
+ (nibble) mem[0:15];
+
+ always @(posedge clk) begin
+ if (wen) mem[addr] <= wdata;
+ rdata <= mem[addr];
+ end
+endmodule
diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys
new file mode 100644
index 000000000..854e554f3
--- /dev/null
+++ b/tests/svtypes/typedef_memory_2.ys
@@ -0,0 +1,4 @@
+read_verilog -sv typedef_memory_2.sv
+prep -top top
+dump
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv
new file mode 100644
index 000000000..a1e16d4b1
--- /dev/null
+++ b/tests/svtypes/typedef_package.sv
@@ -0,0 +1,11 @@
+package pkg;
+ typedef logic [7:0] uint8_t;
+endpackage
+
+module top;
+
+ (* keep *) (pkg::uint8_t) a = 8'hAA;
+
+ always @* assert(a == 8'hAA);
+
+endmodule
diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv
new file mode 100644
index 000000000..ddbd471e0
--- /dev/null
+++ b/tests/svtypes/typedef_param.sv
@@ -0,0 +1,22 @@
+`define STRINGIFY(x) `"x`"
+`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)})
+
+module top;
+
+ typedef logic [1:0] uint2_t;
+ typedef logic signed [3:0] int4_t;
+ typedef logic signed [7:0] int8_t;
+ typedef (int8_t) char_t;
+
+ parameter (uint2_t) int2 = 2'b10;
+ localparam (int4_t) int4 = -1;
+ localparam (int8_t) int8 = int4;
+ localparam (char_t) ch = int8;
+
+
+ `STATIC_ASSERT(int2 == 2'b10);
+ `STATIC_ASSERT(int4 == 4'b1111);
+ `STATIC_ASSERT(int8 == 8'b11111111);
+ `STATIC_ASSERT(ch == 8'b11111111);
+
+endmodule
diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv
new file mode 100644
index 000000000..faa385bd6
--- /dev/null
+++ b/tests/svtypes/typedef_scopes.sv
@@ -0,0 +1,23 @@
+
+typedef logic [3:0] outer_uint4_t;
+
+module top;
+
+ (outer_uint4_t) u4_i = 8'hA5;
+ always @(*) assert(u4_i == 4'h5);
+
+ typedef logic [3:0] inner_type;
+ (inner_type) inner_i1 = 8'h5A;
+ always @(*) assert(inner_i1 == 4'hA);
+
+ if (1) begin: genblock
+ typedef logic [7:0] inner_type;
+ (inner_type) inner_gb_i = 8'hA5;
+ always @(*) assert(inner_gb_i == 8'hA5);
+ end
+
+ (inner_type) inner_i2 = 8'h42;
+ always @(*) assert(inner_i2 == 4'h2);
+
+
+endmodule
diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv
new file mode 100644
index 000000000..7e760dee4
--- /dev/null
+++ b/tests/svtypes/typedef_simple.sv
@@ -0,0 +1,19 @@
+module top;
+
+ typedef logic [1:0] uint2_t;
+ typedef logic signed [3:0] int4_t;
+ typedef logic signed [7:0] int8_t;
+ typedef (int8_t) char_t;
+
+ (* keep *) (uint2_t) int2 = 2'b10;
+ (* keep *) (int4_t) int4 = -1;
+ (* keep *) (int8_t) int8 = int4;
+ (* keep *) (char_t) ch = int8;
+
+
+ always @* assert(int2 == 2'b10);
+ always @* assert(int4 == 4'b1111);
+ always @* assert(int8 == 8'b11111111);
+ always @* assert(ch == 8'b11111111);
+
+endmodule