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-rw-r--r--tests/opt/bug2824.ys7
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/opt/bug2824.ys b/tests/opt/bug2824.ys
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+++ b/tests/opt/bug2824.ys
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+read_verilog -icells << EOT
+module top(input I, output O);
+$pmux #(.WIDTH(1), .S_WIDTH(2)) m (.S({I, 1'b0}), .A(1'b0), .B({I, 1'b0}), .Y(O));
+endmodule
+EOT
+
+equiv_opt -assert opt_muxtree