aboutsummaryrefslogtreecommitdiffstats
path: root/tests/arch/gowin/memory.ys
diff options
context:
space:
mode:
Diffstat (limited to 'tests/arch/gowin/memory.ys')
-rw-r--r--tests/arch/gowin/memory.ys18
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/memory.ys
new file mode 100644
index 000000000..8f88cdd7c
--- /dev/null
+++ b/tests/arch/gowin/memory.ys
@@ -0,0 +1,18 @@
+read_verilog ../common/memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Called with -verify and proof did fail!
+#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 8 t:RAM16S4
+# other logic present that is not simple
+#select -assert-none t:RAM16S4 %% t:* %D