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diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys
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+read_verilog dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_SEQ %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+select -assert-count 1 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D