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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:28 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:28 +0200 |
| commit | b4d765054897f7ee388b54d907fd8ce607db2d58 (patch) | |
| tree | a625838a0efbfb0176a57887c208467a7addd0a6 /tests/anlogic/dffs.ys | |
| parent | b659082e4a72209af62a19668800bb6334a437d7 (diff) | |
| parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
| download | yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.gz yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.bz2 yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.zip | |
Merge branch 'master' into mmicko/efinix
Diffstat (limited to 'tests/anlogic/dffs.ys')
| -rw-r--r-- | tests/anlogic/dffs.ys | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys new file mode 100644 index 000000000..9cbe5fce7 --- /dev/null +++ b/tests/anlogic/dffs.ys @@ -0,0 +1,20 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D |