6 files changed, 96 insertions, 2 deletions
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index f37b5e7e9..67cf9cf10 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -1,6 +1,7 @@
 
 OBJS += techlibs/anlogic/synth_anlogic.o
 OBJS += techlibs/anlogic/anlogic_eqn.o
+OBJS += techlibs/anlogic/anlogic_determine_init.o
 
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
@@ -8,3 +9,4 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
new file mode 100644
index 000000000..34b1d4f8a
--- /dev/null
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -0,0 +1,72 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct AnlogicDetermineInitPass : public Pass {
+	AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
+	void help() YS_OVERRIDE
+	{
+		log("\n");
+		log("    anlogic_determine_init [selection]\n");
+		log("\n");
+		log("Determine the init value of cells that doesn't allow unknown init value.\n");
+		log("\n");
+	}
+
+	Const determine_init(Const init)
+	{
+		for (int i = 0; i < GetSize(init); i++) {
+			if (init[i] != State::S0 && init[i] != State::S1)
+				init[i] = State::S0;
+		}
+
+		return init;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
+
+		extra_args(args, args.size(), design);
+
+		size_t cnt = 0;
+		for (auto module : design->selected_modules())
+		{
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type == "\\EG_LOGIC_DRAM16X4")
+				{
+					cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0")));
+					cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1")));
+					cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2")));
+					cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3")));
+					cnt++;
+				}
+			}
+		}
+		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+	}
+} AnlogicDetermineInitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/dram_init_16x4.vh b/techlibs/anlogic/dram_init_16x4.vh
new file mode 100644
index 000000000..32fb1578c
--- /dev/null
+++ b/techlibs/anlogic/dram_init_16x4.vh
@@ -0,0 +1,16 @@
+.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0],
+	  INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0],
+	  INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0],
+	  INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}),
+.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1],
+	  INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1],
+	  INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1],
+	  INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}),
+.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2],
+	  INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2],
+	  INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2],
+	  INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}),
+.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3],
+	  INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3],
+	  INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3],
+	  INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]})
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt
index eb94775ae..4e903c0a2 100644
--- a/techlibs/anlogic/drams.txt
+++ b/techlibs/anlogic/drams.txt
@@ -1,5 +1,5 @@
 bram $__ANLOGIC_DRAM16X4
-  init 0
+  init 1
   abits 4
   dbits 4
   groups 2
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v
index 87cbb6a45..084e2a25f 100644
--- a/techlibs/anlogic/drams_map.v
+++ b/techlibs/anlogic/drams_map.v
@@ -1,4 +1,5 @@
 module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0]INIT = 64'bx;
 	input CLK1;
 
 	input [3:0] A1ADDR;
@@ -8,7 +9,9 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	input [3:0] B1DATA;
 	input B1EN;
 
-	EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
+	EG_LOGIC_DRAM16X4 #(
+		`include "dram_init_16x4.vh"
+	) _TECHMAP_REPLACE_ (
 		.di(B1DATA),
 		.waddr(B1ADDR),
 		.wclk(CLK1),
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 9c44599ea..b34f4788f 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -154,6 +154,7 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("memory_bram -rules +/anlogic/drams.txt");
 			run("techmap -map +/anlogic/drams_map.v");
+			run("anlogic_determine_init");
 		}
 
 		if (check_label("fine"))