1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 38687489a..8ab124034 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1313,6 +1313,23 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$initstate (Y);
+
+output reg Y = 1;
+reg [3:0] cnt = 1;
+reg trig = 0;
+
+initial trig <= 1;
+
+always @(cnt, trig) begin
+	Y <= |cnt;
+	cnt <= cnt + |cnt;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$equiv (A, B, Y);
 
 input A, B;