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-rw-r--r--techlibs/efinix/cells_map.v12
-rw-r--r--techlibs/efinix/cells_sim.v4
2 files changed, 15 insertions, 1 deletions
diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v
index 0aeab1902..3ecec3bac 100644
--- a/techlibs/efinix/cells_map.v
+++ b/techlibs/efinix/cells_map.v
@@ -17,6 +17,18 @@ module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE
module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module \$_DLATCH_N_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = E ? D : Q;
+endmodule
+
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index 2fc2034a6..a74d1c571 100644
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -59,7 +59,9 @@ module EFX_FF(
assign ce = CE_POLARITY ? CE : ~CE;
assign sr = SR_POLARITY ? SR : ~SR;
assign d = D_POLARITY ? D : ~D;
-
+
+ initial Q = 1'b0;
+
generate
if (SR_SYNC == 1)
begin