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-rw-r--r--techlibs/xilinx/cells_sim.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 5410983ae..1262fc8c1 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -516,7 +516,7 @@ module DSP48E1 (
if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value");
if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value");
`endif
- Pr[42:0] <= Ar[24:0] * Br;
+ Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
end
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