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Diffstat (limited to 'techlibs/gowin/cells_sim.v')
-rw-r--r-- | techlibs/gowin/cells_sim.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 947942626..14441c2fc 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -57,3 +57,9 @@ endmodule module GSR (input GSRI); wire GSRO = GSRI; endmodule + +module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM); + parameter [3:0] ALU_MODE = 0; // default 0 = ADD + assign {COUT, SUM} = CIN + I1 + I0; +endmodule // alu + |