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-rw-r--r--passes/equiv/equiv_add.cc2
-rw-r--r--passes/equiv/equiv_induct.cc20
-rw-r--r--passes/equiv/equiv_make.cc2
-rw-r--r--passes/equiv/equiv_mark.cc20
-rw-r--r--passes/equiv/equiv_miter.cc18
-rw-r--r--passes/equiv/equiv_purge.cc14
-rw-r--r--passes/equiv/equiv_remove.cc6
-rw-r--r--passes/equiv/equiv_simple.cc22
-rw-r--r--passes/equiv/equiv_status.cc6
-rw-r--r--passes/equiv/equiv_struct.cc20
10 files changed, 65 insertions, 65 deletions
diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc
index 71599f46e..cdc74b0b2 100644
--- a/passes/equiv/equiv_add.cc
+++ b/passes/equiv/equiv_add.cc
@@ -152,7 +152,7 @@ struct EquivAddPass : public Pass {
for (int i = 0; i < GetSize(gold_signal); i++) {
Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
- equiv_cell->set_bool_attribute("\\keep");
+ equiv_cell->set_bool_attribute(ID::keep);
to_equiv_bits[gold_signal[i]] = equiv_signal[i];
to_equiv_bits[gate_signal[i]] = equiv_signal[i];
added_equiv_cells.insert(equiv_cell);
diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index bcc68d6d2..ec651193e 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -58,9 +58,9 @@ struct EquivInductWorker
log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
cell_warn_cache.insert(cell);
}
- if (cell->type == "$equiv") {
- SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
+ if (cell->type == ID($equiv)) {
+ SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
if (bit_a != bit_b) {
int ez_a = satgen.importSigBit(bit_a, step);
int ez_b = satgen.importSigBit(bit_b, step);
@@ -125,7 +125,7 @@ struct EquivInductWorker
if (!ez->solve(new_step_not_consistent)) {
log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset));
for (auto cell : workset)
- cell->setPort("\\B", cell->getPort("\\A"));
+ cell->setPort(ID::B, cell->getPort(ID::A));
success_counter += GetSize(workset);
return;
}
@@ -137,10 +137,10 @@ struct EquivInductWorker
for (auto cell : workset)
{
- SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
- log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort("\\Y"))));
+ log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y))));
int ez_a = satgen.importSigBit(bit_a, max_seq+1);
int ez_b = satgen.importSigBit(bit_b, max_seq+1);
@@ -151,7 +151,7 @@ struct EquivInductWorker
if (!ez->solve(cond)) {
log(" success!\n");
- cell->setPort("\\B", cell->getPort("\\A"));
+ cell->setPort(ID::B, cell->getPort(ID::A));
success_counter++;
} else {
log(" failed.\n");
@@ -219,8 +219,8 @@ struct EquivInductPass : public Pass {
pool<Cell*> unproven_equiv_cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
- if (cell->getPort("\\A") != cell->getPort("\\B"))
+ if (cell->type == ID($equiv)) {
+ if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.insert(cell);
}
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 4855ce29e..50572ae5c 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -406,7 +406,7 @@ struct EquivMakeWorker
void init_bit2driven()
{
for (auto cell : equiv_mod->cells()) {
- if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
+ if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
continue;
for (auto &conn : cell->connections())
{
diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
index 135eaf145..737de25d9 100644
--- a/passes/equiv/equiv_mark.cc
+++ b/passes/equiv/equiv_mark.cc
@@ -48,7 +48,7 @@ struct EquivMarkWorker
{
for (auto cell : module->cells())
{
- if (cell->type == "$equiv")
+ if (cell->type == ID($equiv))
equiv_cells.insert(cell->name);
for (auto &port : cell->connections())
@@ -122,8 +122,8 @@ struct EquivMarkWorker
{
auto cell = module->cell(cell_name);
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
if (sig_a == sig_b) {
for (auto bit : sig_a)
@@ -139,11 +139,11 @@ struct EquivMarkWorker
for (auto cell : module->cells())
{
- if (cell_regions.count(cell->name) || cell->type != "$equiv")
+ if (cell_regions.count(cell->name) || cell->type != ID($equiv))
continue;
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
log_assert(sig_a != sig_b);
@@ -176,10 +176,10 @@ struct EquivMarkWorker
{
if (cell_regions.count(cell->name)) {
int r = final_region_map.at(cell_regions.at(cell->name));
- cell->attributes["\\equiv_region"] = Const(r);
+ cell->attributes[ID::equiv_region] = Const(r);
region_cell_count[r]++;
} else
- cell->attributes.erase("\\equiv_region");
+ cell->attributes.erase(ID::equiv_region);
}
for (auto wire : module->wires())
@@ -191,10 +191,10 @@ struct EquivMarkWorker
if (GetSize(regions) == 1) {
int r = final_region_map.at(*regions.begin());
- wire->attributes["\\equiv_region"] = Const(r);
+ wire->attributes[ID::equiv_region] = Const(r);
region_wire_count[r]++;
} else
- wire->attributes.erase("\\equiv_region");
+ wire->attributes.erase(ID::equiv_region);
}
for (int i = 0; i < next_final_region; i++)
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index e06f9515b..085970189 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -47,7 +47,7 @@ struct EquivMiterWorker
if (cone.count(c))
return;
- if (c->type == "$equiv" && !seed_cells.count(c)) {
+ if (c->type == ID($equiv) && !seed_cells.count(c)) {
leaves.insert(c);
return;
}
@@ -57,7 +57,7 @@ struct EquivMiterWorker
for (auto &conn : c->connections()) {
if (!ct.cell_input(c->type, conn.first))
continue;
- if (c->type == "$equiv" && (conn.first == "\\A") != gold_mode)
+ if (c->type == ID($equiv) && (conn.first == ID::A) != gold_mode)
continue;
for (auto bit : sigmap(conn.second))
if (bit_to_driver.count(bit))
@@ -81,7 +81,7 @@ struct EquivMiterWorker
// find seed cells
for (auto c : source_module->selected_cells())
- if (c->type == "$equiv") {
+ if (c->type == ID($equiv)) {
log("Seed $equiv cell: %s\n", log_id(c));
seed_cells.insert(c);
}
@@ -213,18 +213,18 @@ struct EquivMiterWorker
vector<Cell*> equiv_cells;
for (auto c : miter_module->cells())
- if (c->type == "$equiv" && c->getPort("\\A") != c->getPort("\\B"))
+ if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B))
equiv_cells.push_back(c);
for (auto c : equiv_cells)
{
SigSpec cmp = mode_undef ?
- miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort("\\A"), State::Sx),
- miter_module->Eqx(NEW_ID, c->getPort("\\A"), c->getPort("\\B"))) :
- miter_module->Eq(NEW_ID, c->getPort("\\A"), c->getPort("\\B"));
+ miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx),
+ miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) :
+ miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
if (mode_cmp) {
- string cmp_name = string("\\cmp") + log_signal(c->getPort("\\Y"));
+ string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
for (int i = 1; i < GetSize(cmp_name); i++)
if (cmp_name[i] == '\\')
cmp_name[i] = '_';
@@ -242,7 +242,7 @@ struct EquivMiterWorker
}
if (mode_trigger) {
- auto w = miter_module->addWire("\\trigger");
+ auto w = miter_module->addWire(ID(trigger));
w->port_output = true;
miter_module->addReduceOr(NEW_ID, trigger_signals, w);
}
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index 18b3e7d36..688c20f43 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -102,7 +102,7 @@ struct EquivPurgeWorker
for (auto cell : module->cells())
{
- if (cell->type != "$equiv") {
+ if (cell->type != ID($equiv)) {
for (auto &port : cell->connections()) {
if (cell->input(port.first))
for (auto bit : sigmap(port.second))
@@ -114,9 +114,9 @@ struct EquivPurgeWorker
continue;
}
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
if (sig_a == sig_b)
continue;
@@ -130,7 +130,7 @@ struct EquivPurgeWorker
for (auto bit : sig_y)
visited.insert(bit);
- cell->setPort("\\Y", make_output(sig_y, cell->name));
+ cell->setPort(ID::Y, make_output(sig_y, cell->name));
}
SigSpec srcsig;
@@ -167,8 +167,8 @@ struct EquivPurgeWorker
rewrite_sigmap.add(chunk, make_input(chunk));
for (auto cell : module->cells())
- if (cell->type == "$equiv")
- cell->setPort("\\Y", rewrite_sigmap(sigmap(cell->getPort("\\Y"))));
+ if (cell->type == ID($equiv))
+ cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
module->fixup_ports();
}
diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc
index c5c28c7d9..6daa112b5 100644
--- a/passes/equiv/equiv_remove.cc
+++ b/passes/equiv/equiv_remove.cc
@@ -68,9 +68,9 @@ struct EquivRemovePass : public Pass {
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort("\\A") == cell->getPort("\\B"))) {
- log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort("\\Y")));
- module->connect(cell->getPort("\\Y"), mode_gate ? cell->getPort("\\B") : cell->getPort("\\A"));
+ if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
+ log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
+ module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
module->remove(cell);
remove_count++;
}
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index c2fab26f2..4d2839f4d 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -60,8 +60,8 @@ struct EquivSimpleWorker
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first))
for (auto bit : sigmap(conn.second)) {
- if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) {
- if (!conn.first.in("\\CLK", "\\C"))
+ if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) {
+ if (!conn.first.in(ID::CLK, ID::C))
next_seed.insert(bit);
} else
find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit);
@@ -90,8 +90,8 @@ struct EquivSimpleWorker
bool run_cell()
{
- SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(equiv_cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(equiv_cell->getPort(ID::B)).as_bit();
int ez_context = ez->frozen_literal();
if (satgen.model_undef)
@@ -115,9 +115,9 @@ struct EquivSimpleWorker
if (verbose) {
log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell));
- log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y")));
+ log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort(ID::Y)));
} else {
- log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort("\\Y")));
+ log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort(ID::Y)));
}
int step = max_seq;
@@ -199,7 +199,7 @@ struct EquivSimpleWorker
if (!ez->solve(ez_context)) {
log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
- equiv_cell->setPort("\\B", equiv_cell->getPort("\\A"));
+ equiv_cell->setPort(ID::B, equiv_cell->getPort(ID::A));
ez->assume(ez->NOT(ez_context));
return true;
}
@@ -256,7 +256,7 @@ struct EquivSimpleWorker
if (GetSize(equiv_cells) > 1) {
SigSpec sig;
for (auto c : equiv_cells)
- sig.append(sigmap(c->getPort("\\Y")));
+ sig.append(sigmap(c->getPort(ID::Y)));
log(" Grouping SAT models for %s:\n", log_signal(sig));
}
@@ -344,8 +344,8 @@ struct EquivSimplePass : public Pass {
int unproven_cells_counter = 0;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
- auto bit = sigmap(cell->getPort("\\Y").as_bit());
+ if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) {
+ auto bit = sigmap(cell->getPort(ID::Y).as_bit());
auto bit_group = bit;
if (!nogroup && bit_group.wire)
bit_group.offset = 0;
@@ -360,7 +360,7 @@ struct EquivSimplePass : public Pass {
unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
for (auto cell : module->cells()) {
- if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
+ if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
continue;
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first))
diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc
index b4a93ccf5..258e2e45b 100644
--- a/passes/equiv/equiv_status.cc
+++ b/passes/equiv/equiv_status.cc
@@ -59,8 +59,8 @@ struct EquivStatusPass : public Pass {
int proven_equiv_cells = 0;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
- if (cell->getPort("\\A") != cell->getPort("\\B"))
+ if (cell->type == ID($equiv)) {
+ if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.push_back(cell);
else
proven_equiv_cells++;
@@ -77,7 +77,7 @@ struct EquivStatusPass : public Pass {
log(" Equivalence successfully proven!\n");
} else {
for (auto cell : unproven_equiv_cells)
- log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort("\\A")), log_signal(cell->getPort("\\B")));
+ log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
}
unproven_count += GetSize(unproven_equiv_cells);
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index 6672948b9..1b7bf96a8 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -110,9 +110,9 @@ struct EquivStructWorker
module->connect(sig_b, sig_a);
}
- auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged");
+ auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged);
merged_attr.insert(log_id(cell_b));
- cell_a->add_strpool_attribute("\\equiv_merged", merged_attr);
+ cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr);
module->remove(cell_b);
}
@@ -126,9 +126,9 @@ struct EquivStructWorker
pool<IdString> cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
- SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
- SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
+ if (cell->type == ID($equiv)) {
+ SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
equiv_bits.add(sig_b, sig_a);
equiv_inputs.insert(sig_a);
equiv_inputs.insert(sig_b);
@@ -139,10 +139,10 @@ struct EquivStructWorker
}
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
- SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
- SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
- SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
+ if (cell->type == ID($equiv)) {
+ SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
+ SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", log_id(cell));
module->connect(sig_y, sig_a);
@@ -316,7 +316,7 @@ struct EquivStructPass : public Pass {
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{
- pool<IdString> fwonly_cells({ "$equiv" });
+ pool<IdString> fwonly_cells({ ID($equiv) });
bool mode_icells = false;
bool mode_fwd = false;
int max_iter = -1;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 09:43:57 +0000