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-rw-r--r--backends/verilog/verilog_backend.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index e174a6ea4..71f71554b 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1718,6 +1718,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
}
f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*");
+ if (!systemverilog)
+ f << indent + " " << "if (" << id("\\initial") << ") begin end\n";
dump_case_body(f, indent, &proc->root_case, true);
std::string backup_indent = indent;
@@ -1850,6 +1852,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
}
f << stringf(");\n");
+ if (!systemverilog && !module->processes.empty())
+ f << indent + " " << "reg " << id("\\initial") << " = 0;\n";
+
for (auto w : module->wires())
dump_wire(f, indent + " ", w);