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-rw-r--r--CHANGELOG3
1 files changed, 2 insertions, 1 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 12fc88550..08af3f4c9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -39,7 +39,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Improvements in pmgen: slices, choices, define, generate
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
- - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
+ - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added "-match-init" option to "dff2dffs" pass
- Added "techmap_autopurge" support to techmap
- Added "add -mod <modname[s]>"
@@ -69,6 +69,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added $divfloor and $modfloor cells
- Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
- Added "dfflegalize" pass
+ - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
Yosys 0.8 .. Yosys 0.9
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