diff options
| -rw-r--r-- | passes/pmgen/Makefile.inc | 2 | ||||
| -rw-r--r-- | passes/pmgen/peepopt.cc | 2 | ||||
| -rw-r--r-- | passes/pmgen/peepopt_dffmux.pmg | 89 | ||||
| -rw-r--r-- | passes/pmgen/peepopt_dffmuxext.pmg | 55 | ||||
| -rw-r--r-- | tests/various/peepopt.ys | 19 |
5 files changed, 109 insertions, 58 deletions
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index fcbaa99ed..21f29a49a 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -33,7 +33,7 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h)) PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg -PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmuxext.pmg +PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) $(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index b57d26cef..72b02127a 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -60,7 +60,7 @@ struct PeepoptPass : public Pass { peepopt_pm pm(module, module->selected_cells()); pm.run_shiftmul(); pm.run_muldiv(); - pm.run_dffmuxext(); + pm.run_dffmux(); } } } diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg new file mode 100644 index 000000000..4fc8e3b4c --- /dev/null +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -0,0 +1,89 @@ +pattern dffmux + +state <IdString> muxAB + +match dff + select dff->type == $dff + select GetSize(port(dff, \D)) > 1 +endmatch + +match mux + select mux->type == $mux + select GetSize(port(mux, \Y)) > 1 + choice <IdString> AB {\A, \B} + //select port(mux, AB)[GetSize(port(mux, \Y))-1].wire + index <SigSpec> port(mux, \Y) === port(dff, \D) + define <IdString> BA (AB == \A ? \B : \A) + index <SigSpec> port(mux, BA) === port(dff, \Q) + set muxAB AB +endmatch + +code + SigSpec &D = mux->connections_.at(muxAB); + SigSpec &Q = dff->connections_.at(\Q); + int width = GetSize(D); + + SigSpec AB = port(mux, muxAB); + if (AB[width-1] == AB[width-2]) { + did_something = true; + + SigBit sign = D[width-1]; + bool is_signed = sign.wire; + int i; + for (i = width-1; i >= 2; i--) { + if (!is_signed) { + module->connect(Q[i], sign); + if (D[i-1] != sign) + break; + } + else { + module->connect(Q[i], Q[i-1]); + if (D[i-2] != sign) + break; + } + } + + mux->connections_.at(\A).remove(i, width-i); + mux->connections_.at(\B).remove(i, width-i); + mux->connections_.at(\Y).remove(i, width-i); + mux->fixup_parameters(); + dff->connections_.at(\D).remove(i, width-i); + dff->connections_.at(\Q).remove(i, width-i); + dff->fixup_parameters(); + + log("dffmux pattern in %s: dff=%s, mux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(mux), width-i); + accept; + } + else { + int count = 0; + for (int i = width-1; i >= 0; i--) { + if (AB[i].wire) + continue; + Wire *w = Q[i].wire; + auto it = w->attributes.find(\init); + State init; + if (it != w->attributes.end()) + init = it->second[Q[i].offset]; + else + init = State::Sx; + + if (init == State::Sx || init == AB[i].data) { + count++; + module->connect(Q[i], AB[i]); + mux->connections_.at(\A).remove(i); + mux->connections_.at(\B).remove(i); + mux->connections_.at(\Y).remove(i); + dff->connections_.at(\D).remove(i); + dff->connections_.at(\Q).remove(i); + } + } + if (count > 0) { + did_something = true; + mux->fixup_parameters(); + dff->fixup_parameters(); + } + + log("dffmux pattern in %s: dff=%s, mux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(mux), count); + accept; + } +endcode diff --git a/passes/pmgen/peepopt_dffmuxext.pmg b/passes/pmgen/peepopt_dffmuxext.pmg deleted file mode 100644 index 2465d6171..000000000 --- a/passes/pmgen/peepopt_dffmuxext.pmg +++ /dev/null @@ -1,55 +0,0 @@ -pattern dffmuxext - -state <IdString> muxAB - -match dff - select dff->type == $dff - select GetSize(port(dff, \D)) > 1 -endmatch - -match mux - select mux->type == $mux - select GetSize(port(mux, \Y)) > 1 - choice <IdString> AB {\A, \B} - //select port(mux, AB)[GetSize(port(mux, \Y))-1].wire - index <SigSpec> port(mux, \Y) === port(dff, \D) - define <IdString> BA (AB == \A ? \B : \A) - index <SigSpec> port(mux, BA) === port(dff, \Q) - filter port(mux, AB)[GetSize(port(mux, \Y))-1] == port(mux, AB)[GetSize(port(mux, \Y))-2] - set muxAB AB -endmatch - -code - did_something = true; - - SigSpec &D = mux->connections_.at(muxAB); - SigSpec &Q = dff->connections_.at(\Q); - int width = GetSize(D); - - SigBit sign = D[width-1]; - bool is_signed = sign.wire; - int i; - for (i = width-1; i >= 2; i--) { - if (!is_signed) { - module->connect(Q[i], sign); - if (D[i-1] != sign) - break; - } - else { - module->connect(Q[i], Q[i-1]); - if (D[i-2] != sign) - break; - } - } - - mux->connections_.at(\A).remove(i, width-i); - mux->connections_.at(\B).remove(i, width-i); - mux->connections_.at(\Y).remove(i, width-i); - mux->fixup_parameters(); - dff->connections_.at(\D).remove(i, width-i); - dff->connections_.at(\Q).remove(i, width-i); - dff->fixup_parameters(); - - log("dffmuxext pattern in %s: dff=%s, mux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(mux), width-i); - accept; -endcode diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 33555264d..2a660d5c9 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -49,12 +49,29 @@ select -assert-count 0 t:* design -reset read_verilog <<EOT +module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +clean +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); always @(posedge clk) if (ce) o <= i; endmodule EOT -prep -nokeepdc +proc equiv_opt -assert peepopt design -load postopt clean |