diff options
| -rw-r--r-- | techlibs/ice40/brams.txt | 59 | ||||
| -rw-r--r-- | tests/arch/common/blockram.v | 42 | ||||
| -rw-r--r-- | tests/arch/common/blockrom.v | 31 | ||||
| -rw-r--r-- | tests/arch/ice40/memories.ys | 126 |
4 files changed, 238 insertions, 20 deletions
diff --git a/techlibs/ice40/brams.txt b/techlibs/ice40/brams.txt index 03d596111..d51c7119a 100644 --- a/techlibs/ice40/brams.txt +++ b/techlibs/ice40/brams.txt @@ -28,13 +28,72 @@ bram $__ICE40_RAM4K_M123 clkpol 2 3 endbram +# The syn_* attributes are described in: +# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx + match $__ICE40_RAM4K_M0 + # implicitly requested RAM or ROM + attribute !syn_ramstyle syn_ramstyle=auto + attribute !syn_romstyle syn_romstyle=auto + attribute !ram_block + attribute !rom_block + attribute !logic_block min efficiency 2 make_transp or_next_if_better endmatch +match $__ICE40_RAM4K_M0 + # explicitly requested RAM + attribute syn_ramstyle=block_ram ram_block + attribute !syn_romstyle + attribute !rom_block + attribute !logic_block + min wports 1 + make_transp + or_next_if_better +endmatch + +match $__ICE40_RAM4K_M0 + # explicitly requested ROM + attribute syn_romstyle=ebr rom_block + attribute !syn_ramstyle + attribute !ram_block + attribute !logic_block + max wports 0 + make_transp + or_next_if_better +endmatch + match $__ICE40_RAM4K_M123 + # implicitly requested RAM or ROM + attribute !syn_ramstyle syn_ramstyle=auto + attribute !syn_romstyle syn_romstyle=auto + attribute !ram_block + attribute !rom_block + attribute !logic_block min efficiency 2 make_transp + or_next_if_better +endmatch + +match $__ICE40_RAM4K_M123 + # explicitly requested RAM + attribute syn_ramstyle=block_ram ram_block + attribute !syn_romstyle + attribute !rom_block + attribute !logic_block + min wports 1 + make_transp + or_next_if_better +endmatch + +match $__ICE40_RAM4K_M123 + # explicitly requested ROM + attribute syn_romstyle=ebr rom_block + attribute !syn_ramstyle + attribute !ram_block + attribute !logic_block + max wports 0 + make_transp endmatch diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index dbc6ca65c..5ed0736d0 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -5,19 +5,20 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); - reg [WORD:0] data_out_r; - reg [WORD:0] memory [0:DEPTH]; + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; - always @(posedge clk) begin - if (write_enable) - memory[address_in] <= data_in; - data_out_r <= memory[address_in]; - end + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; - assign data_out = data_out_r; endmodule // sync_ram_sp @@ -28,18 +29,19 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, output wire [DATA_WIDTH-1:0] data_out); - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; - reg [WORD:0] data_out_r; - reg [WORD:0] memory [0:DEPTH]; + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r <= memory[address_in_r]; + end - always @(posedge clk) begin - if (write_enable) - memory[address_in_w] <= data_in; - data_out_r <= memory[address_in_r]; - end + assign data_out = data_out_r; - assign data_out = data_out_r; endmodule // sync_ram_sdp diff --git a/tests/arch/common/blockrom.v b/tests/arch/common/blockrom.v new file mode 100644 index 000000000..6f6c9d946 --- /dev/null +++ b/tests/arch/common/blockrom.v @@ -0,0 +1,31 @@ +`default_nettype none +module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + integer i,j = 16'hACE1; + initial + for (i = 0; i <= DEPTH; i++) begin + // In case this ROM will be implemented in fabric: fill the memory with some data + // uncorrelated with the address, or Yosys might see through the ruse and e.g. not + // emit any LUTs at all for `memory[i] = i;`, just a latch. + memory[i] = j; + j = j ^ (j >> 7); + j = j ^ (j << 9); + j = j ^ (j >> 13); + end + + always @(posedge clk) begin + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; + +endmodule // sync_rom diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys new file mode 100644 index 000000000..83386f0ec --- /dev/null +++ b/tests/arch/ice40/memories.ys @@ -0,0 +1,126 @@ +# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +## With parameters + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # too inefficient +select -assert-min 1 t:SB_DFFE + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "block_ram" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set ram_block 1 m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set logic_block 1 m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly +select -assert-min 1 t:SB_DFFE + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_romstyle "ebr" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM +select -assert-min 1 t:SB_DFFE + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set rom_block 1 m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM +select -assert-min 1 t:SB_DFFE + +# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +## With parameters + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +write_ilang +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # too inefficient +select -assert-min 1 t:SB_LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_romstyle "ebr" m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set rom_block 1 m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set logic_block 1 m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly +select -assert-min 1 t:SB_LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_ramstyle "block_ram" m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM +select -assert-min 1 t:SB_LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set ram_block 1 m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM +select -assert-min 1 t:SB_LUT4 |