diff options
| -rw-r--r-- | kernel/celltypes.h | 1 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 8 | ||||
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 | ||||
| -rw-r--r-- | techlibs/common/simlib.v | 24 |
4 files changed, 33 insertions, 2 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 3a56de2f7..60e6606f8 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -114,6 +114,7 @@ struct CellTypes setup_type("$fa", {A, B, C}, {X, Y}, true); setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true); + setup_type("$equiv", {A, B}, {Y}, true); } void setup_internals_mem() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b35cbc3d1..ec61cb529 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -905,6 +905,14 @@ namespace { return; } + if (cell->type == "$equiv") { + port("\\A", 1); + port("\\B", 1); + port("\\Y", 1); + check_expected(); + return; + } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index c12d8734e..43d40c73f 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -417,7 +417,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert} cells. +Add information about {\tt \$assert} and {\tt \$equiv} cells. \end{fixme} \begin{fixme} diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index f16bd6bd2..d0feadd81 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1160,12 +1160,34 @@ module \$assert (A, EN); input A, EN; +`ifndef SIMLIB_NOCHECKS always @* begin if (A !== 1'b1 && EN === 1'b1) begin $display("Assertation failed!"); - $finish; + $stop; + end +end +`endif + +endmodule + +// -------------------------------------------------------- + +module \$equiv (A, B, Y); + +input A, B; +output Y; + +assign Y = (A !== 1'bx && A !== B) ? 1'bx : A; + +`ifndef SIMLIB_NOCHECKS +always @* begin + if (A !== 1'bx && A !== B) begin + $display("Equivalence failed!"); + $stop; end end +`endif endmodule |