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-rw-r--r--techlibs/xilinx/abc9_model.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 204fa883f..15d12c89f 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -42,7 +42,7 @@ endmodule
// Box to emulate async behaviour of FDP*
(* abc9_box_id = 1001, lib_whitebox *)
module \$__ABC9_ASYNC1 (input A, S, output Y);
- assign Y = S ? 1'b0 : A;
+ assign Y = S ? 1'b1 : A;
endmodule
// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}