diff options
| -rw-r--r-- | passes/opt/opt_const.cc | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index a3f3ee418..84285567e 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -160,19 +160,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons assert(a.chunks.size() == b.chunks.size()); for (size_t i = 0; i < a.chunks.size(); i++) { - if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL && - a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0]) { + if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL && a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0] && + a.chunks[i].data.bits[0] <= RTLIL::State::S1 && b.chunks[i].data.bits[0] <= RTLIL::State::S1) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (cell->type == "$eq" || cell->type == "$ne") { - if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1) - continue; - if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1) - continue; - } if (a.chunks[i] == b.chunks[i]) continue; new_a.append(a.chunks[i]); |