diff options
| -rw-r--r-- | passes/memory/memory_dff.cc | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 40691d160..6e036397d 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -33,8 +33,20 @@ struct MemoryDffWorker dict<SigBit, int> sigbit_users_count; dict<SigSpec, Cell*> mux_cells_a, mux_cells_b; pool<Cell*> forward_merged_dffs, candidate_dffs; + pool<SigBit> init_bits; - MemoryDffWorker(Module *module) : module(module), sigmap(module) { } + MemoryDffWorker(Module *module) : module(module), sigmap(module) + { + for (auto wire : module->wires()) { + if (wire->attributes.count("\\init") == 0) + continue; + SigSpec sig = sigmap(wire); + Const initval = wire->attributes.count("\\init"); + for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++) + if (initval[i] == State::S0 || initval[i] == State::S1) + init_bits.insert(sig[i]); + } + } bool find_sig_before_dff(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) { @@ -45,6 +57,9 @@ struct MemoryDffWorker if (bit.wire == NULL) continue; + if (!after && init_bits.count(sigmap(bit))) + return false; + for (auto cell : dff_cells) { if (after && forward_merged_dffs.count(cell)) @@ -72,6 +87,9 @@ struct MemoryDffWorker if (d.size() != 1) continue; + if (after && init_bits.count(d)) + return false; + bit = d; clk = this_clk; clk_polarity = this_clk_polarity; |