diff options
| -rw-r--r-- | tests/ice40/mul.v | 7 | ||||
| -rw-r--r-- | tests/ice40/mul.ys | 7 |
2 files changed, 6 insertions, 8 deletions
diff --git a/tests/ice40/mul.v b/tests/ice40/mul.v index c099db0d9..d5b48b1d7 100644 --- a/tests/ice40/mul.v +++ b/tests/ice40/mul.v @@ -1,10 +1,9 @@ module top ( - input [3:0] x, - input [3:0] y, + input [5:0] x, + input [5:0] y, - output [3:0] A, - output [3:0] B + output [11:0] A, ); assign A = x * y; diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index 35048d14a..adf1b3211 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,9 +1,8 @@ read_verilog mul.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +#synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 15 t:SB_LUT4 -select -assert-count 3 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D |