diff options
| -rw-r--r-- | passes/pmgen/peepopt_dffmux.pmg | 72 | ||||
| -rw-r--r-- | tests/various/peepopt.ys | 71 |
2 files changed, 116 insertions, 27 deletions
diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index 4fc8e3b4c..60a708616 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -1,30 +1,48 @@ pattern dffmux -state <IdString> muxAB +state <IdString> cemuxAB rstmuxBA +state <SigSpec> sigD match dff select dff->type == $dff select GetSize(port(dff, \D)) > 1 endmatch -match mux - select mux->type == $mux - select GetSize(port(mux, \Y)) > 1 +match rstmux + select rstmux->type == $mux + select GetSize(port(rstmux, \Y)) > 1 + index <SigSpec> port(rstmux, \Y) === port(dff, \D) + choice <IdString> BA {\B, \A} + select port(rstmux, BA).is_fully_const() + set rstmuxBA BA + optional +endmatch + +code sigD + if (rstmux) + sigD = port(rstmux, rstmuxBA == \B ? \A : \B); + else + sigD = port(dff, \D); +endcode + +match cemux + select cemux->type == $mux + select GetSize(port(cemux, \Y)) > 1 + index <SigSpec> port(cemux, \Y) === sigD choice <IdString> AB {\A, \B} - //select port(mux, AB)[GetSize(port(mux, \Y))-1].wire - index <SigSpec> port(mux, \Y) === port(dff, \D) - define <IdString> BA (AB == \A ? \B : \A) - index <SigSpec> port(mux, BA) === port(dff, \Q) - set muxAB AB + index <SigSpec> port(cemux, AB) === port(dff, \Q) + set cemuxAB AB endmatch code - SigSpec &D = mux->connections_.at(muxAB); + SigSpec &D = cemux->connections_.at(cemuxAB == \A ? \B : \A); SigSpec &Q = dff->connections_.at(\Q); + Const rst; + if (rstmux) + rst = port(rstmux, rstmuxBA).as_const(); int width = GetSize(D); - SigSpec AB = port(mux, muxAB); - if (AB[width-1] == AB[width-2]) { + if (D[width-1] == D[width-2]) { did_something = true; SigBit sign = D[width-1]; @@ -33,31 +51,31 @@ code for (i = width-1; i >= 2; i--) { if (!is_signed) { module->connect(Q[i], sign); - if (D[i-1] != sign) + if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1])) break; } else { module->connect(Q[i], Q[i-1]); - if (D[i-2] != sign) + if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1])) break; } } - mux->connections_.at(\A).remove(i, width-i); - mux->connections_.at(\B).remove(i, width-i); - mux->connections_.at(\Y).remove(i, width-i); - mux->fixup_parameters(); + cemux->connections_.at(\A).remove(i, width-i); + cemux->connections_.at(\B).remove(i, width-i); + cemux->connections_.at(\Y).remove(i, width-i); + cemux->fixup_parameters(); dff->connections_.at(\D).remove(i, width-i); dff->connections_.at(\Q).remove(i, width-i); dff->fixup_parameters(); - log("dffmux pattern in %s: dff=%s, mux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(mux), width-i); + log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i); accept; } else { int count = 0; for (int i = width-1; i >= 0; i--) { - if (AB[i].wire) + if (D[i].wire) continue; Wire *w = Q[i].wire; auto it = w->attributes.find(\init); @@ -67,23 +85,23 @@ code else init = State::Sx; - if (init == State::Sx || init == AB[i].data) { + if (init == State::Sx || init == D[i].data) { count++; - module->connect(Q[i], AB[i]); - mux->connections_.at(\A).remove(i); - mux->connections_.at(\B).remove(i); - mux->connections_.at(\Y).remove(i); + module->connect(Q[i], D[i]); + cemux->connections_.at(\A).remove(i); + cemux->connections_.at(\B).remove(i); + cemux->connections_.at(\Y).remove(i); dff->connections_.at(\D).remove(i); dff->connections_.at(\Q).remove(i); } } if (count > 0) { did_something = true; - mux->fixup_parameters(); + cemux->fixup_parameters(); dff->fixup_parameters(); + log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count); } - log("dffmux pattern in %s: dff=%s, mux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(mux), count); accept; } endcode diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 2a660d5c9..886c8cd9d 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -78,3 +78,74 @@ clean select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 1 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$dff t:$mux %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +select -assert-count 1 t:$dff r:WIDTH=5 %i +select -assert-count 1 t:$mux r:WIDTH=5 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +wreduce +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) begin + if (ce) o <= i; + if (!rstn) o <= 4'b1111; + end +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +wreduce +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D |