diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | backends/json/json.cc | 4 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 7 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 56 |
4 files changed, 65 insertions, 4 deletions
@@ -86,7 +86,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = a4872e22c646 +ABCREV = 55cd83f432c0 ABCPULL = 1 ABCURL ?= https://bitbucket.org/alanmi/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" diff --git a/backends/json/json.cc b/backends/json/json.cc index 4baffa33e..f3969d0e6 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -333,6 +333,10 @@ struct JsonBackend : public Backend { log("connected to a constant driver are denoted as string \"0\" or \"1\" instead of\n"); log("a number.\n"); log("\n"); + log("Numeric parameter and attribute values up to 32 bits are written as decimal\n"); + log("values. Numbers larger than that are written as string holding the binary\n"); + log("representation of the value.\n"); + log("\n"); log("For example the following Verilog code:\n"); log("\n"); log(" module test(input x, y);\n"); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7693e3052..40ad8ca13 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2766,10 +2766,11 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe other->unpack(); } - for (int i = GetSize(bits_) - 1; i >= 0; i--) { + for (int i = GetSize(bits_) - 1; i >= 0; i--) + { if (bits_[i].wire == NULL) continue; - for (auto &pattern_chunk : pattern.chunks()) { + for (auto &pattern_chunk : pattern.chunks()) if (bits_[i].wire == pattern_chunk.wire && bits_[i].offset >= pattern_chunk.offset && bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) { @@ -2779,8 +2780,8 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe other->bits_.erase(other->bits_.begin() + i); other->width_--; } + break; } - } } check(); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 376df5698..337af7fd7 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -367,6 +367,11 @@ struct HierarchyPass : public Pass { log(" per default this pass also converts positional arguments in cells\n"); log(" to arguments using port names. this option disables this behavior.\n"); log("\n"); + log(" -keep_portwidths\n"); + log(" per default this pass adjusts the port width on cells that are\n"); + log(" module instances when the width does not match the module port. this\n"); + log(" option disables this behavior.\n"); + log("\n"); log(" -nokeep_asserts\n"); log(" per default this pass sets the \"keep\" attribute on all modules\n"); log(" that directly or indirectly contain one or more $assert cells. this\n"); @@ -412,6 +417,7 @@ struct HierarchyPass : public Pass { bool auto_top_mode = false; bool generate_mode = false; bool keep_positionals = false; + bool keep_portwidths = false; bool nokeep_asserts = false; std::vector<std::string> generate_cells; std::vector<generate_port_decl_t> generate_ports; @@ -470,6 +476,10 @@ struct HierarchyPass : public Pass { keep_positionals = true; continue; } + if (args[argidx] == "-keep_portwidths") { + keep_portwidths = true; + continue; + } if (args[argidx] == "-nokeep_asserts") { nokeep_asserts = true; continue; @@ -614,6 +624,52 @@ struct HierarchyPass : public Pass { } } + if (!keep_portwidths) + { + for (auto module : design->modules()) + for (auto cell : module->cells()) + { + Module *m = design->module(cell->type); + + if (m == nullptr) + continue; + + for (auto &conn : cell->connections()) + { + Wire *w = m->wire(conn.first); + + if (w == nullptr || w->port_id == 0) + continue; + + if (GetSize(w) == GetSize(conn.second)) + continue; + + SigSpec sig = conn.second; + + if (GetSize(w) < GetSize(conn.second)) + { + int n = GetSize(conn.second) - GetSize(w); + if (!w->port_input && w->port_output) + module->connect(sig.extract(GetSize(w), n), Const(0, n)); + sig.remove(GetSize(w), n); + } + else + { + int n = GetSize(w) - GetSize(conn.second); + if (w->port_input && !w->port_output) + sig.append(Const(0, n)); + else + sig.append(module->addWire(NEW_ID, n)); + } + + if (!conn.second.is_fully_const() || !w->port_input || w->port_output) + log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell), + log_id(conn.first), GetSize(conn.second), GetSize(sig)); + cell->setPort(conn.first, sig); + } + } + } + log_pop(); } } HierarchyPass; |