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-rw-r--r--passes/techmap/abc.cc4
-rw-r--r--techlibs/ice40/abc_hx.box12
-rw-r--r--techlibs/ice40/abc_lp.box12
-rw-r--r--techlibs/ice40/abc_u.box14
-rw-r--r--techlibs/ice40/arith_map.v10
-rw-r--r--techlibs/ice40/cells_map.v24
-rw-r--r--techlibs/ice40/cells_sim.v27
-rw-r--r--techlibs/ice40/ice40_opt.cc45
-rw-r--r--techlibs/ice40/synth_ice40.cc5
9 files changed, 122 insertions, 31 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 15e79f9d1..65c7d1bb8 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
continue;
}
}
-
- cell_stats[RTLIL::unescape_id(c->type)]++;
+ else
+ cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
RTLIL::SigSig conn;
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index f8e12b527..c0ea742e2 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,15 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_FULL_ADDER 1 1 3 2
+400 379 316
259 231 126
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index fbe4c56e6..d73b6d649 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,15 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: CI I0 I1
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_FULL_ADDER 1 1 3 2
+589 558 465
675 609 186
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index f44deabc4..42d666051 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,15 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
-675 609 278
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
+$__ICE40_FULL_ADDER 1 1 3 2
+1231 1205 874
+675 609 278
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,6 +44,15 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+`ifdef _ABC
+ \$__ICE40_FULL_ADDER carry (
+ .A(AA[i]),
+ .B(BB[i]),
+ .CI(C[i]),
+ .CO(CO[i]),
+ .O(Y[i])
+ );
+`else
SB_CARRY carry (
.I0(AA[i]),
.I1(BB[i]),
@@ -63,6 +72,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
.I3(C[i]),
.O(Y[i])
);
+`endif
end endgenerate
assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 759549e30..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -61,3 +61,27 @@ module \$lut (A, Y);
endgenerate
endmodule
`endif
+
+`ifdef _ABC
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+ SB_CARRY carry (
+ .I0(A),
+ .I1(B),
+ .CI(CI),
+ .CO(CO)
+ );
+ SB_LUT4 #(
+ // I0: 1010 1010 1010 1010
+ // I1: 1100 1100 1100 1100
+ // I2: 1111 0000 1111 0000
+ // I3: 1111 1111 0000 0000
+ .LUT_INIT(16'b 0110_1001_1001_0110)
+ ) adder (
+ .I0(1'b0),
+ .I1(A),
+ .I2(B),
+ .I3(CI),
+ .O(O)
+ );
+endmodule
+`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b746ba4e5..609facc93 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
// SiliconBlue Logic Cells
-(* abc_box_id = 2, lib_whitebox *)
+(* lib_whitebox *)
module SB_LUT4 (output O, input I0, I1, I2, I3);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,11 +136,34 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
assign O = I0 ? s1[1] : s1[0];
endmodule
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+(* lib_whitebox *)
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+ SB_CARRY carry (
+ .I0(A),
+ .I1(B),
+ .CI(CI),
+ .CO(CO)
+ );
+ SB_LUT4 #(
+ // I0: 1010 1010 1010 1010
+ // I1: 1100 1100 1100 1100
+ // I2: 1111 0000 1111 0000
+ // I3: 1111 1111 0000 0000
+ .LUT_INIT(16'b 0110_1001_1001_0110)
+ ) adder (
+ .I0(1'b0),
+ .I1(A),
+ .I2(B),
+ .I3(CI),
+ .O(O)
+ );
+endmodule
+
// Positive Edge SiliconBlue FF Cells
module SB_DFF (output `SB_DFF_REG, input C, D);
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..e492454fb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,51 @@ static void run_ice40_opts(Module *module)
}
continue;
}
+
+ if (cell->type == "$__ICE40_FULL_ADDER")
+ {
+ SigSpec non_const_inputs, replacement_output;
+ int count_zeros = 0, count_ones = 0;
+
+ SigBit inbit[3] = {
+ cell->getPort("\\A"),
+ cell->getPort("\\B"),
+ cell->getPort("\\CI")
+ };
+ for (int i = 0; i < 3; i++)
+ if (inbit[i].wire == nullptr) {
+ if (inbit[i] == State::S1)
+ count_ones++;
+ else
+ count_zeros++;
+ } else
+ non_const_inputs.append(inbit[i]);
+
+ if (count_zeros >= 2)
+ replacement_output = State::S0;
+ else if (count_ones >= 2)
+ replacement_output = State::S1;
+ else if (GetSize(non_const_inputs) == 1)
+ replacement_output = non_const_inputs;
+
+ if (GetSize(replacement_output)) {
+ optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+ module->connect(cell->getPort("\\CO")[0], replacement_output);
+ module->design->scratchpad_set_bool("opt.did_something", true);
+ log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+ log_id(module), log_id(cell), log_signal(replacement_output));
+ cell->type = "$lut";
+ cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
+ cell->setPort("\\Y", cell->getPort("\\O"));
+ cell->unsetPort("\\B");
+ cell->unsetPort("\\CI");
+ cell->unsetPort("\\CO");
+ cell->unsetPort("\\O");
+ cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+ cell->setParam("\\WIDTH", 4);
+ }
+ continue;
+ }
}
for (auto cell : sb_lut_cells)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 0474e76e9..b3d30791a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
+ run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@@ -294,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass
if (nocarry)
run("techmap");
else
- run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+ run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
if (retime || help_mode)
run(abc + " -dff", "(only if -retime)");
run("ice40_opt");
@@ -338,6 +338,7 @@ struct SynthIce40Pass : public ScriptPass
else
wire_delay = 250;
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+ run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
}
else
run(abc + " -dress -lut 4", "(skip if -noabc)");
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-12 16:46:51 +0000