diff options
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 8e3691b34..2921c92d8 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -54,7 +54,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; - if (wire->port_output) { + if (wire->port_output || wire->get_bool_attribute("\\keep")) { std::set<RTLIL::Cell*> cell_list; RTLIL::SigSpec sig = RTLIL::SigSpec(wire); assign_map.apply(sig); |