diff options
| -rw-r--r-- | passes/techmap/dfflegalize.cc | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 013f2d974..7f2cdc6ac 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -111,31 +111,31 @@ struct DffLegalizePass : public Pass { log("- $_DLATCHSR_[NP][NP][NP]_\n"); log("\n"); log("The following transformations are performed by this pass:"); - log(""); + log("\n"); log("- upconversion from a less capable cell to a more capable cell, if the less"); log(" capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)"); - log(""); + log("\n"); log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)"); - log(""); + log("\n"); log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)"); - log(""); + log("\n"); log("- adding inverters on the control pins (due to unsupported polarity)"); - log(""); + log("\n"); log("- adding inverters on the D and Q pins and inverting the init/reset values\n"); log(" (due to unsupported init or reset value)"); - log(""); + log("\n"); log("- converting sr into adlatch (by tying D to 1 and using E as set input)"); - log(""); + log("\n"); log("- emulating unsupported dffsr cell by adff + adff + sr + mux"); - log(""); + log("\n"); log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux"); - log(""); + log("\n"); log("- emulating adff when the (reset, init) value combination is unsupported by\n"); log(" dff + adff + dlatch + mux"); - log(""); + log("\n"); log("- emulating adlatch when the (reset, init) value combination is unsupported by\n"); log("- dlatch + adlatch + dlatch + mux"); - log(""); + log("\n"); log("If the pass is unable to realize a given cell type (eg. adff when only plain dff"); log("is available), an error is raised."); } |