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-rw-r--r--techlibs/ice40/cells_sim.v86
-rwxr-xr-xtests/arch/run-test.sh2
2 files changed, 62 insertions, 26 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 7ee809262..bde3c1a87 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,12 +2,22 @@
`define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q
+`ifndef NO_ICE40_DEFAULT_ASSIGNMENTS
+`define ICE40_DEFAULT_ASSIGNMENT_V(v) = v
+`define ICE40_DEFAULT_ASSIGNMENT_0 = 1'b0
+`define ICE40_DEFAULT_ASSIGNMENT_1 = 1'b1
+`else
+`define ICE40_DEFAULT_ASSIGNMENT_V(v)
+`define ICE40_DEFAULT_ASSIGNMENT_0
+`define ICE40_DEFAULT_ASSIGNMENT_1
+`endif
+
// SiliconBlue IO Cells
module SB_IO (
inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
- input CLOCK_ENABLE,
+ input CLOCK_ENABLE `ICE40_DEFAULT_ASSIGNMENT_1,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
@@ -114,7 +124,7 @@ module SB_GB_IO (
inout PACKAGE_PIN,
output GLOBAL_BUFFER_OUTPUT,
input LATCH_INPUT_VALUE,
- input CLOCK_ENABLE,
+ input CLOCK_ENABLE `ICE40_DEFAULT_ASSIGNMENT_1,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
@@ -164,7 +174,13 @@ endmodule
// SiliconBlue Logic Cells
(* abc9_lut=1, lib_whitebox *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
+module SB_LUT4 (
+ output O,
+ input I0 `ICE40_DEFAULT_ASSIGNMENT_0,
+ input I1 `ICE40_DEFAULT_ASSIGNMENT_0,
+ input I2 `ICE40_DEFAULT_ASSIGNMENT_0,
+ input I3 `ICE40_DEFAULT_ASSIGNMENT_0
+);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
@@ -284,7 +300,7 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFE (
output `SB_DFF_REG,
- input C, E, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
);
always @(posedge C)
if (E)
@@ -561,7 +577,7 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESR (
output `SB_DFF_REG,
- input C, E, R, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
always @(posedge C)
if (E) begin
@@ -617,7 +633,7 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFER (
output `SB_DFF_REG,
- input C, E, R, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
always @(posedge C, posedge R)
if (R)
@@ -692,7 +708,7 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESS (
output `SB_DFF_REG,
- input C, E, S, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
always @(posedge C)
if (E) begin
@@ -748,7 +764,7 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFES (
output `SB_DFF_REG,
- input C, E, S, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
always @(posedge C, posedge S)
if (S)
@@ -861,7 +877,7 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNE (
output `SB_DFF_REG,
- input C, E, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
);
always @(negedge C)
if (E)
@@ -1138,7 +1154,7 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESR (
output `SB_DFF_REG,
- input C, E, R, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
always @(negedge C)
if (E) begin
@@ -1194,7 +1210,7 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNER (
output `SB_DFF_REG,
- input C, E, R, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
always @(negedge C, posedge R)
if (R)
@@ -1269,7 +1285,7 @@ endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESS (
output `SB_DFF_REG,
- input C, E, S, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
always @(negedge C)
if (E) begin
@@ -1325,7 +1341,7 @@ endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNES (
output `SB_DFF_REG,
- input C, E, S, D
+ input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
always @(negedge C, posedge S)
if (S)
@@ -1402,11 +1418,16 @@ endmodule
module SB_RAM40_4K (
output [15:0] RDATA,
- input RCLK, RCLKE, RE,
+ input RCLK,
+ input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
- input WCLK, WCLKE, WE,
+ input WCLK,
+ input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
- input [15:0] MASK, WDATA
+ input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
+ input [15:0] WDATA
);
// MODE 0: 256 x 16
// MODE 1: 512 x 8
@@ -1636,11 +1657,16 @@ endmodule
module SB_RAM40_4KNR (
output [15:0] RDATA,
- input RCLKN, RCLKE, RE,
+ input RCLKN,
+ input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
- input WCLK, WCLKE, WE,
+ input WCLK,
+ input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
- input [15:0] MASK, WDATA
+ input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
+ input [15:0] WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
@@ -1767,11 +1793,16 @@ endmodule
module SB_RAM40_4KNW (
output [15:0] RDATA,
- input RCLK, RCLKE, RE,
+ input RCLK,
+ input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
- input WCLKN, WCLKE, WE,
+ input WCLKN,
+ input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
- input [15:0] MASK, WDATA
+ input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
+ input [15:0] WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
@@ -1898,11 +1929,16 @@ endmodule
module SB_RAM40_4KNRNW (
output [15:0] RDATA,
- input RCLKN, RCLKE, RE,
+ input RCLKN,
+ input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
- input WCLKN, WCLKE, WE,
+ input WCLKN,
+ input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
+ input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
- input [15:0] MASK, WDATA
+ input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
+ input [15:0] WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index 170078a7f..5d923db56 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -11,7 +11,7 @@ for arch in ../../techlibs/*; do
if [ "${defines[$arch_name]}" ]; then
for def in ${defines[$arch_name]}; do
echo -n "Test $path -D$def ->"
- iverilog -t null -I$arch -D$def $path
+ iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
echo " ok"
done
else
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 19:14:38 +0000