diff options
| -rw-r--r-- | README | 3 | ||||
| -rw-r--r-- | passes/fsm/fsm_map.cc | 3 | ||||
| -rw-r--r-- | passes/memory/memory_share.cc | 13 |
3 files changed, 19 insertions, 0 deletions
@@ -268,6 +268,9 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by yosys to synthesize verilog functions and access arrays. +- The "onehot" attribute on wires mark them as onehot state register. This + is used for example for memory port sharing and set by the fsm_map pass. + - The "blackbox" attribute on modules is used to mark empty stub modules that have the same ports as the real thing but do not contain information on the internal configuration. This modules are only used by the synthesis diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index a260653fb..155801a3a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -224,6 +224,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } + if (encoding_is_onehot) + state_wire->set_bool_attribute("\\onehot"); + // generate next_state signal if (GetSize(fsm_data.state_table) == 1) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index ec8df7598..a2f89f6d9 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -544,6 +544,7 @@ struct MemoryShareWorker // create SAT representation of common input cone of all considered EN signals + pool<Wire*> one_hot_wires; std::set<RTLIL::Cell*> sat_cells; std::set<RTLIL::SigBit> bits_queue; std::map<int, int> port_to_sat_variable; @@ -560,6 +561,10 @@ struct MemoryShareWorker while (!bits_queue.empty()) { + for (auto bit : bits_queue) + if (bit.wire && bit.wire->get_bool_attribute("\\onehot")) + one_hot_wires.insert(bit.wire); + pool<ModWalker::PortBit> portbits; modwalker.get_drivers(portbits, bits_queue); bits_queue.clear(); @@ -572,6 +577,14 @@ struct MemoryShareWorker } } + for (auto wire : one_hot_wires) { + log(" Adding one-hot constraint for wire %s.\n", log_id(wire)); + vector<int> ez_wire_bits = satgen.importSigSpec(wire); + for (int i : ez_wire_bits) + for (int j : ez_wire_bits) + if (i != j) ez.assume(ez.NOT(i), j); + } + log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size())); for (auto cell : sat_cells) |