diff options
228 files changed, 9036 insertions, 7017 deletions
@@ -51,6 +51,10 @@ ifneq ($(wildcard Makefile.conf),) include Makefile.conf endif +ifeq ($(ENABLE_PYOSYS),1) +ENABLE_LIBYOSYS := 1 +endif + BINDIR := $(PREFIX)/bin LIBDIR := $(PREFIX)/lib DATDIR := $(PREFIX)/share/yosys @@ -115,7 +119,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.9+1706 +YOSYS_VER := 0.9+2406 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o @@ -529,6 +533,7 @@ $(eval $(call add_include_file,kernel/register.h)) $(eval $(call add_include_file,kernel/celltypes.h)) $(eval $(call add_include_file,kernel/celledges.h)) $(eval $(call add_include_file,kernel/consteval.h)) +$(eval $(call add_include_file,kernel/constids.inc)) $(eval $(call add_include_file,kernel/sigtools.h)) $(eval $(call add_include_file,kernel/modtools.h)) $(eval $(call add_include_file,kernel/macc.h)) @@ -716,6 +721,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/memories && bash run-test.sh $(ABCOPT) $(SEEDOPT) +cd tests/bram && bash run-test.sh $(SEEDOPT) +cd tests/various && bash run-test.sh + +cd tests/select && bash run-test.sh +cd tests/sat && bash run-test.sh +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT) +cd tests/svtypes && bash run-test.sh $(SEEDOPT) @@ -541,8 +541,6 @@ from SystemVerilog: SystemVerilog files being read into the same design afterwards. - typedefs are supported (including inside packages) - - type identifiers must currently be enclosed in (parentheses) when declaring - signals of that type (this is syntactically incorrect SystemVerilog) - type casts are currently not supported - enums are supported (including inside packages) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index a51e3648c..cac32a8da 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -126,9 +126,9 @@ struct AigerWriter for (auto wire : module->wires()) { - if (wire->attributes.count("\\init")) { + if (wire->attributes.count(ID::init)) { SigSpec initsig = sigmap(wire); - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++) if (initval[i] == State::S0 || initval[i] == State::S1) init_map[initsig[i]] = initval[i] == State::S1; @@ -169,31 +169,31 @@ struct AigerWriter for (auto cell : module->cells()) { - if (cell->type == "$_NOT_") + if (cell->type == ID($_NOT_)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; continue; } - if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_")) + if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_))) { - SigBit D = sigmap(cell->getPort("\\D").as_bit()); - SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); + SigBit D = sigmap(cell->getPort(ID::D).as_bit()); + SigBit Q = sigmap(cell->getPort(ID::Q).as_bit()); unused_bits.erase(D); undriven_bits.erase(Q); ff_map[Q] = D; continue; } - if (cell->type == "$_AND_") + if (cell->type == ID($_AND_)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit B = sigmap(cell->getPort("\\B").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit B = sigmap(cell->getPort(ID::B).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); @@ -201,66 +201,66 @@ struct AigerWriter continue; } - if (cell->type == "$initstate") + if (cell->type == ID($initstate)) { - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); undriven_bits.erase(Y); initstate_bits.insert(Y); continue; } - if (cell->type == "$assert") + if (cell->type == ID($assert)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); asserts.push_back(make_pair(A, EN)); continue; } - if (cell->type == "$assume") + if (cell->type == ID($assume)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); assumes.push_back(make_pair(A, EN)); continue; } - if (cell->type == "$live") + if (cell->type == ID($live)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); liveness.push_back(make_pair(A, EN)); continue; } - if (cell->type == "$fair") + if (cell->type == ID($fair)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit EN = sigmap(cell->getPort(ID::EN).as_bit()); unused_bits.erase(A); unused_bits.erase(EN); fairness.push_back(make_pair(A, EN)); continue; } - if (cell->type == "$anyconst") + if (cell->type == ID($anyconst)) { - for (auto bit : sigmap(cell->getPort("\\Y"))) { + for (auto bit : sigmap(cell->getPort(ID::Y))) { undriven_bits.erase(bit); ff_map[bit] = bit; } continue; } - if (cell->type == "$anyseq") + if (cell->type == ID($anyseq)) { - for (auto bit : sigmap(cell->getPort("\\Y"))) { + for (auto bit : sigmap(cell->getPort(ID::Y))) { undriven_bits.erase(bit); input_bits.insert(bit); } diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cde6d066a..3b51d8685 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -174,7 +174,7 @@ struct XAigerWriter undriven_bits.insert(bit); unused_bits.insert(bit); - bool scc = wire->attributes.count(ID(abc9_scc)); + bool scc = wire->attributes.count(ID::abc9_scc); if (wire->port_input || scc) input_bits.insert(bit); @@ -190,21 +190,21 @@ struct XAigerWriter for (auto cell : module->cells()) { if (!cell->has_keep_attr()) { - if (cell->type == "$_NOT_") + if (cell->type == ID($_NOT_)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); undriven_bits.erase(Y); not_map[Y] = A; continue; } - if (cell->type == "$_AND_") + if (cell->type == ID($_AND_)) { - SigBit A = sigmap(cell->getPort("\\A").as_bit()); - SigBit B = sigmap(cell->getPort("\\B").as_bit()); - SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); + SigBit A = sigmap(cell->getPort(ID::A).as_bit()); + SigBit B = sigmap(cell->getPort(ID::B).as_bit()); + SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); unused_bits.erase(A); unused_bits.erase(B); undriven_bits.erase(Y); @@ -212,13 +212,13 @@ struct XAigerWriter continue; } - if (cell->type == "$__ABC9_FF_" && + if (cell->type == ID($__ABC9_FF_) && // The presence of an abc9_mergeability attribute indicates // that we do want to pass this flop to ABC - cell->attributes.count("\\abc9_mergeability")) + cell->attributes.count(ID::abc9_mergeability)) { - SigBit D = sigmap(cell->getPort("\\D").as_bit()); - SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); + SigBit D = sigmap(cell->getPort(ID::D).as_bit()); + SigBit Q = sigmap(cell->getPort(ID::Q).as_bit()); unused_bits.erase(D); undriven_bits.erase(Q); alias_map[Q] = D; @@ -227,7 +227,7 @@ struct XAigerWriter continue; } - if (cell->type.in("$specify2", "$specify3", "$specrule")) + if (cell->type.in(ID($specify2), ID($specify3), ID($specrule))) continue; } @@ -239,7 +239,7 @@ struct XAigerWriter bool abc9_flop = false; if (!cell->has_keep_attr()) { - auto it = cell->attributes.find("\\abc9_box_seq"); + auto it = cell->attributes.find(ID::abc9_box_seq); if (it != cell->attributes.end()) { int abc9_box_seq = it->second.as_int(); if (GetSize(box_list) <= abc9_box_seq) @@ -247,7 +247,7 @@ struct XAigerWriter box_list[abc9_box_seq] = cell; // Only flop boxes may have arrival times // (all others are combinatorial) - abc9_flop = inst_module->get_bool_attribute("\\abc9_flop"); + abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop); if (!abc9_flop) continue; } @@ -315,7 +315,7 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); log_assert(box_module); - log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop")); + log_assert(box_module->attributes.count(ID::abc9_box_id) || box_module->get_bool_attribute(ID::abc9_flop)); auto r = box_ports.insert(cell->type); if (r.second) { @@ -325,7 +325,7 @@ struct XAigerWriter for (const auto &port_name : box_module->ports) { auto w = box_module->wire(port_name); log_assert(w); - if (w->get_bool_attribute("\\abc9_carry")) { + if (w->get_bool_attribute(ID::abc9_carry)) { if (w->port_input) { if (carry_in != IdString()) log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module)); @@ -381,7 +381,7 @@ struct XAigerWriter } // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box - if (box_module->get_bool_attribute("\\abc9_flop")) { + if (box_module->get_bool_attribute(ID::abc9_flop)) { SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str())); if (rhs.empty()) log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module)); @@ -437,7 +437,7 @@ struct XAigerWriter for (const auto &i : ff_bits) { const Cell *cell = i.second; - const SigBit &q = sigmap(cell->getPort("\\Q")); + const SigBit &q = sigmap(cell->getPort(ID::Q)); aig_m++, aig_i++; log_assert(!aig_map.count(q)); aig_map[q] = 2*aig_m; @@ -608,12 +608,12 @@ struct XAigerWriter // For flops only, create an extra 1-bit input that drives a new wire // called "<cell>.abc9_ff.Q" that is used below - if (box_module->get_bool_attribute("\\abc9_flop")) + if (box_module->get_bool_attribute(ID::abc9_flop)) box_inputs++; std::get<0>(v) = box_inputs; std::get<1>(v) = box_outputs; - std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int(); + std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int(); } write_h_buffer(std::get<0>(v)); @@ -635,11 +635,11 @@ struct XAigerWriter const SigBit &d = i.first; const Cell *cell = i.second; - int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int(); + int mergeability = cell->attributes.at(ID::abc9_mergeability).as_int(); log_assert(mergeability > 0); write_r_buffer(mergeability); - Const init = cell->attributes.at(ID(abc9_init), State::Sx); + Const init = cell->attributes.at(ID::abc9_init, State::Sx); log_assert(GetSize(init) == 1); if (init == State::S1) write_s_buffer(1); diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index b6e38c16c..b028df848 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -69,9 +69,9 @@ struct BlifDumper f(f), module(module), design(design), config(config), ct(design), sigmap(module) { for (Wire *wire : module->wires()) - if (wire->attributes.count("\\init")) { + if (wire->attributes.count(ID::init)) { SigSpec initsig = sigmap(wire); - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) switch (initval[i]) { case State::S0: @@ -138,9 +138,9 @@ struct BlifDumper { if (!config->gates_mode) return "subckt"; - if (!design->modules_.count(RTLIL::escape_id(cell_type))) + if (design->module(RTLIL::escape_id(cell_type)) == nullptr) return "gate"; - if (design->modules_.at(RTLIL::escape_id(cell_type))->get_blackbox_attribute()) + if (design->module(RTLIL::escape_id(cell_type))->get_blackbox_attribute()) return "gate"; return "subckt"; } @@ -148,7 +148,7 @@ struct BlifDumper void dump_params(const char *command, dict<IdString, Const> ¶ms) { for (auto ¶m : params) { - f << stringf("%s %s ", command, RTLIL::id2cstr(param.first)); + f << stringf("%s %s ", command, log_id(param.first)); if (param.second.flags & RTLIL::CONST_FLAG_STRING) { std::string str = param.second.decode_string(); f << stringf("\""); @@ -172,8 +172,7 @@ struct BlifDumper std::map<int, RTLIL::Wire*> inputs, outputs; - for (auto &wire_it : module->wires_) { - RTLIL::Wire *wire = wire_it.second; + for (auto wire : module->wires()) { if (wire->port_input) inputs[wire->port_id] = wire; if (wire->port_output) @@ -229,10 +228,8 @@ struct BlifDumper f << stringf(".names $undef\n"); } - for (auto &cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; - if (config->unbuf_types.count(cell->type)) { auto portnames = config->unbuf_types.at(cell->type); f << stringf(".names %s %s\n1 1\n", @@ -240,142 +237,142 @@ struct BlifDumper continue; } - if (!config->icells_mode && cell->type == "$_NOT_") { + if (!config->icells_mode && cell->type == ID($_NOT_)) { f << stringf(".names %s %s\n0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_AND_") { + if (!config->icells_mode && cell->type == ID($_AND_)) { f << stringf(".names %s %s %s\n11 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_OR_") { + if (!config->icells_mode && cell->type == ID($_OR_)) { f << stringf(".names %s %s %s\n1- 1\n-1 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_XOR_") { + if (!config->icells_mode && cell->type == ID($_XOR_)) { f << stringf(".names %s %s %s\n10 1\n01 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_NAND_") { + if (!config->icells_mode && cell->type == ID($_NAND_)) { f << stringf(".names %s %s %s\n0- 1\n-0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_NOR_") { + if (!config->icells_mode && cell->type == ID($_NOR_)) { f << stringf(".names %s %s %s\n00 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_XNOR_") { + if (!config->icells_mode && cell->type == ID($_XNOR_)) { f << stringf(".names %s %s %s\n11 1\n00 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_ANDNOT_") { + if (!config->icells_mode && cell->type == ID($_ANDNOT_)) { f << stringf(".names %s %s %s\n10 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_ORNOT_") { + if (!config->icells_mode && cell->type == ID($_ORNOT_)) { f << stringf(".names %s %s %s\n1- 1\n-0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_AOI3_") { + if (!config->icells_mode && cell->type == ID($_AOI3_)) { f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_OAI3_") { + if (!config->icells_mode && cell->type == ID($_OAI3_)) { f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_AOI4_") { + if (!config->icells_mode && cell->type == ID($_AOI4_)) { f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_OAI4_") { + if (!config->icells_mode && cell->type == ID($_OAI4_)) { f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_MUX_") { + if (!config->icells_mode && cell->type == ID($_MUX_)) { f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_NMUX_") { + if (!config->icells_mode && cell->type == ID($_NMUX_)) { f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n", - cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), - cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y"))); + cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), + cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_FF_") { - f << stringf(".latch %s %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), - cstr_init(cell->getPort("\\Q"))); + if (!config->icells_mode && cell->type == ID($_FF_)) { + f << stringf(".latch %s %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)), + cstr_init(cell->getPort(ID::Q))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_DFF_N_") { - f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), - cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q"))); + if (!config->icells_mode && cell->type == ID($_DFF_N_)) { + f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)), + cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_DFF_P_") { - f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), - cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q"))); + if (!config->icells_mode && cell->type == ID($_DFF_P_)) { + f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)), + cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_DLATCH_N_") { - f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), - cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q"))); + if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) { + f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)), + cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$_DLATCH_P_") { - f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), - cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q"))); + if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) { + f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)), + cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q))); goto internal_cell; } - if (!config->icells_mode && cell->type == "$lut") { + if (!config->icells_mode && cell->type == ID($lut)) { f << stringf(".names"); - auto &inputs = cell->getPort("\\A"); - auto width = cell->parameters.at("\\WIDTH").as_int(); + auto &inputs = cell->getPort(ID::A); + auto width = cell->parameters.at(ID::WIDTH).as_int(); log_assert(inputs.size() == width); for (int i = width-1; i >= 0; i--) f << stringf(" %s", cstr(inputs.extract(i, 1))); - auto &output = cell->getPort("\\Y"); + auto &output = cell->getPort(ID::Y); log_assert(output.size() == 1); f << stringf(" %s", cstr(output)); f << stringf("\n"); - RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); + RTLIL::SigSpec mask = cell->parameters.at(ID::LUT); for (int i = 0; i < (1 << width); i++) if (mask[i] == State::S1) { for (int j = width-1; j >= 0; j--) { @@ -386,18 +383,18 @@ struct BlifDumper goto internal_cell; } - if (!config->icells_mode && cell->type == "$sop") { + if (!config->icells_mode && cell->type == ID($sop)) { f << stringf(".names"); - auto &inputs = cell->getPort("\\A"); - auto width = cell->parameters.at("\\WIDTH").as_int(); - auto depth = cell->parameters.at("\\DEPTH").as_int(); - vector<State> table = cell->parameters.at("\\TABLE").bits; + auto &inputs = cell->getPort(ID::A); + auto width = cell->parameters.at(ID::WIDTH).as_int(); + auto depth = cell->parameters.at(ID::DEPTH).as_int(); + vector<State> table = cell->parameters.at(ID::TABLE).bits; while (GetSize(table) < 2*width*depth) table.push_back(State::S0); log_assert(inputs.size() == width); for (int i = 0; i < width; i++) f << stringf(" %s", cstr(inputs.extract(i, 1))); - auto &output = cell->getPort("\\Y"); + auto &output = cell->getPort(ID::Y); log_assert(output.size() == 1); f << stringf(" %s", cstr(output)); f << stringf("\n"); @@ -649,25 +646,24 @@ struct BlifBackend : public Backend { extra_args(f, filename, args, argidx); if (top_module_name.empty()) - for (auto & mod_it:design->modules_) - if (mod_it.second->get_bool_attribute("\\top")) - top_module_name = mod_it.first.str(); + for (auto module : design->modules()) + if (module->get_bool_attribute(ID::top)) + top_module_name = module->name.str(); *f << stringf("# Generated by %s\n", yosys_version_str); std::vector<RTLIL::Module*> mod_list; design->sort(); - for (auto module_it : design->modules_) + for (auto module : design->modules()) { - RTLIL::Module *module = module_it.second; if (module->get_blackbox_attribute() && !config.blackbox_mode) continue; if (module->processes.size() != 0) - log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name)); + log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", log_id(module->name)); if (module->memories.size() != 0) - log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name)); + log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", log_id(module->name)); if (module->name == RTLIL::escape_id(top_module_name)) { BlifDumper::dump(*f, module, design, config); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index c1da4b127..14c8484e8 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -39,6 +39,7 @@ struct BtorWorker RTLIL::Module *module; bool verbose; bool single_bad; + bool cover_mode; int next_nid = 1; int initstate_nid = -1; @@ -71,7 +72,11 @@ struct BtorWorker vector<int> bad_properties; dict<SigBit, bool> initbits; pool<Wire*> statewires; - string indent; + pool<string> srcsymbols; + + string indent, info_filename; + vector<string> info_lines; + dict<int, int> info_clocks; void btorf(const char *fmt, ...) { @@ -81,6 +86,40 @@ struct BtorWorker va_end(ap); } + void infof(const char *fmt, ...) + { + va_list ap; + va_start(ap, fmt); + info_lines.push_back(vstringf(fmt, ap)); + va_end(ap); + } + + template<typename T> + string getinfo(T *obj, bool srcsym = false) + { + string infostr = log_id(obj); + if (obj->attributes.count(ID::src)) { + string src = obj->attributes.at(ID::src).decode_string().c_str(); + if (srcsym && infostr[0] == '$') { + std::replace(src.begin(), src.end(), ' ', '_'); + if (srcsymbols.count(src) || module->count_id("\\" + src)) { + for (int i = 1;; i++) { + string s = stringf("%s-%d", src.c_str(), i); + if (!srcsymbols.count(s) && !module->count_id("\\" + s)) { + src = s; + break; + } + } + } + srcsymbols.insert(src); + infostr = src; + } else { + infostr += " ; " + src; + } + } + return infostr; + } + void btorf_push(const string &id) { if (verbose) { @@ -144,40 +183,40 @@ struct BtorWorker cell_recursion_guard.insert(cell); btorf_push(log_id(cell)); - if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx", - "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) + if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx), + ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_))) { string btor_op; - if (cell->type == "$add") btor_op = "add"; - if (cell->type == "$sub") btor_op = "sub"; - if (cell->type == "$mul") btor_op = "mul"; - if (cell->type.in("$shl", "$sshl")) btor_op = "sll"; - if (cell->type == "$shr") btor_op = "srl"; - if (cell->type == "$sshr") btor_op = "sra"; - if (cell->type.in("$shift", "$shiftx")) btor_op = "shift"; - if (cell->type.in("$and", "$_AND_")) btor_op = "and"; - if (cell->type.in("$or", "$_OR_")) btor_op = "or"; - if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor"; - if (cell->type == "$concat") btor_op = "concat"; - if (cell->type == "$_NAND_") btor_op = "nand"; - if (cell->type == "$_NOR_") btor_op = "nor"; - if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor"; + if (cell->type == ID($add)) btor_op = "add"; + if (cell->type == ID($sub)) btor_op = "sub"; + if (cell->type == ID($mul)) btor_op = "mul"; + if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll"; + if (cell->type == ID($shr)) btor_op = "srl"; + if (cell->type == ID($sshr)) btor_op = "sra"; + if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift"; + if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and"; + if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or"; + if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor"; + if (cell->type == ID($concat)) btor_op = "concat"; + if (cell->type == ID($_NAND_)) btor_op = "nand"; + if (cell->type == ID($_NOR_)) btor_op = "nor"; + if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor"; log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort("\\Y")); - width = std::max(width, GetSize(cell->getPort("\\A"))); - width = std::max(width, GetSize(cell->getPort("\\B"))); + int width = GetSize(cell->getPort(ID::Y)); + width = std::max(width, GetSize(cell->getPort(ID::A))); + width = std::max(width, GetSize(cell->getPort(ID::B))); - bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; - bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; + bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; + bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false; if (btor_op == "shift" && !b_signed) btor_op = "srl"; - if (cell->type.in("$shl", "$sshl", "$shr", "$sshr")) + if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr))) b_signed = false; - if (cell->type == "$sshr" && !a_signed) + if (cell->type == ID($sshr) && !a_signed) btor_op = "srl"; int sid = get_bv_sid(width); @@ -185,8 +224,8 @@ struct BtorWorker if (btor_op == "shift") { - int nid_a = get_sig_nid(cell->getPort("\\A"), width, false); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, false); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int nid_r = next_nid++; btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b); @@ -203,18 +242,18 @@ struct BtorWorker btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero); nid = next_nid++; - btorf("%d ite %d %d %d %d\n", nid, sid, nid_b_ltz, nid_l, nid_r); + btorf("%d ite %d %d %d %d %s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str()); } else { - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); nid = next_nid++; - btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b); + btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -227,28 +266,28 @@ struct BtorWorker goto okay; } - if (cell->type.in("$div", "$mod")) + if (cell->type.in(ID($div), ID($mod))) { string btor_op; - if (cell->type == "$div") btor_op = "div"; - if (cell->type == "$mod") btor_op = "rem"; + if (cell->type == ID($div)) btor_op = "div"; + if (cell->type == ID($mod)) btor_op = "rem"; log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort("\\Y")); - width = std::max(width, GetSize(cell->getPort("\\A"))); - width = std::max(width, GetSize(cell->getPort("\\B"))); + int width = GetSize(cell->getPort(ID::Y)); + width = std::max(width, GetSize(cell->getPort(ID::A))); + width = std::max(width, GetSize(cell->getPort(ID::B))); - bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; - bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; + bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; + bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false; - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int sid = get_bv_sid(width); int nid = next_nid++; - btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b); + btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -261,120 +300,120 @@ struct BtorWorker goto okay; } - if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) + if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = get_sig_nid(cell->getPort("\\B")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = get_sig_nid(cell->getPort(ID::B)); int nid1 = next_nid++; int nid2 = next_nid++; - if (cell->type == "$_ANDNOT_") { + if (cell->type == ID($_ANDNOT_)) { btorf("%d not %d %d\n", nid1, sid, nid_b); - btorf("%d and %d %d %d\n", nid2, sid, nid_a, nid1); + btorf("%d and %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str()); } - if (cell->type == "$_ORNOT_") { + if (cell->type == ID($_ORNOT_)) { btorf("%d not %d %d\n", nid1, sid, nid_b); - btorf("%d or %d %d %d\n", nid2, sid, nid_a, nid1); + btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); add_nid_sig(nid2, sig); goto okay; } - if (cell->type.in("$_OAI3_", "$_AOI3_")) + if (cell->type.in(ID($_OAI3_), ID($_AOI3_))) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = get_sig_nid(cell->getPort("\\B")); - int nid_c = get_sig_nid(cell->getPort("\\C")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = get_sig_nid(cell->getPort(ID::B)); + int nid_c = get_sig_nid(cell->getPort(ID::C)); int nid1 = next_nid++; int nid2 = next_nid++; int nid3 = next_nid++; - if (cell->type == "$_OAI3_") { + if (cell->type == ID($_OAI3_)) { btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c); - btorf("%d not %d %d\n", nid3, sid, nid2); + btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str()); } - if (cell->type == "$_AOI3_") { + if (cell->type == ID($_AOI3_)) { btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c); - btorf("%d not %d %d\n", nid3, sid, nid2); + btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); add_nid_sig(nid3, sig); goto okay; } - if (cell->type.in("$_OAI4_", "$_AOI4_")) + if (cell->type.in(ID($_OAI4_), ID($_AOI4_))) { int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = get_sig_nid(cell->getPort("\\B")); - int nid_c = get_sig_nid(cell->getPort("\\C")); - int nid_d = get_sig_nid(cell->getPort("\\D")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = get_sig_nid(cell->getPort(ID::B)); + int nid_c = get_sig_nid(cell->getPort(ID::C)); + int nid_d = get_sig_nid(cell->getPort(ID::D)); int nid1 = next_nid++; int nid2 = next_nid++; int nid3 = next_nid++; int nid4 = next_nid++; - if (cell->type == "$_OAI4_") { + if (cell->type == ID($_OAI4_)) { btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d); btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2); - btorf("%d not %d %d\n", nid4, sid, nid3); + btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str()); } - if (cell->type == "$_AOI4_") { + if (cell->type == ID($_AOI4_)) { btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d); btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2); - btorf("%d not %d %d\n", nid4, sid, nid3); + btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); add_nid_sig(nid4, sig); goto okay; } - if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt")) + if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt))) { string btor_op; - if (cell->type == "$lt") btor_op = "lt"; - if (cell->type == "$le") btor_op = "lte"; - if (cell->type.in("$eq", "$eqx")) btor_op = "eq"; - if (cell->type.in("$ne", "$nex")) btor_op = "neq"; - if (cell->type == "$ge") btor_op = "gte"; - if (cell->type == "$gt") btor_op = "gt"; + if (cell->type == ID($lt)) btor_op = "lt"; + if (cell->type == ID($le)) btor_op = "lte"; + if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq"; + if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq"; + if (cell->type == ID($ge)) btor_op = "gte"; + if (cell->type == ID($gt)) btor_op = "gt"; log_assert(!btor_op.empty()); int width = 1; - width = std::max(width, GetSize(cell->getPort("\\A"))); - width = std::max(width, GetSize(cell->getPort("\\B"))); + width = std::max(width, GetSize(cell->getPort(ID::A))); + width = std::max(width, GetSize(cell->getPort(ID::B))); - bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; - bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; + bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; + bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false; int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); - int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int nid = next_nid++; - if (cell->type.in("$lt", "$le", "$ge", "$gt")) { - btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b); + if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) { + btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); } else { - btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b); + btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -387,25 +426,24 @@ struct BtorWorker goto okay; } - if (cell->type.in("$not", "$neg", "$_NOT_")) + if (cell->type.in(ID($not), ID($neg), ID($_NOT_))) { string btor_op; - if (cell->type.in("$not", "$_NOT_")) btor_op = "not"; - if (cell->type == "$neg") btor_op = "neg"; + if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not"; + if (cell->type == ID($neg)) btor_op = "neg"; log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort("\\Y")); - width = std::max(width, GetSize(cell->getPort("\\A"))); + int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y))); - bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; + bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; int sid = get_bv_sid(width); - int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed); + int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); int nid = next_nid++; - btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a); + btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) < width) { int sid = get_bv_sid(GetSize(sig)); @@ -418,25 +456,25 @@ struct BtorWorker goto okay; } - if (cell->type.in("$logic_and", "$logic_or", "$logic_not")) + if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not))) { string btor_op; - if (cell->type == "$logic_and") btor_op = "and"; - if (cell->type == "$logic_or") btor_op = "or"; - if (cell->type == "$logic_not") btor_op = "not"; + if (cell->type == ID($logic_and)) btor_op = "and"; + if (cell->type == ID($logic_or)) btor_op = "or"; + if (cell->type == ID($logic_not)) btor_op = "not"; log_assert(!btor_op.empty()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0; + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0; - if (GetSize(cell->getPort("\\A")) > 1) { + if (GetSize(cell->getPort(ID::A)) > 1) { int nid_red_a = next_nid++; btorf("%d redor %d %d\n", nid_red_a, sid, nid_a); nid_a = nid_red_a; } - if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) { + if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) { int nid_red_b = next_nid++; btorf("%d redor %d %d\n", nid_red_b, sid, nid_b); nid_b = nid_red_b; @@ -444,11 +482,11 @@ struct BtorWorker int nid = next_nid++; if (btor_op != "not") - btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b); + btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); else - btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a); + btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -462,27 +500,29 @@ struct BtorWorker goto okay; } - if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor")) + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor))) { string btor_op; - if (cell->type == "$reduce_and") btor_op = "redand"; - if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor"; - if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor"; + if (cell->type == ID($reduce_and)) btor_op = "redand"; + if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor"; + if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor"; log_assert(!btor_op.empty()); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid = next_nid++; - btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a); - if (cell->type == "$reduce_xnor") { + if (cell->type == ID($reduce_xnor)) { int nid2 = next_nid++; + btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); btorf("%d not %d %d %d\n", nid2, sid, nid); nid = nid2; + } else { + btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); } - SigSpec sig = sigmap(cell->getPort("\\Y")); + SigSpec sig = sigmap(cell->getPort(ID::Y)); if (GetSize(sig) > 1) { int sid = get_bv_sid(GetSize(sig)); @@ -496,12 +536,12 @@ struct BtorWorker goto okay; } - if (cell->type.in("$mux", "$_MUX_", "$_NMUX_")) + if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_))) { - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); int nid_a = get_sig_nid(sig_a); int nid_b = get_sig_nid(sig_b); @@ -509,24 +549,26 @@ struct BtorWorker int sid = get_bv_sid(GetSize(sig_y)); int nid = next_nid++; - btorf("%d ite %d %d %d %d\n", nid, sid, nid_s, nid_b, nid_a); - if (cell->type == "$_NMUX_") { + if (cell->type == ID($_NMUX_)) { int tmp = nid; nid = next_nid++; - btorf("%d not %d %d\n", nid, sid, tmp); + btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a); + btorf("%d not %d %d %s\n", nid, sid, tmp, getinfo(cell).c_str()); + } else { + btorf("%d ite %d %d %d %d %s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str()); } add_nid_sig(nid, sig_y); goto okay; } - if (cell->type == "$pmux") + if (cell->type == ID($pmux)) { - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); int width = GetSize(sig_a); int sid = get_bv_sid(width); @@ -536,7 +578,10 @@ struct BtorWorker int nid_b = get_sig_nid(sig_b.extract(i*width, width)); int nid_s = get_sig_nid(sig_s.extract(i)); int nid2 = next_nid++; - btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid); + if (i == GetSize(sig_s)-1) + btorf("%d ite %d %d %d %d %s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str()); + else + btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid); nid = nid2; } @@ -544,10 +589,25 @@ struct BtorWorker goto okay; } - if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_")) + if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_))) { - SigSpec sig_d = sigmap(cell->getPort("\\D")); - SigSpec sig_q = sigmap(cell->getPort("\\Q")); + SigSpec sig_d = sigmap(cell->getPort(ID::D)); + SigSpec sig_q = sigmap(cell->getPort(ID::Q)); + + if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_))) + { + SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C)); + int nid = get_sig_nid(sig_c); + bool negedge = false; + + if (cell->type == ID($_DFF_N_)) + negedge = true; + + if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool()) + negedge = true; + + info_clocks[nid] |= negedge ? 2 : 1; + } IdString symbol; @@ -591,16 +651,16 @@ struct BtorWorker goto okay; } - if (cell->type.in("$anyconst", "$anyseq")) + if (cell->type.in(ID($anyconst), ID($anyseq))) { - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); int sid = get_bv_sid(GetSize(sig_y)); int nid = next_nid++; btorf("%d state %d\n", nid, sid); - if (cell->type == "$anyconst") { + if (cell->type == ID($anyconst)) { int nid2 = next_nid++; btorf("%d next %d %d %d\n", nid2, sid, nid, nid); } @@ -609,9 +669,9 @@ struct BtorWorker goto okay; } - if (cell->type == "$initstate") + if (cell->type == ID($initstate)) { - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); if (initstate_nid < 0) { @@ -628,16 +688,16 @@ struct BtorWorker goto okay; } - if (cell->type == "$mem") + if (cell->type == ID($mem)) { - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); - int nwords = cell->getParam("\\SIZE").as_int(); - int rdports = cell->getParam("\\RD_PORTS").as_int(); - int wrports = cell->getParam("\\WR_PORTS").as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int nwords = cell->getParam(ID::SIZE).as_int(); + int rdports = cell->getParam(ID::RD_PORTS).as_int(); + int wrports = cell->getParam(ID::WR_PORTS).as_int(); - Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE"); - Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE"); + Const wr_clk_en = cell->getParam(ID::WR_CLK_ENABLE); + Const rd_clk_en = cell->getParam(ID::RD_CLK_ENABLE); bool asyncwr = wr_clk_en.is_fully_zero(); @@ -649,18 +709,18 @@ struct BtorWorker log_error("Memory %s.%s has sync read ports.\n", log_id(module), log_id(cell)); - SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR")); - SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA")); + SigSpec sig_rd_addr = sigmap(cell->getPort(ID::RD_ADDR)); + SigSpec sig_rd_data = sigmap(cell->getPort(ID::RD_DATA)); - SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR")); - SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA")); - SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN")); + SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR)); + SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA)); + SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN)); int data_sid = get_bv_sid(width); int bool_sid = get_bv_sid(1); int sid = get_mem_sid(abits, width); - Const initdata = cell->getParam("\\INIT"); + Const initdata = cell->getParam(ID::INIT); initdata.exts(nwords*width); int nid_init_val = -1; @@ -983,15 +1043,18 @@ struct BtorWorker return nid; } - BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad) : - f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad) + BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, string info_filename) : + f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), info_filename(info_filename) { + if (!info_filename.empty()) + infof("name %s\n", log_id(module)); + btorf_push("inputs"); for (auto wire : module->wires()) { - if (wire->attributes.count("\\init")) { - Const attrval = wire->attributes.at("\\init"); + if (wire->attributes.count(ID::init)) { + Const attrval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++) if (attrval[i] == State::S0 || attrval[i] == State::S1) initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1); @@ -1004,7 +1067,7 @@ struct BtorWorker int sid = get_bv_sid(GetSize(sig)); int nid = next_nid++; - btorf("%d input %d %s\n", nid, sid, log_id(wire)); + btorf("%d input %d %s\n", nid, sid, getinfo(wire).c_str()); add_nid_sig(nid, sig); } @@ -1028,20 +1091,20 @@ struct BtorWorker btorf_push(stringf("output %s", log_id(wire))); int nid = get_sig_nid(wire); - btorf("%d output %d %s\n", next_nid++, nid, log_id(wire)); + btorf("%d output %d %s\n", next_nid++, nid, getinfo(wire).c_str()); btorf_pop(stringf("output %s", log_id(wire))); } for (auto cell : module->cells()) { - if (cell->type == "$assume") + if (cell->type == ID($assume)) { btorf_push(log_id(cell)); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_en = get_sig_nid(cell->getPort("\\EN")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_en = get_sig_nid(cell->getPort(ID::EN)); int nid_not_en = next_nid++; int nid_a_or_not_en = next_nid++; int nid = next_nid++; @@ -1053,29 +1116,49 @@ struct BtorWorker btorf_pop(log_id(cell)); } - if (cell->type == "$assert") + if (cell->type == ID($assert)) { btorf_push(log_id(cell)); int sid = get_bv_sid(1); - int nid_a = get_sig_nid(cell->getPort("\\A")); - int nid_en = get_sig_nid(cell->getPort("\\EN")); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_en = get_sig_nid(cell->getPort(ID::EN)); int nid_not_a = next_nid++; int nid_en_and_not_a = next_nid++; btorf("%d not %d %d\n", nid_not_a, sid, nid_a); btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a); - if (single_bad) { + if (single_bad && !cover_mode) { bad_properties.push_back(nid_en_and_not_a); } else { - int nid = next_nid++; - string infostr = log_id(cell); - if (infostr[0] == '$' && cell->attributes.count("\\src")) { - infostr = cell->attributes.at("\\src").decode_string().c_str(); - std::replace(infostr.begin(), infostr.end(), ' ', '_'); + if (cover_mode) { + infof("bad %d %s\n", nid_en_and_not_a, getinfo(cell, true).c_str()); + } else { + int nid = next_nid++; + btorf("%d bad %d %s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str()); } - btorf("%d bad %d %s\n", nid, nid_en_and_not_a, infostr.c_str()); + } + + btorf_pop(log_id(cell)); + } + + if (cell->type == ID($cover) && cover_mode) + { + btorf_push(log_id(cell)); + + int sid = get_bv_sid(1); + int nid_a = get_sig_nid(cell->getPort(ID::A)); + int nid_en = get_sig_nid(cell->getPort(ID::EN)); + int nid_en_and_a = next_nid++; + + btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a); + + if (single_bad) { + bad_properties.push_back(nid_en_and_a); + } else { + int nid = next_nid++; + btorf("%d bad %d %s\n", nid, nid_en_and_a, getinfo(cell, true).c_str()); } btorf_pop(log_id(cell)); @@ -1096,7 +1179,7 @@ struct BtorWorker continue; int this_nid = next_nid++; - btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, log_id(wire)); + btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, getinfo(wire).c_str()); btorf_pop(stringf("wire %s", log_id(wire))); continue; @@ -1114,15 +1197,15 @@ struct BtorWorker btorf_push(stringf("next %s", log_id(cell))); - if (cell->type == "$mem") + if (cell->type == ID($mem)) { - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); - int wrports = cell->getParam("\\WR_PORTS").as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int wrports = cell->getParam(ID::WR_PORTS).as_int(); - SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR")); - SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA")); - SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN")); + SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR)); + SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA)); + SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN)); int data_sid = get_bv_sid(width); int bool_sid = get_bv_sid(1); @@ -1167,14 +1250,14 @@ struct BtorWorker } int nid2 = next_nid++; - btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head); + btorf("%d next %d %d %d %s\n", nid2, sid, nid, nid_head, getinfo(cell).c_str()); } else { - SigSpec sig = sigmap(cell->getPort("\\D")); + SigSpec sig = sigmap(cell->getPort(ID::D)); int nid_q = get_sig_nid(sig); int sid = get_bv_sid(GetSize(sig)); - btorf("%d next %d %d %d\n", next_nid++, sid, nid, nid_q); + btorf("%d next %d %d %d %s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str()); } btorf_pop(stringf("next %s", log_id(cell))); @@ -1210,6 +1293,35 @@ struct BtorWorker btorf("%d bad %d\n", nid, todo[cursor]); } } + + if (!info_filename.empty()) + { + for (auto &it : info_clocks) + { + switch (it.second) + { + case 1: + infof("posedge %d\n", it.first); + break; + case 2: + infof("negedge %d\n", it.first); + break; + case 3: + infof("event %d\n", it.first); + break; + default: + log_abort(); + } + } + + std::ofstream f; + f.open(info_filename.c_str(), std::ofstream::trunc); + if (f.fail()) + log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno)); + for (auto &it : info_lines) + f << it; + f.close(); + } } }; @@ -1229,10 +1341,17 @@ struct BtorBackend : public Backend { log(" -s\n"); log(" Output only a single bad property for all asserts\n"); log("\n"); + log(" -c\n"); + log(" Output cover properties using 'bad' statements instead of asserts\n"); + log("\n"); + log(" -i <filename>\n"); + log(" Create additional info file with auxiliary information\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { - bool verbose = false, single_bad = false; + bool verbose = false, single_bad = false, cover_mode = false; + string info_filename; log_header(design, "Executing BTOR backend.\n"); @@ -1247,6 +1366,14 @@ struct BtorBackend : public Backend { single_bad = true; continue; } + if (args[argidx] == "-c") { + cover_mode = true; + continue; + } + if (args[argidx] == "-i" && argidx+1 < args.size()) { + info_filename = args[++argidx]; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -1259,7 +1386,7 @@ struct BtorBackend : public Backend { *f << stringf("; BTOR description generated by %s for module %s.\n", yosys_version_str, log_id(topmod)); - BtorWorker(*f, topmod, verbose, single_bad); + BtorWorker(*f, topmod, verbose, single_bad, cover_mode, info_filename); *f << stringf("; end of yosys output\n"); } diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 199560ad0..cc20f17fc 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -171,13 +171,12 @@ struct EdifBackend : public Backend { extra_args(f, filename, args, argidx); if (top_module_name.empty()) - for (auto & mod_it:design->modules_) - if (mod_it.second->get_bool_attribute("\\top")) - top_module_name = mod_it.first.str(); + for (auto module : design->modules()) + if (module->get_bool_attribute(ID::top)) + top_module_name = module->name.str(); - for (auto module_it : design->modules_) + for (auto module : design->modules()) { - RTLIL::Module *module = module_it.second; if (module->get_blackbox_attribute()) continue; @@ -185,14 +184,13 @@ struct EdifBackend : public Backend { top_module_name = module->name.str(); if (module->processes.size() != 0) - log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name)); + log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", log_id(module->name)); if (module->memories.size() != 0) - log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name)); + log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", log_id(module->name)); - for (auto cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; - if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_blackbox_attribute()) { + if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) { lib_cell_ports[cell->type]; for (auto p : cell->connections()) lib_cell_ports[cell->type][p.first] = GetSize(p.second); @@ -277,11 +275,11 @@ struct EdifBackend : public Backend { // extract module dependencies std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps; - for (auto &mod_it : design->modules_) { - module_deps[mod_it.second] = std::set<RTLIL::Module*>(); - for (auto &cell_it : mod_it.second->cells_) - if (design->modules_.count(cell_it.second->type) > 0) - module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type)); + for (auto module : design->modules()) { + module_deps[module] = std::set<RTLIL::Module*>(); + for (auto cell : module->cells()) + if (design->module(cell->type) != nullptr) + module_deps[module].insert(design->module(cell->type)); } // simple good-enough topological sort @@ -292,12 +290,12 @@ struct EdifBackend : public Backend { for (auto &dep : it.second) if (module_deps.count(dep) > 0) goto not_ready_yet; - // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name)); + // log("Next in topological sort: %s\n", log_id(it.first->name)); sorted_modules.push_back(it.first); not_ready_yet:; } if (sorted_modules_idx == sorted_modules.size()) - log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name)); + log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name)); while (sorted_modules_idx < sorted_modules.size()) module_deps.erase(sorted_modules.at(sorted_modules_idx++)); } @@ -339,8 +337,7 @@ struct EdifBackend : public Backend { *f << stringf(" (view VIEW_NETLIST\n"); *f << stringf(" (viewType NETLIST)\n"); *f << stringf(" (interface\n"); - for (auto &wire_it : module->wires_) { - RTLIL::Wire *wire = wire_it.second; + for (auto wire : module->wires()) { if (wire->port_id == 0) continue; const char *dir = "INOUT"; @@ -378,8 +375,7 @@ struct EdifBackend : public Backend { *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n"); *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); } - for (auto &cell_it : module->cells_) { - RTLIL::Cell *cell = cell_it.second; + for (auto cell : module->cells()) { *f << stringf(" (instance %s\n", EDIF_DEF(cell->name)); *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); @@ -459,8 +455,7 @@ struct EdifBackend : public Backend { add_prop(p.first, p.second); *f << stringf("\n )\n"); } - for (auto &wire_it : module->wires_) { - RTLIL::Wire *wire = wire_it.second; + for (auto wire : module->wires()) { if (!wire->get_bool_attribute(ID::keep)) continue; for(int i = 0; i < wire->width; i++) { diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 3ef886664..94d3e14c1 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -208,7 +208,7 @@ struct FirrtlWorker const char *atLine() { if (srcLine == "") { if (pCell) { - auto p = pCell->attributes.find("\\src"); + auto p = pCell->attributes.find(ID::src); srcLine = " at " + p->second.decode_string(); } } @@ -414,9 +414,9 @@ struct FirrtlWorker std::string wireFileinfo = getFileinfo(wire); // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it. - if (wire->attributes.count("\\init")) { + if (wire->attributes.count(ID::init)) { log_warning("Initial value (%s) for (%s.%s) not supported\n", - wire->attributes.at("\\init").as_string().c_str(), + wire->attributes.at(ID::init).as_string().c_str(), log_id(module), log_id(wire)); } if (wire->port_id) @@ -444,11 +444,11 @@ struct FirrtlWorker } // Not a module instance. Set up cell properties bool extract_y_bits = false; // Assume no extraction of final bits will be required. - int a_width = cell->parameters.at("\\A_WIDTH", ndef).as_int(); // The width of "A" - int b_width = cell->parameters.at("\\B_WIDTH", ndef).as_int(); // The width of "A" - const int y_width = cell->parameters.at("\\Y_WIDTH", ndef).as_int(); // The width of the result - const bool a_signed = cell->parameters.at("\\A_SIGNED", ndef).as_bool(); - const bool b_signed = cell->parameters.at("\\B_SIGNED", ndef).as_bool(); + int a_width = cell->parameters.at(ID::A_WIDTH, ndef).as_int(); // The width of "A" + int b_width = cell->parameters.at(ID::B_WIDTH, ndef).as_int(); // The width of "A" + const int y_width = cell->parameters.at(ID::Y_WIDTH, ndef).as_int(); // The width of the result + const bool a_signed = cell->parameters.at(ID::A_SIGNED, ndef).as_bool(); + const bool b_signed = cell->parameters.at(ID::B_SIGNED, ndef).as_bool(); bool firrtl_is_signed = a_signed; // The result is signed (subsequent code may change this). int firrtl_width = 0; string primop; @@ -456,9 +456,9 @@ struct FirrtlWorker string y_id = make_id(cell->name); std::string cellFileinfo = getFileinfo(cell); - if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor")) + if (cell->type.in(ID($not), ID($logic_not), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor))) { - string a_expr = make_expr(cell->getPort("\\A")); + string a_expr = make_expr(cell->getPort(ID::A)); wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str())); if (a_signed) { @@ -466,29 +466,29 @@ struct FirrtlWorker } // Don't use the results of logical operations (a single bit) to control padding - if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) { + if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) { a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width); } // Assume the FIRRTL width is a single bit. firrtl_width = 1; - if (cell->type == "$not") primop = "not"; - else if (cell->type == "$neg") { + if (cell->type == ID($not)) primop = "not"; + else if (cell->type == ID($neg)) { primop = "neg"; firrtl_is_signed = true; // Result of "neg" is signed (an SInt). firrtl_width = a_width; - } else if (cell->type == "$logic_not") { + } else if (cell->type == ID($logic_not)) { primop = "eq"; a_expr = stringf("%s, UInt(0)", a_expr.c_str()); } - else if (cell->type == "$reduce_and") primop = "andr"; - else if (cell->type == "$reduce_or") primop = "orr"; - else if (cell->type == "$reduce_xor") primop = "xorr"; - else if (cell->type == "$reduce_xnor") { + else if (cell->type == ID($reduce_and)) primop = "andr"; + else if (cell->type == ID($reduce_or)) primop = "orr"; + else if (cell->type == ID($reduce_xor)) primop = "xorr"; + else if (cell->type == ID($reduce_xnor)) { primop = "not"; a_expr = stringf("xorr(%s)", a_expr.c_str()); } - else if (cell->type == "$reduce_bool") { + else if (cell->type == ID($reduce_bool)) { primop = "neq"; // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand. a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width); @@ -500,16 +500,16 @@ struct FirrtlWorker expr = stringf("asUInt(%s)", expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } - if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx", - "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl", - "$logic_and", "$logic_or", "$pow")) + if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx), + ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl), + ID($logic_and), ID($logic_or), ID($pow))) { - string a_expr = make_expr(cell->getPort("\\A")); - string b_expr = make_expr(cell->getPort("\\B")); + string a_expr = make_expr(cell->getPort(ID::A)); + string b_expr = make_expr(cell->getPort(ID::B)); std::string cellFileinfo = getFileinfo(cell); wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str())); @@ -523,7 +523,7 @@ struct FirrtlWorker } // Shift amount is always unsigned, and needn't be padded to result width, // otherwise, we need to cast the b_expr appropriately - if (b_signed && !cell->type.in("$shr", "$sshr", "$shl", "$sshl", "$pow")) { + if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) { b_expr = "asSInt(" + b_expr + ")"; // Expand the "B" operand to the result width if (b_width < y_width) { @@ -534,7 +534,7 @@ struct FirrtlWorker // For the arithmetic ops, expand operand widths to result widths befor performing the operation. // This corresponds (according to iverilog) to what verilog compilers implement. - if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or")) + if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or))) { if (a_width < y_width) { a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width); @@ -547,85 +547,85 @@ struct FirrtlWorker } // Assume the FIRRTL width is the width of "A" firrtl_width = a_width; - auto a_sig = cell->getPort("\\A"); + auto a_sig = cell->getPort(ID::A); - if (cell->type == "$add") { + if (cell->type == ID($add)) { primop = "add"; firrtl_is_signed = a_signed | b_signed; firrtl_width = max(a_width, b_width); - } else if (cell->type == "$sub") { + } else if (cell->type == ID($sub)) { primop = "sub"; firrtl_is_signed = true; int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0; int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0; firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc); - } else if (cell->type == "$mul") { + } else if (cell->type == ID($mul)) { primop = "mul"; firrtl_is_signed = a_signed | b_signed; firrtl_width = a_width + b_width; - } else if (cell->type == "$div") { + } else if (cell->type == ID($div)) { primop = "div"; firrtl_is_signed = a_signed | b_signed; firrtl_width = a_width; - } else if (cell->type == "$mod") { + } else if (cell->type == ID($mod)) { primop = "rem"; firrtl_width = min(a_width, b_width); - } else if (cell->type == "$and") { + } else if (cell->type == ID($and)) { primop = "and"; always_uint = true; firrtl_width = max(a_width, b_width); } - else if (cell->type == "$or" ) { + else if (cell->type == ID($or) ) { primop = "or"; always_uint = true; firrtl_width = max(a_width, b_width); } - else if (cell->type == "$xor") { + else if (cell->type == ID($xor)) { primop = "xor"; always_uint = true; firrtl_width = max(a_width, b_width); } - else if (cell->type == "$xnor") { + else if (cell->type == ID($xnor)) { primop = "xnor"; always_uint = true; firrtl_width = max(a_width, b_width); } - else if ((cell->type == "$eq") | (cell->type == "$eqx")) { + else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) { primop = "eq"; always_uint = true; firrtl_width = 1; - } - else if ((cell->type == "$ne") | (cell->type == "$nex")) { + } + else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) { primop = "neq"; always_uint = true; firrtl_width = 1; } - else if (cell->type == "$gt") { + else if (cell->type == ID($gt)) { primop = "gt"; always_uint = true; firrtl_width = 1; } - else if (cell->type == "$ge") { + else if (cell->type == ID($ge)) { primop = "geq"; always_uint = true; firrtl_width = 1; } - else if (cell->type == "$lt") { + else if (cell->type == ID($lt)) { primop = "lt"; always_uint = true; firrtl_width = 1; } - else if (cell->type == "$le") { + else if (cell->type == ID($le)) { primop = "leq"; always_uint = true; firrtl_width = 1; } - else if ((cell->type == "$shl") | (cell->type == "$sshl")) { + else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) { // FIRRTL will widen the result (y) by the amount of the shift. // We'll need to offset this by extracting the un-widened portion as Verilog would do. extract_y_bits = true; // Is the shift amount constant? - auto b_sig = cell->getPort("\\B"); + auto b_sig = cell->getPort(ID::B); if (b_sig.is_fully_const()) { primop = "shl"; int shift_amount = b_sig.as_int(); @@ -638,11 +638,11 @@ struct FirrtlWorker firrtl_width = a_width + (1 << b_width) - 1; } } - else if ((cell->type == "$shr") | (cell->type == "$sshr")) { + else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) { // We don't need to extract a specific range of bits. extract_y_bits = false; // Is the shift amount constant? - auto b_sig = cell->getPort("\\B"); + auto b_sig = cell->getPort(ID::B); if (b_sig.is_fully_const()) { primop = "shr"; int shift_amount = b_sig.as_int(); @@ -655,26 +655,26 @@ struct FirrtlWorker // We'll need to do some special fixups if the source (and thus result) is signed. if (firrtl_is_signed) { // If this is a "logical" shift right, pretend the source is unsigned. - if (cell->type == "$shr") { + if (cell->type == ID($shr)) { a_expr = "asUInt(" + a_expr + ")"; } } } - else if ((cell->type == "$logic_and")) { + else if ((cell->type == ID($logic_and))) { primop = "and"; a_expr = "neq(" + a_expr + ", UInt(0))"; b_expr = "neq(" + b_expr + ", UInt(0))"; always_uint = true; firrtl_width = 1; } - else if ((cell->type == "$logic_or")) { + else if ((cell->type == ID($logic_or))) { primop = "or"; a_expr = "neq(" + a_expr + ", UInt(0))"; b_expr = "neq(" + b_expr + ", UInt(0))"; always_uint = true; firrtl_width = 1; } - else if ((cell->type == "$pow")) { + else if ((cell->type == ID($pow))) { if (a_sig.is_fully_const() && a_sig.as_int() == 2) { // We'll convert this to a shift. To simplify things, change the a_expr to "1" // so we can use b_expr directly as a shift amount. @@ -684,7 +684,7 @@ struct FirrtlWorker a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)"; extract_y_bits = true; // Is the shift amount constant? - auto b_sig = cell->getPort("\\B"); + auto b_sig = cell->getPort(ID::B); if (b_sig.is_fully_const()) { primop = "shl"; int shiftAmount = b_sig.as_int(); @@ -704,7 +704,7 @@ struct FirrtlWorker } } - if (!cell->parameters.at("\\B_SIGNED").as_bool()) { + if (!cell->parameters.at(ID::B_SIGNED).as_bool()) { b_expr = "asUInt(" + b_expr + ")"; } @@ -728,47 +728,47 @@ struct FirrtlWorker expr = stringf("asUInt(%s)", expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } - if (cell->type.in("$mux")) + if (cell->type.in(ID($mux))) { - int width = cell->parameters.at("\\WIDTH").as_int(); - string a_expr = make_expr(cell->getPort("\\A")); - string b_expr = make_expr(cell->getPort("\\B")); - string s_expr = make_expr(cell->getPort("\\S")); + int width = cell->parameters.at(ID::WIDTH).as_int(); + string a_expr = make_expr(cell->getPort(ID::A)); + string b_expr = make_expr(cell->getPort(ID::B)); + string s_expr = make_expr(cell->getPort(ID::S)); wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), width, cellFileinfo.c_str())); string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } - if (cell->type.in("$mem")) + if (cell->type.in(ID($mem))) { string mem_id = make_id(cell->name); - int abits = cell->parameters.at("\\ABITS").as_int(); - int width = cell->parameters.at("\\WIDTH").as_int(); - int size = cell->parameters.at("\\SIZE").as_int(); + int abits = cell->parameters.at(ID::ABITS).as_int(); + int width = cell->parameters.at(ID::WIDTH).as_int(); + int size = cell->parameters.at(ID::SIZE).as_int(); memory m(cell, mem_id, abits, size, width); - int rd_ports = cell->parameters.at("\\RD_PORTS").as_int(); - int wr_ports = cell->parameters.at("\\WR_PORTS").as_int(); + int rd_ports = cell->parameters.at(ID::RD_PORTS).as_int(); + int wr_ports = cell->parameters.at(ID::WR_PORTS).as_int(); - Const initdata = cell->parameters.at("\\INIT"); + Const initdata = cell->parameters.at(ID::INIT); for (State bit : initdata.bits) if (bit != State::Sx) log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell)); - Const rd_clk_enable = cell->parameters.at("\\RD_CLK_ENABLE"); - Const wr_clk_enable = cell->parameters.at("\\WR_CLK_ENABLE"); - Const wr_clk_polarity = cell->parameters.at("\\WR_CLK_POLARITY"); + Const rd_clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE); + Const wr_clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE); + Const wr_clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY); - int offset = cell->parameters.at("\\OFFSET").as_int(); + int offset = cell->parameters.at(ID::OFFSET).as_int(); if (offset != 0) log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell)); @@ -777,8 +777,8 @@ struct FirrtlWorker if (rd_clk_enable[i] != State::S0) log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell)); - SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(i*abits, abits); - SigSpec data_sig = cell->getPort("\\RD_DATA").extract(i*width, width); + SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(i*abits, abits); + SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(i*width, width); string addr_expr = make_expr(addr_sig); string name(stringf("%s.r%d", m.name.c_str(), i)); bool clk_enable = false; @@ -804,14 +804,14 @@ struct FirrtlWorker bool clk_enable = true; bool clk_parity = true; bool transparency = false; - SigSpec addr_sig =cell->getPort("\\WR_ADDR").extract(i*abits, abits); + SigSpec addr_sig =cell->getPort(ID::WR_ADDR).extract(i*abits, abits); string addr_expr = make_expr(addr_sig); - SigSpec data_sig =cell->getPort("\\WR_DATA").extract(i*width, width); + SigSpec data_sig =cell->getPort(ID::WR_DATA).extract(i*width, width); string data_expr = make_expr(data_sig); - SigSpec clk_sig = cell->getPort("\\WR_CLK").extract(i); + SigSpec clk_sig = cell->getPort(ID::WR_CLK).extract(i); string clk_expr = make_expr(clk_sig); - SigSpec wen_sig = cell->getPort("\\WR_EN").extract(i*width, width); + SigSpec wen_sig = cell->getPort(ID::WR_EN).extract(i*width, width); string wen_expr = make_expr(wen_sig[0]); for (int i = 1; i < GetSize(wen_sig); i++) @@ -828,23 +828,23 @@ struct FirrtlWorker continue; } - if (cell->type.in("$memwr", "$memrd", "$meminit")) + if (cell->type.in(ID($memwr), ID($memrd), ID($meminit))) { std::string cell_type = fid(cell->type); - std::string mem_id = make_id(cell->parameters["\\MEMID"].decode_string()); - int abits = cell->parameters.at("\\ABITS").as_int(); - int width = cell->parameters.at("\\WIDTH").as_int(); + std::string mem_id = make_id(cell->parameters[ID::MEMID].decode_string()); + int abits = cell->parameters.at(ID::ABITS).as_int(); + int width = cell->parameters.at(ID::WIDTH).as_int(); memory *mp = nullptr; - if (cell->type == "$meminit" ) { + if (cell->type == ID($meminit) ) { log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str()); } else { // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition. - auto addrSig = cell->getPort("\\ADDR"); - auto dataSig = cell->getPort("\\DATA"); - auto enableSig = cell->getPort("\\EN"); - auto clockSig = cell->getPort("\\CLK"); - Const clk_enable = cell->parameters.at("\\CLK_ENABLE"); - Const clk_polarity = cell->parameters.at("\\CLK_POLARITY"); + auto addrSig = cell->getPort(ID::ADDR); + auto dataSig = cell->getPort(ID::DATA); + auto enableSig = cell->getPort(ID::EN); + auto clockSig = cell->getPort(ID::CLK); + Const clk_enable = cell->parameters.at(ID::CLK_ENABLE); + Const clk_polarity = cell->parameters.at(ID::CLK_POLARITY); // Do we already have an entry for this memory? if (memories.count(mem_id) == 0) { @@ -855,13 +855,13 @@ struct FirrtlWorker int portNum = 0; bool transparency = false; string data_expr = make_expr(dataSig); - if (cell->type.in("$memwr")) { + if (cell->type.in(ID($memwr))) { portNum = (int) mp->write_ports.size(); write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig); mp->add_memory_write_port(wp); cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str())); cell_exprs.push_back(wp.gen_write(indent.c_str())); - } else if (cell->type.in("$memrd")) { + } else if (cell->type.in(ID($memrd))) { portNum = (int) mp->read_ports.size(); read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig); mp->add_memory_read_port(rp); @@ -872,20 +872,20 @@ struct FirrtlWorker continue; } - if (cell->type.in("$dff")) + if (cell->type.in(ID($dff))) { - bool clkpol = cell->parameters.at("\\CLK_POLARITY").as_bool(); + bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool(); if (clkpol == false) log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell)); - int width = cell->parameters.at("\\WIDTH").as_int(); - string expr = make_expr(cell->getPort("\\D")); - string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")"; + int width = cell->parameters.at(ID::WIDTH).as_int(); + string expr = make_expr(cell->getPort(ID::D)); + string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")"; wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s %s\n", y_id.c_str(), width, clk_expr.c_str(), cellFileinfo.c_str())); cell_exprs.push_back(stringf(" %s <= %s %s\n", y_id.c_str(), expr.c_str(), cellFileinfo.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Q")); + register_reverse_wire_map(y_id, cell->getPort(ID::Q)); continue; } @@ -896,38 +896,38 @@ struct FirrtlWorker process_instance(cell, wire_exprs); continue; } - if (cell->type == "$shiftx") { + if (cell->type == ID($shiftx)) { // assign y = a[b +: y_width]; // We'll extract the correct bits as part of the primop. - string a_expr = make_expr(cell->getPort("\\A")); + string a_expr = make_expr(cell->getPort(ID::A)); // Get the initial bit selector - string b_expr = make_expr(cell->getPort("\\B")); + string b_expr = make_expr(cell->getPort(ID::B)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); - if (cell->getParam("\\B_SIGNED").as_bool()) { + if (cell->getParam(ID::B_SIGNED).as_bool()) { // Use validif to constrain the selection (test the sign bit) auto b_string = b_expr.c_str(); - int b_sign = cell->parameters.at("\\B_WIDTH").as_int() - 1; + int b_sign = cell->parameters.at(ID::B_WIDTH).as_int() - 1; b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string); } string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str()); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } - if (cell->type == "$shift") { + if (cell->type == ID($shift)) { // assign y = a >> b; // where b may be negative - string a_expr = make_expr(cell->getPort("\\A")); - string b_expr = make_expr(cell->getPort("\\B")); + string a_expr = make_expr(cell->getPort(ID::A)); + string b_expr = make_expr(cell->getPort(ID::B)); auto b_string = b_expr.c_str(); string expr; wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); - if (cell->getParam("\\B_SIGNED").as_bool()) { + if (cell->getParam(ID::B_SIGNED).as_bool()) { // We generate a left or right shift based on the sign of b. std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width); std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string); @@ -940,13 +940,13 @@ struct FirrtlWorker expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string); } cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } - if (cell->type == "$pos") { + if (cell->type == ID($pos)) { // assign y = a; // printCell(cell); - string a_expr = make_expr(cell->getPort("\\A")); + string a_expr = make_expr(cell->getPort(ID::A)); // Verilog appears to treat the result as signed, so if the result is wider than "A", // we need to pad. if (a_width < y_width) { @@ -954,7 +954,7 @@ struct FirrtlWorker } wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), a_expr.c_str())); - register_reverse_wire_map(y_id, cell->getPort("\\Y")); + register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell)); @@ -1134,7 +1134,7 @@ struct FirrtlBackend : public Backend { for (auto module : design->modules()) { make_id(module->name); last = module; - if (top == nullptr && module->get_bool_attribute("\\top")) { + if (top == nullptr && module->get_bool_attribute(ID::top)) { top = module; } for (auto wire : module->wires()) diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index e06786220..5445fad90 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -358,10 +358,10 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!flag_m) { int count_selected_mods = 0; - for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { - if (design->selected_whole_module(it->first)) + for (auto module : design->modules()) { + if (design->selected_whole_module(module->name)) flag_m = true; - if (design->selected(it->second)) + if (design->selected(module)) count_selected_mods++; } if (count_selected_mods > 1) @@ -374,11 +374,11 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl f << stringf("autoidx %d\n", autoidx); } - for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { - if (!only_selected || design->selected(it->second)) { + for (auto module : design->modules()) { + if (!only_selected || design->selected(module)) { if (only_selected) f << stringf("\n"); - dump_module(f, "", it->second, design, only_selected, flag_m, flag_n); + dump_module(f, "", module, design, only_selected, flag_m, flag_n); } } diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 809a0fa09..31dce1cca 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -122,70 +122,67 @@ struct IntersynthBackend : public Backend { for (auto lib : libs) ct.setup_design(lib); - for (auto module_it : design->modules_) + for (auto module : design->modules()) { - RTLIL::Module *module = module_it.second; SigMap sigmap(module); if (module->get_blackbox_attribute()) continue; - if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0) + if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells().size() == 0) continue; if (selected && !design->selected_whole_module(module->name)) { if (design->selected_module(module->name)) - log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name)); + log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name)); continue; } - log("Generating netlist %s.\n", RTLIL::id2cstr(module->name)); + log("Generating netlist %s.\n", log_id(module->name)); if (module->memories.size() != 0 || module->processes.size() != 0) log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n"); std::set<std::string> constcells_code; - netlists_code += stringf("# Netlist of module %s\n", RTLIL::id2cstr(module->name)); - netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name)); + netlists_code += stringf("# Netlist of module %s\n", log_id(module->name)); + netlists_code += stringf("netlist %s\n", log_id(module->name)); // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports - for (auto wire_it : module->wires_) { - RTLIL::Wire *wire = wire_it.second; + for (auto wire : module->wires()) { if (wire->port_input || wire->port_output) { celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n", - RTLIL::id2cstr(wire->name), wire->width, wire->port_input ? "*" : "", - wire->port_input ? "input" : "output", RTLIL::id2cstr(wire->name), wire->width, RTLIL::id2cstr(wire->name))); - netlists_code += stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(wire->name), + log_id(wire->name), wire->width, wire->port_input ? "*" : "", + wire->port_input ? "input" : "output", log_id(wire->name), wire->width, log_id(wire->name))); + netlists_code += stringf("node %s %s PORT %s\n", log_id(wire->name), log_id(wire->name), netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str()); } } // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types - for (auto cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; std::string celltype_code, node_code; if (!ct.cell_known(cell->type)) - log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell->type)); + log_error("Found unknown cell type %s in module!\n", log_id(cell->type)); - celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type)); - node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + celltype_code = stringf("celltype %s", log_id(cell->type)); + node_code = stringf("node %s %s", log_id(cell->name), log_id(cell->type)); for (auto &port : cell->connections()) { RTLIL::SigSpec sig = sigmap(port.second); if (sig.size() != 0) { conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); - celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); - node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); + celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", log_id(port.first)); + node_code += stringf(" %s %s", log_id(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); } } for (auto ¶m : cell->parameters) { - celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first)); + celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first)); if (param.second.bits.size() != 32) { - node_code += stringf(" %s '", RTLIL::id2cstr(param.first)); + node_code += stringf(" %s '", log_id(param.first)); for (int i = param.second.bits.size()-1; i >= 0; i--) node_code += param.second.bits[i] == State::S1 ? "1" : "0"; } else - node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int()); + node_code += stringf(" %s 0x%x", log_id(param.first), param.second.as_int()); } celltypes_code.insert(celltype_code + "\n"); diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index 54dbb84af..83ed5e6e0 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -378,16 +378,16 @@ struct SimplecWorker void eval_cell(HierDirtyFlags *work, Cell *cell) { - if (cell->type.in("$_BUF_", "$_NOT_")) + if (cell->type.in(ID($_BUF_), ID($_NOT_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string expr; - if (cell->type == "$_BUF_") expr = a_expr; - if (cell->type == "$_NOT_") expr = "!" + a_expr; + if (cell->type == ID($_BUF_)) expr = a_expr; + if (cell->type == ID($_NOT_)) expr = "!" + a_expr; log_assert(y.wire); funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + @@ -397,24 +397,24 @@ struct SimplecWorker return; } - if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) + if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; string expr; - if (cell->type == "$_AND_") expr = stringf("%s & %s", a_expr.c_str(), b_expr.c_str()); - if (cell->type == "$_NAND_") expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str()); - if (cell->type == "$_OR_") expr = stringf("%s | %s", a_expr.c_str(), b_expr.c_str()); - if (cell->type == "$_NOR_") expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str()); - if (cell->type == "$_XOR_") expr = stringf("%s ^ %s", a_expr.c_str(), b_expr.c_str()); - if (cell->type == "$_XNOR_") expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str()); - if (cell->type == "$_ANDNOT_") expr = stringf("%s & (!%s)", a_expr.c_str(), b_expr.c_str()); - if (cell->type == "$_ORNOT_") expr = stringf("%s | (!%s)", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_AND_)) expr = stringf("%s & %s", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_NAND_)) expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_OR_)) expr = stringf("%s | %s", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_NOR_)) expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_XOR_)) expr = stringf("%s ^ %s", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_XNOR_)) expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_ANDNOT_)) expr = stringf("%s & (!%s)", a_expr.c_str(), b_expr.c_str()); + if (cell->type == ID($_ORNOT_)) expr = stringf("%s | (!%s)", a_expr.c_str(), b_expr.c_str()); log_assert(y.wire); funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + @@ -424,20 +424,20 @@ struct SimplecWorker return; } - if (cell->type.in("$_AOI3_", "$_OAI3_")) + if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); - SigBit c = sigmaps.at(work->module)(cell->getPort("\\C")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); + SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0"; string expr; - if (cell->type == "$_AOI3_") expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str()); - if (cell->type == "$_OAI3_") expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str()); + if (cell->type == ID($_AOI3_)) expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str()); + if (cell->type == ID($_OAI3_)) expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str()); log_assert(y.wire); funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + @@ -447,13 +447,13 @@ struct SimplecWorker return; } - if (cell->type.in("$_AOI4_", "$_OAI4_")) + if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); - SigBit c = sigmaps.at(work->module)(cell->getPort("\\C")); - SigBit d = sigmaps.at(work->module)(cell->getPort("\\D")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); + SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C)); + SigBit d = sigmaps.at(work->module)(cell->getPort(ID::D)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -461,8 +461,8 @@ struct SimplecWorker string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0"; string expr; - if (cell->type == "$_AOI4_") expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str()); - if (cell->type == "$_OAI4_") expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str()); + if (cell->type == ID($_AOI4_)) expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str()); + if (cell->type == ID($_OAI4_)) expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str()); log_assert(y.wire); funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + @@ -472,12 +472,12 @@ struct SimplecWorker return; } - if (cell->type.in("$_MUX_", "$_NMUX_")) + if (cell->type.in(ID($_MUX_), ID($_NMUX_))) { - SigBit a = sigmaps.at(work->module)(cell->getPort("\\A")); - SigBit b = sigmaps.at(work->module)(cell->getPort("\\B")); - SigBit s = sigmaps.at(work->module)(cell->getPort("\\S")); - SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y")); + SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); + SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); + SigBit s = sigmaps.at(work->module)(cell->getPort(ID::S)); + SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; @@ -485,8 +485,8 @@ struct SimplecWorker // casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933) string expr = stringf("%s ? %s(bool)%s : %s(bool)%s", s_expr.c_str(), - cell->type == "$_NMUX_" ? "!" : "", b_expr.c_str(), - cell->type == "$_NMUX_" ? "!" : "", a_expr.c_str()); + cell->type == ID($_NMUX_) ? "!" : "", b_expr.c_str(), + cell->type == ID($_NMUX_) ? "!" : "", a_expr.c_str()); log_assert(y.wire); funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + @@ -653,10 +653,10 @@ struct SimplecWorker for (Wire *w : module->wires()) { - if (w->attributes.count("\\init")) + if (w->attributes.count(ID::init)) { SigSpec sig = sigmaps.at(module)(w); - Const val = w->attributes.at("\\init"); + Const val = w->attributes.at(ID::init); val.bits.resize(GetSize(sig), State::Sx); for (int i = 0; i < GetSize(sig); i++) diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index ea252b6b9..3e67e55f2 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -135,7 +135,7 @@ struct Smt2Worker log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n", log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type)); - if (cell->type.in("$mem") && conn.first.in("\\RD_CLK", "\\WR_CLK")) + if (cell->type.in(ID($mem)) && conn.first.in(ID::RD_CLK, ID::WR_CLK)) { SigSpec clk = sigmap(conn.second); for (int i = 0; i < GetSize(clk); i++) @@ -143,19 +143,19 @@ struct Smt2Worker if (clk[i].wire == nullptr) continue; - if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_ENABLE" : "\\WR_CLK_ENABLE")[i] != State::S1) + if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_ENABLE : ID::WR_CLK_ENABLE)[i] != State::S1) continue; - if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_POLARITY" : "\\WR_CLK_POLARITY")[i] == State::S1) + if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_POLARITY : ID::WR_CLK_POLARITY)[i] == State::S1) clock_posedge.insert(clk[i]); else clock_negedge.insert(clk[i]); } } else - if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn.first.in("\\CLK", "\\C")) + if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && conn.first.in(ID::CLK, ID::C)) { - bool posedge = (cell->type == "$_DFF_N_") || (cell->type == "$dff" && cell->getParam("\\CLK_POLARITY").as_bool()); + bool posedge = (cell->type == ID($_DFF_N_)) || (cell->type == ID($dff) && cell->getParam(ID::CLK_POLARITY).as_bool()); for (auto bit : sigmap(conn.second)) { if (posedge) clock_posedge.insert(bit); @@ -367,15 +367,15 @@ struct Smt2Worker void export_gate(RTLIL::Cell *cell, std::string expr) { - RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").as_bit()); + RTLIL::SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); std::string processed_expr; for (char ch : expr) { - if (ch == 'A') processed_expr += get_bool(cell->getPort("\\A")); - else if (ch == 'B') processed_expr += get_bool(cell->getPort("\\B")); - else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C")); - else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D")); - else if (ch == 'S') processed_expr += get_bool(cell->getPort("\\S")); + if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A)); + else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B)); + else if (ch == 'C') processed_expr += get_bool(cell->getPort(ID::C)); + else if (ch == 'D') processed_expr += get_bool(cell->getPort(ID::D)); + else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S)); else processed_expr += ch; } @@ -391,23 +391,23 @@ struct Smt2Worker void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0) { RTLIL::SigSpec sig_a, sig_b; - RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); int width = GetSize(sig_y); if (type == 's' || type == 'd' || type == 'b') { - width = max(width, GetSize(cell->getPort("\\A"))); - if (cell->hasPort("\\B")) - width = max(width, GetSize(cell->getPort("\\B"))); + width = max(width, GetSize(cell->getPort(ID::A))); + if (cell->hasPort(ID::B)) + width = max(width, GetSize(cell->getPort(ID::B))); } - if (cell->hasPort("\\A")) { - sig_a = cell->getPort("\\A"); + if (cell->hasPort(ID::A)) { + sig_a = cell->getPort(ID::A); sig_a.extend_u0(width, is_signed); } - if (cell->hasPort("\\B")) { - sig_b = cell->getPort("\\B"); + if (cell->hasPort(ID::B)) { + sig_b = cell->getPort(ID::B); sig_b.extend_u0(width, is_signed && !(type == 's')); } @@ -416,7 +416,7 @@ struct Smt2Worker for (char ch : expr) { if (ch == 'A') processed_expr += get_bv(sig_a); else if (ch == 'B') processed_expr += get_bv(sig_b); - else if (ch == 'P') processed_expr += get_bv(cell->getPort("\\B")); + else if (ch == 'P') processed_expr += get_bv(cell->getPort(ID::B)); else if (ch == 'L') processed_expr += is_signed ? "a" : "l"; else if (ch == 'U') processed_expr += is_signed ? "s" : "u"; else processed_expr += ch; @@ -443,7 +443,7 @@ struct Smt2Worker void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val) { - RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); + RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); std::string processed_expr; for (char ch : expr) @@ -480,9 +480,9 @@ struct Smt2Worker exported_cells.insert(cell); recursive_cells.insert(cell); - if (cell->type == "$initstate") + if (cell->type == ID($initstate)) { - SigBit bit = sigmap(cell->getPort("\\Y").as_bit()); + SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n", get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit))); register_bool(bit, idcounter++); @@ -490,132 +490,132 @@ struct Smt2Worker return; } - if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_")) + if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_))) { registers.insert(cell); - makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort("\\Q"))); - register_bool(cell->getPort("\\Q"), idcounter++); + makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(ID::Q))); + register_bool(cell->getPort(ID::Q), idcounter++); recursive_cells.erase(cell); return; } - if (cell->type == "$_BUF_") return export_gate(cell, "A"); - if (cell->type == "$_NOT_") return export_gate(cell, "(not A)"); - if (cell->type == "$_AND_") return export_gate(cell, "(and A B)"); - if (cell->type == "$_NAND_") return export_gate(cell, "(not (and A B))"); - if (cell->type == "$_OR_") return export_gate(cell, "(or A B)"); - if (cell->type == "$_NOR_") return export_gate(cell, "(not (or A B))"); - if (cell->type == "$_XOR_") return export_gate(cell, "(xor A B)"); - if (cell->type == "$_XNOR_") return export_gate(cell, "(not (xor A B))"); - if (cell->type == "$_ANDNOT_") return export_gate(cell, "(and A (not B))"); - if (cell->type == "$_ORNOT_") return export_gate(cell, "(or A (not B))"); - if (cell->type == "$_MUX_") return export_gate(cell, "(ite S B A)"); - if (cell->type == "$_NMUX_") return export_gate(cell, "(not (ite S B A))"); - if (cell->type == "$_AOI3_") return export_gate(cell, "(not (or (and A B) C))"); - if (cell->type == "$_OAI3_") return export_gate(cell, "(not (and (or A B) C))"); - if (cell->type == "$_AOI4_") return export_gate(cell, "(not (or (and A B) (and C D)))"); - if (cell->type == "$_OAI4_") return export_gate(cell, "(not (and (or A B) (or C D)))"); + if (cell->type == ID($_BUF_)) return export_gate(cell, "A"); + if (cell->type == ID($_NOT_)) return export_gate(cell, "(not A)"); + if (cell->type == ID($_AND_)) return export_gate(cell, "(and A B)"); + if (cell->type == ID($_NAND_)) return export_gate(cell, "(not (and A B))"); + if (cell->type == ID($_OR_)) return export_gate(cell, "(or A B)"); + if (cell->type == ID($_NOR_)) return export_gate(cell, "(not (or A B))"); + if (cell->type == ID($_XOR_)) return export_gate(cell, "(xor A B)"); + if (cell->type == ID($_XNOR_)) return export_gate(cell, "(not (xor A B))"); + if (cell->type == ID($_ANDNOT_)) return export_gate(cell, "(and A (not B))"); + if (cell->type == ID($_ORNOT_)) return export_gate(cell, "(or A (not B))"); + if (cell->type == ID($_MUX_)) return export_gate(cell, "(ite S B A)"); + if (cell->type == ID($_NMUX_)) return export_gate(cell, "(not (ite S B A))"); + if (cell->type == ID($_AOI3_)) return export_gate(cell, "(not (or (and A B) C))"); + if (cell->type == ID($_OAI3_)) return export_gate(cell, "(not (and (or A B) C))"); + if (cell->type == ID($_AOI4_)) return export_gate(cell, "(not (or (and A B) (and C D)))"); + if (cell->type == ID($_OAI4_)) return export_gate(cell, "(not (and (or A B) (or C D)))"); // FIXME: $lut if (bvmode) { - if (cell->type.in("$ff", "$dff")) + if (cell->type.in(ID($ff), ID($dff))) { registers.insert(cell); - makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q"))); - register_bv(cell->getPort("\\Q"), idcounter++); + makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q))); + register_bv(cell->getPort(ID::Q), idcounter++); recursive_cells.erase(cell); return; } - if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) + if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) { registers.insert(cell); - string infostr = cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell); - if (cell->attributes.count("\\reg")) - infostr += " " + cell->attributes.at("\\reg").decode_string(); - decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort("\\Y")), infostr.c_str())); - if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\maximize")){ + string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell); + if (cell->attributes.count(ID::reg)) + infostr += " " + cell->attributes.at(ID::reg).decode_string(); + decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(ID::Y)), infostr.c_str())); + if (cell->getPort(ID::Y).is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute(ID::maximize)){ decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is maximized\n", cell->getPort("\\Y").as_wire()->name.str().c_str()); + log("Wire %s is maximized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str()); } - else if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\minimize")){ + else if (cell->getPort(ID::Y).is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute(ID::minimize)){ decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is minimized\n", cell->getPort("\\Y").as_wire()->name.str().c_str()); + log("Wire %s is minimized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str()); } - makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y"))); - if (cell->type == "$anyseq") + makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::Y))); + if (cell->type == ID($anyseq)) ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter)); - register_bv(cell->getPort("\\Y"), idcounter++); + register_bv(cell->getPort(ID::Y), idcounter++); recursive_cells.erase(cell); return; } - if (cell->type == "$and") return export_bvop(cell, "(bvand A B)"); - if (cell->type == "$or") return export_bvop(cell, "(bvor A B)"); - if (cell->type == "$xor") return export_bvop(cell, "(bvxor A B)"); - if (cell->type == "$xnor") return export_bvop(cell, "(bvxnor A B)"); + if (cell->type == ID($and)) return export_bvop(cell, "(bvand A B)"); + if (cell->type == ID($or)) return export_bvop(cell, "(bvor A B)"); + if (cell->type == ID($xor)) return export_bvop(cell, "(bvxor A B)"); + if (cell->type == ID($xnor)) return export_bvop(cell, "(bvxnor A B)"); - if (cell->type == "$shl") return export_bvop(cell, "(bvshl A B)", 's'); - if (cell->type == "$shr") return export_bvop(cell, "(bvlshr A B)", 's'); - if (cell->type == "$sshl") return export_bvop(cell, "(bvshl A B)", 's'); - if (cell->type == "$sshr") return export_bvop(cell, "(bvLshr A B)", 's'); + if (cell->type == ID($shl)) return export_bvop(cell, "(bvshl A B)", 's'); + if (cell->type == ID($shr)) return export_bvop(cell, "(bvlshr A B)", 's'); + if (cell->type == ID($sshl)) return export_bvop(cell, "(bvshl A B)", 's'); + if (cell->type == ID($sshr)) return export_bvop(cell, "(bvLshr A B)", 's'); - if (cell->type.in("$shift", "$shiftx")) { - if (cell->getParam("\\B_SIGNED").as_bool()) { + if (cell->type.in(ID($shift), ID($shiftx))) { + if (cell->getParam(ID::B_SIGNED).as_bool()) { return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) " "(bvlshr A B) (bvlshr A (bvneg B)))", - GetSize(cell->getPort("\\B")), 0), 's'); + GetSize(cell->getPort(ID::B)), 0), 's'); } else { return export_bvop(cell, "(bvlshr A B)", 's'); } } - if (cell->type == "$lt") return export_bvop(cell, "(bvUlt A B)", 'b'); - if (cell->type == "$le") return export_bvop(cell, "(bvUle A B)", 'b'); - if (cell->type == "$ge") return export_bvop(cell, "(bvUge A B)", 'b'); - if (cell->type == "$gt") return export_bvop(cell, "(bvUgt A B)", 'b'); - - if (cell->type == "$ne") return export_bvop(cell, "(distinct A B)", 'b'); - if (cell->type == "$nex") return export_bvop(cell, "(distinct A B)", 'b'); - if (cell->type == "$eq") return export_bvop(cell, "(= A B)", 'b'); - if (cell->type == "$eqx") return export_bvop(cell, "(= A B)", 'b'); - - if (cell->type == "$not") return export_bvop(cell, "(bvnot A)"); - if (cell->type == "$pos") return export_bvop(cell, "A"); - if (cell->type == "$neg") return export_bvop(cell, "(bvneg A)"); - - if (cell->type == "$add") return export_bvop(cell, "(bvadd A B)"); - if (cell->type == "$sub") return export_bvop(cell, "(bvsub A B)"); - if (cell->type == "$mul") return export_bvop(cell, "(bvmul A B)"); - if (cell->type == "$div") return export_bvop(cell, "(bvUdiv A B)", 'd'); - if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd'); - - if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool") && - 2*GetSize(cell->getPort("\\A").chunks()) < GetSize(cell->getPort("\\A"))) { - bool is_and = cell->type == "$reduce_and"; - string bits(GetSize(cell->getPort("\\A")), is_and ? '1' : '0'); + if (cell->type == ID($lt)) return export_bvop(cell, "(bvUlt A B)", 'b'); + if (cell->type == ID($le)) return export_bvop(cell, "(bvUle A B)", 'b'); + if (cell->type == ID($ge)) return export_bvop(cell, "(bvUge A B)", 'b'); + if (cell->type == ID($gt)) return export_bvop(cell, "(bvUgt A B)", 'b'); + + if (cell->type == ID($ne)) return export_bvop(cell, "(distinct A B)", 'b'); + if (cell->type == ID($nex)) return export_bvop(cell, "(distinct A B)", 'b'); + if (cell->type == ID($eq)) return export_bvop(cell, "(= A B)", 'b'); + if (cell->type == ID($eqx)) return export_bvop(cell, "(= A B)", 'b'); + + if (cell->type == ID($not)) return export_bvop(cell, "(bvnot A)"); + if (cell->type == ID($pos)) return export_bvop(cell, "A"); + if (cell->type == ID($neg)) return export_bvop(cell, "(bvneg A)"); + + if (cell->type == ID($add)) return export_bvop(cell, "(bvadd A B)"); + if (cell->type == ID($sub)) return export_bvop(cell, "(bvsub A B)"); + if (cell->type == ID($mul)) return export_bvop(cell, "(bvmul A B)"); + if (cell->type == ID($div)) return export_bvop(cell, "(bvUdiv A B)", 'd'); + if (cell->type == ID($mod)) return export_bvop(cell, "(bvUrem A B)", 'd'); + + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) && + 2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) { + bool is_and = cell->type == ID($reduce_and); + string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0'); return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b'); } - if (cell->type == "$reduce_and") return export_reduce(cell, "(and A)", true); - if (cell->type == "$reduce_or") return export_reduce(cell, "(or A)", false); - if (cell->type == "$reduce_xor") return export_reduce(cell, "(xor A)", false); - if (cell->type == "$reduce_xnor") return export_reduce(cell, "(not (xor A))", false); - if (cell->type == "$reduce_bool") return export_reduce(cell, "(or A)", false); + if (cell->type == ID($reduce_and)) return export_reduce(cell, "(and A)", true); + if (cell->type == ID($reduce_or)) return export_reduce(cell, "(or A)", false); + if (cell->type == ID($reduce_xor)) return export_reduce(cell, "(xor A)", false); + if (cell->type == ID($reduce_xnor)) return export_reduce(cell, "(not (xor A))", false); + if (cell->type == ID($reduce_bool)) return export_reduce(cell, "(or A)", false); - if (cell->type == "$logic_not") return export_reduce(cell, "(not (or A))", false); - if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false); - if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false); + if (cell->type == ID($logic_not)) return export_reduce(cell, "(not (or A))", false); + if (cell->type == ID($logic_and)) return export_reduce(cell, "(and (or A) (or B))", false); + if (cell->type == ID($logic_or)) return export_reduce(cell, "(or A B)", false); - if (cell->type.in("$mux", "$pmux")) + if (cell->type.in(ID($mux), ID($pmux))) { - int width = GetSize(cell->getPort("\\Y")); - std::string processed_expr = get_bv(cell->getPort("\\A")); + int width = GetSize(cell->getPort(ID::Y)); + std::string processed_expr = get_bv(cell->getPort(ID::A)); - RTLIL::SigSpec sig_b = cell->getPort("\\B"); - RTLIL::SigSpec sig_s = cell->getPort("\\S"); + RTLIL::SigSpec sig_b = cell->getPort(ID::B); + RTLIL::SigSpec sig_s = cell->getPort(ID::S); get_bv(sig_b); get_bv(sig_s); @@ -626,7 +626,7 @@ struct Smt2Worker if (verbose) log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell)); - RTLIL::SigSpec sig = sigmap(cell->getPort("\\Y")); + RTLIL::SigSpec sig = sigmap(cell->getPort(ID::Y)); decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n", get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig))); register_bv(sig, idcounter++); @@ -637,19 +637,19 @@ struct Smt2Worker // FIXME: $slice $concat } - if (memmode && cell->type == "$mem") + if (memmode && cell->type == ID($mem)) { int arrayid = idcounter++; memarrays[cell] = arrayid; - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); - int rd_ports = cell->getParam("\\RD_PORTS").as_int(); - int wr_ports = cell->getParam("\\WR_PORTS").as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int rd_ports = cell->getParam(ID::RD_PORTS).as_int(); + int wr_ports = cell->getParam(ID::WR_PORTS).as_int(); bool async_read = false; - if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) { - if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_zero()) + if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) { + if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero()) log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module)); async_read = true; } @@ -665,8 +665,8 @@ struct Smt2Worker if (statebv) { - int mem_size = cell->getParam("\\SIZE").as_int(); - int mem_offset = cell->getParam("\\OFFSET").as_int(); + int mem_size = cell->getParam(ID::SIZE).as_int(); + int mem_offset = cell->getParam(ID::OFFSET).as_int(); makebits(memstate, width*mem_size, get_id(cell)); decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n", @@ -674,11 +674,11 @@ struct Smt2Worker for (int i = 0; i < rd_ports; i++) { - SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits); - SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width); + SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits); + SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width); std::string addr = get_bv(addr_sig); - if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool()) + if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool()) log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! " "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module)); @@ -717,11 +717,11 @@ struct Smt2Worker for (int i = 0; i < rd_ports; i++) { - SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits); - SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width); + SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits); + SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width); std::string addr = get_bv(addr_sig); - if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool()) + if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool()) log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! " "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module)); @@ -801,9 +801,9 @@ struct Smt2Worker pool<SigBit> reg_bits; for (auto cell : module->cells()) - if (cell->type.in("$ff", "$dff", "$_FF_", "$_DFF_P_", "$_DFF_N_")) { + if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_))) { // not using sigmap -- we want the net directly at the dff output - for (auto bit : cell->getPort("\\Q")) + for (auto bit : cell->getPort(ID::Q)) reg_bits.insert(bit); } @@ -812,7 +812,7 @@ struct Smt2Worker for (auto bit : SigSpec(wire)) if (reg_bits.count(bit)) is_register = true; - if (wire->port_id || is_register || wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\')) { + if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) { RTLIL::SigSpec sig = sigmap(wire); if (wire->port_input) decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width)); @@ -820,7 +820,7 @@ struct Smt2Worker decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width)); if (is_register) decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width)); - if (wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\')) + if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width)); if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig))) decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire), @@ -854,9 +854,9 @@ struct Smt2Worker vector<string> init_list; for (auto wire : module->wires()) - if (wire->attributes.count("\\init")) { + if (wire->attributes.count(ID::init)) { RTLIL::SigSpec sig = sigmap(wire); - Const val = wire->attributes.at("\\init"); + Const val = wire->attributes.at(ID::init); val.bits.resize(GetSize(sig), State::Sx); if (bvmode && GetSize(sig) > 1) { Const mask(State::S1, GetSize(sig)); @@ -885,31 +885,31 @@ struct Smt2Worker for (auto cell : module->cells()) { - if (cell->type.in("$assert", "$assume", "$cover")) + if (cell->type.in(ID($assert), ID($assume), ID($cover))) { - int &id = cell->type == "$assert" ? assert_id : - cell->type == "$assume" ? assume_id : - cell->type == "$cover" ? cover_id : *(int*)nullptr; + int &id = cell->type == ID($assert) ? assert_id : + cell->type == ID($assume) ? assume_id : + cell->type == ID($cover) ? cover_id : *(int*)nullptr; - char postfix = cell->type == "$assert" ? 'a' : - cell->type == "$assume" ? 'u' : - cell->type == "$cover" ? 'c' : 0; + char postfix = cell->type == ID($assert) ? 'a' : + cell->type == ID($assume) ? 'u' : + cell->type == ID($cover) ? 'c' : 0; - string name_a = get_bool(cell->getPort("\\A")); - string name_en = get_bool(cell->getPort("\\EN")); - string infostr = (cell->name[0] == '$' && cell->attributes.count("\\src")) ? cell->attributes.at("\\src").decode_string() : get_id(cell); + string name_a = get_bool(cell->getPort(ID::A)); + string name_en = get_bool(cell->getPort(ID::EN)); + string infostr = (cell->name[0] == '$' && cell->attributes.count(ID::src)) ? cell->attributes.at(ID::src).decode_string() : get_id(cell); decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str())); - if (cell->type == "$cover") + if (cell->type == ID($cover)) decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n", get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell))); else decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n", get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell))); - if (cell->type == "$assert") + if (cell->type == ID($assert)) assert_list.push_back(stringf("(|%s_a %d| state)", get_id(module), id)); - else if (cell->type == "$assume") + else if (cell->type == ID($assume)) assume_list.push_back(stringf("(|%s_u %d| state)", get_id(module), id)); id++; @@ -965,44 +965,44 @@ struct Smt2Worker for (auto cell : this_regs) { - if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_")) + if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_))) { - std::string expr_d = get_bool(cell->getPort("\\D")); - std::string expr_q = get_bool(cell->getPort("\\Q"), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q")))); - ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort("\\Q")).c_str(), get_bool(cell->getPort("\\Q"), "other_state").c_str())); + std::string expr_d = get_bool(cell->getPort(ID::D)); + std::string expr_q = get_bool(cell->getPort(ID::Q), "next_state"); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q)))); + ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)).c_str(), get_bool(cell->getPort(ID::Q), "other_state").c_str())); } - if (cell->type.in("$ff", "$dff")) + if (cell->type.in(ID($ff), ID($dff))) { - std::string expr_d = get_bv(cell->getPort("\\D")); - std::string expr_q = get_bv(cell->getPort("\\Q"), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q")))); - ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Q")).c_str(), get_bv(cell->getPort("\\Q"), "other_state").c_str())); + std::string expr_d = get_bv(cell->getPort(ID::D)); + std::string expr_q = get_bv(cell->getPort(ID::Q), "next_state"); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q)))); + ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)).c_str(), get_bv(cell->getPort(ID::Q), "other_state").c_str())); } - if (cell->type.in("$anyconst", "$allconst")) + if (cell->type.in(ID($anyconst), ID($allconst))) { - std::string expr_d = get_bv(cell->getPort("\\Y")); - std::string expr_q = get_bv(cell->getPort("\\Y"), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Y")))); - if (cell->type == "$anyconst") - ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Y")).c_str(), get_bv(cell->getPort("\\Y"), "other_state").c_str())); + std::string expr_d = get_bv(cell->getPort(ID::Y)); + std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state"); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y)))); + if (cell->type == ID($anyconst)) + ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str())); } - if (cell->type == "$mem") + if (cell->type == ID($mem)) { int arrayid = memarrays.at(cell); - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); - int wr_ports = cell->getParam("\\WR_PORTS").as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int wr_ports = cell->getParam(ID::WR_PORTS).as_int(); bool async_read = false; string initial_memstate, final_memstate; - if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) { - log_assert(cell->getParam("\\WR_CLK_ENABLE").is_fully_zero()); + if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) { + log_assert(cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero()); async_read = true; initial_memstate = stringf("%s#%d#0", get_id(module), arrayid); final_memstate = stringf("%s#%d#final", get_id(module), arrayid); @@ -1010,8 +1010,8 @@ struct Smt2Worker if (statebv) { - int mem_size = cell->getParam("\\SIZE").as_int(); - int mem_offset = cell->getParam("\\OFFSET").as_int(); + int mem_size = cell->getParam(ID::SIZE).as_int(); + int mem_offset = cell->getParam(ID::OFFSET).as_int(); if (async_read) { makebits(final_memstate, width*mem_size, get_id(cell)); @@ -1019,9 +1019,9 @@ struct Smt2Worker for (int i = 0; i < wr_ports; i++) { - SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits); - SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width); - SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width); + SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits); + SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width); + SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width); std::string addr = get_bv(addr_sig); std::string data = get_bv(data_sig); @@ -1066,9 +1066,9 @@ struct Smt2Worker for (int i = 0; i < wr_ports; i++) { - SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits); - SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width); - SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width); + SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits); + SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width); + SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width); std::string addr = get_bv(addr_sig); std::string data = get_bv(data_sig); @@ -1104,8 +1104,8 @@ struct Smt2Worker if (async_read) hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(cell))); - Const init_data = cell->getParam("\\INIT"); - int memsize = cell->getParam("\\SIZE").as_int(); + Const init_data = cell->getParam(ID::INIT); + int memsize = cell->getParam(ID::SIZE).as_int(); for (int i = 0; i < memsize; i++) { @@ -1394,7 +1394,7 @@ struct Smt2Backend : public Backend { log("\n"); log("For this proof we create the following template (test.tpl).\n"); log("\n"); - log(" ; we need QF_UFBV for this poof\n"); + log(" ; we need QF_UFBV for this proof\n"); log(" (set-logic QF_UFBV)\n"); log("\n"); log(" ; insert the auto-generated code here\n"); @@ -1523,12 +1523,12 @@ struct Smt2Backend : public Backend { for (auto &dep : it.second) if (module_deps.count(dep) > 0) goto not_ready_yet; - // log("Next in topological sort: %s\n", RTLIL::id2cstr(it.first->name)); + // log("Next in topological sort: %s\n", log_id(it.first->name)); sorted_modules.push_back(it.first); not_ready_yet:; } if (sorted_modules_idx == sorted_modules.size()) - log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", RTLIL::id2cstr(module_deps.begin()->first->name)); + log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", log_id(module_deps.begin()->first->name)); while (sorted_modules_idx < sorted_modules.size()) module_deps.erase(sorted_modules.at(sorted_modules_idx++)); } @@ -1540,7 +1540,7 @@ struct Smt2Backend : public Backend { for (auto module : sorted_modules) for (auto cell : module->cells()) - if (cell->type.in("$allconst", "$allseq")) + if (cell->type.in(ID($allconst), ID($allseq))) goto found_forall; if (0) { found_forall: diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 4c691716e..69f59df79 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -704,8 +704,12 @@ class SmtIo: if msg is not None: print("%s waiting for solver (%s)" % (self.timestamp(), msg), flush=True) - result = "" - while result not in ["sat", "unsat"]: + if self.forall: + result = self.read() + while result not in ["sat", "unsat", "unknown"]: + print("%s %s: %s" % (self.timestamp(), self.solver, result)) + result = self.read() + else: result = self.read() if self.debug_file: diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index f755307bf..7113ebc97 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -219,30 +219,30 @@ struct SmvWorker if (wire->port_input) inputvars.push_back(stringf("%s : unsigned word[%d]; -- %s", cid(wire->name), wire->width, log_id(wire))); - if (wire->attributes.count("\\init")) - assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at("\\init")))); + if (wire->attributes.count(ID::init)) + assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at(ID::init)))); } for (auto cell : module->cells()) { // FIXME: $slice, $concat, $mem - if (cell->type.in("$assert")) + if (cell->type.in(ID($assert))) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_en = cell->getPort("\\EN"); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_en = cell->getPort(ID::EN); invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a))); continue; } - if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) + if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_b = cell->getPort("\\B"); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_b = cell->getPort(ID::B); - int width_y = GetSize(cell->getPort("\\Y")); + int width_y = GetSize(cell->getPort(ID::Y)); int shift_b_width = GetSize(sig_b); int width_ay = max(GetSize(sig_a), width_y); int width = width_ay; @@ -254,12 +254,12 @@ struct SmvWorker break; } - bool signed_a = cell->getParam("\\A_SIGNED").as_bool(); - bool signed_b = cell->getParam("\\B_SIGNED").as_bool(); - string op = cell->type.in("$shl", "$sshl") ? "<<" : ">>"; + bool signed_a = cell->getParam(ID::A_SIGNED).as_bool(); + bool signed_b = cell->getParam(ID::B_SIGNED).as_bool(); + string op = cell->type.in(ID($shl), ID($sshl)) ? "<<" : ">>"; string expr, expr_a; - if (cell->type == "$sshr" && signed_a) + if (cell->type == ID($sshr) && signed_a) { expr_a = rvalue_s(sig_a, width); expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a.c_str(), op.c_str(), rvalue(sig_b.extract(0, shift_b_width)), width_y); @@ -268,7 +268,7 @@ struct SmvWorker rvalue(sig_b.extract(shift_b_width, GetSize(sig_b) - shift_b_width)), GetSize(sig_b) - shift_b_width, rvalue(sig_a[GetSize(sig_a)-1]), width_y, width_y, expr.c_str()); } - else if (cell->type.in("$shift", "$shiftx") && signed_b) + else if (cell->type.in(ID($shift), ID($shiftx)) && signed_b) { expr_a = rvalue_u(sig_a, width); @@ -292,7 +292,7 @@ struct SmvWorker } else { - if (cell->type.in("$shift", "$shiftx") || !signed_a) + if (cell->type.in(ID($shift), ID($shiftx)) || !signed_a) expr_a = rvalue_u(sig_a, width); else expr_a = stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a, width_ay), width); @@ -303,272 +303,272 @@ struct SmvWorker GetSize(sig_b)-shift_b_width, width_y, expr.c_str()); } - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str())); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str())); continue; } - if (cell->type.in("$not", "$pos", "$neg")) + if (cell->type.in(ID($not), ID($pos), ID($neg))) { - int width = GetSize(cell->getPort("\\Y")); + int width = GetSize(cell->getPort(ID::Y)); string expr_a, op; - if (cell->type == "$not") op = "!"; - if (cell->type == "$pos") op = ""; - if (cell->type == "$neg") op = "-"; + if (cell->type == ID($not)) op = "!"; + if (cell->type == ID($pos)) op = ""; + if (cell->type == ID($neg)) op = "-"; - if (cell->getParam("\\A_SIGNED").as_bool()) + if (cell->getParam(ID::A_SIGNED).as_bool()) { - definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort("\\Y")), - op.c_str(), rvalue_s(cell->getPort("\\A"), width))); + definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)), + op.c_str(), rvalue_s(cell->getPort(ID::A), width))); } else { - definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), - op.c_str(), rvalue_u(cell->getPort("\\A"), width))); + definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), + op.c_str(), rvalue_u(cell->getPort(ID::A), width))); } continue; } - if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor")) + if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor))) { - int width = GetSize(cell->getPort("\\Y")); + int width = GetSize(cell->getPort(ID::Y)); string expr_a, expr_b, op; - if (cell->type == "$add") op = "+"; - if (cell->type == "$sub") op = "-"; - if (cell->type == "$mul") op = "*"; - if (cell->type == "$and") op = "&"; - if (cell->type == "$or") op = "|"; - if (cell->type == "$xor") op = "xor"; - if (cell->type == "$xnor") op = "xnor"; + if (cell->type == ID($add)) op = "+"; + if (cell->type == ID($sub)) op = "-"; + if (cell->type == ID($mul)) op = "*"; + if (cell->type == ID($and)) op = "&"; + if (cell->type == ID($or)) op = "|"; + if (cell->type == ID($xor)) op = "xor"; + if (cell->type == ID($xnor)) op = "xnor"; - if (cell->getParam("\\A_SIGNED").as_bool()) + if (cell->getParam(ID::A_SIGNED).as_bool()) { - definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")), - rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width))); + definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)), + rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width))); } else { - definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")), - rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width))); + definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)), + rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width))); } continue; } - if (cell->type.in("$div", "$mod")) + if (cell->type.in(ID($div), ID($mod))) { - int width_y = GetSize(cell->getPort("\\Y")); - int width = max(width_y, GetSize(cell->getPort("\\A"))); - width = max(width, GetSize(cell->getPort("\\B"))); + int width_y = GetSize(cell->getPort(ID::Y)); + int width = max(width_y, GetSize(cell->getPort(ID::A))); + width = max(width, GetSize(cell->getPort(ID::B))); string expr_a, expr_b, op; - if (cell->type == "$div") op = "/"; - if (cell->type == "$mod") op = "mod"; + if (cell->type == ID($div)) op = "/"; + if (cell->type == ID($mod)) op = "mod"; - if (cell->getParam("\\A_SIGNED").as_bool()) + if (cell->getParam(ID::A_SIGNED).as_bool()) { - definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort("\\Y")), - rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width), width_y)); + definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)), + rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y)); } else { - definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort("\\Y")), - rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width), width_y)); + definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(ID::Y)), + rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width), width_y)); } continue; } - if (cell->type.in("$eq", "$ne", "$eqx", "$nex", "$lt", "$le", "$ge", "$gt")) + if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt))) { - int width = max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B"))); + int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))); string expr_a, expr_b, op; - if (cell->type == "$eq") op = "="; - if (cell->type == "$ne") op = "!="; - if (cell->type == "$eqx") op = "="; - if (cell->type == "$nex") op = "!="; - if (cell->type == "$lt") op = "<"; - if (cell->type == "$le") op = "<="; - if (cell->type == "$ge") op = ">="; - if (cell->type == "$gt") op = ">"; + if (cell->type == ID($eq)) op = "="; + if (cell->type == ID($ne)) op = "!="; + if (cell->type == ID($eqx)) op = "="; + if (cell->type == ID($nex)) op = "!="; + if (cell->type == ID($lt)) op = "<"; + if (cell->type == ID($le)) op = "<="; + if (cell->type == ID($ge)) op = ">="; + if (cell->type == ID($gt)) op = ">"; - if (cell->getParam("\\A_SIGNED").as_bool()) + if (cell->getParam(ID::A_SIGNED).as_bool()) { - expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\A")), width); - expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\B")), width); + expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width); + expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width); } else { - expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort("\\A")), width); - expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort("\\B")), width); + expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::A)), width); + expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::B)), width); } - definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")), - expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort("\\Y")))); + definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)), + expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(ID::Y)))); continue; } - if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { - int width_a = GetSize(cell->getPort("\\A")); - int width_y = GetSize(cell->getPort("\\Y")); - const char *expr_a = rvalue(cell->getPort("\\A")); - const char *expr_y = lvalue(cell->getPort("\\Y")); + int width_a = GetSize(cell->getPort(ID::A)); + int width_y = GetSize(cell->getPort(ID::Y)); + const char *expr_a = rvalue(cell->getPort(ID::A)); + const char *expr_y = lvalue(cell->getPort(ID::Y)); string expr; - if (cell->type == "$reduce_and") expr = stringf("%s = !0ub%d_0", expr_a, width_a); - if (cell->type == "$reduce_or") expr = stringf("%s != 0ub%d_0", expr_a, width_a); - if (cell->type == "$reduce_bool") expr = stringf("%s != 0ub%d_0", expr_a, width_a); + if (cell->type == ID($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a); + if (cell->type == ID($reduce_or)) expr = stringf("%s != 0ub%d_0", expr_a, width_a); + if (cell->type == ID($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a); definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y)); continue; } - if (cell->type.in("$reduce_xor", "$reduce_xnor")) + if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { - int width_y = GetSize(cell->getPort("\\Y")); - const char *expr_y = lvalue(cell->getPort("\\Y")); + int width_y = GetSize(cell->getPort(ID::Y)); + const char *expr_y = lvalue(cell->getPort(ID::Y)); string expr; - for (auto bit : cell->getPort("\\A")) { + for (auto bit : cell->getPort(ID::A)) { if (!expr.empty()) expr += " xor "; expr += rvalue(bit); } - if (cell->type == "$reduce_xnor") + if (cell->type == ID($reduce_xnor)) expr = "!(" + expr + ")"; definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y)); continue; } - if (cell->type.in("$logic_and", "$logic_or")) + if (cell->type.in(ID($logic_and), ID($logic_or))) { - int width_a = GetSize(cell->getPort("\\A")); - int width_b = GetSize(cell->getPort("\\B")); - int width_y = GetSize(cell->getPort("\\Y")); + int width_a = GetSize(cell->getPort(ID::A)); + int width_b = GetSize(cell->getPort(ID::B)); + int width_y = GetSize(cell->getPort(ID::Y)); - string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a); - string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort("\\B")), width_b); - const char *expr_y = lvalue(cell->getPort("\\Y")); + string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a); + string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::B)), width_b); + const char *expr_y = lvalue(cell->getPort(ID::Y)); string expr; - if (cell->type == "$logic_and") expr = expr_a + " & " + expr_b; - if (cell->type == "$logic_or") expr = expr_a + " | " + expr_b; + if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b; + if (cell->type == ID($logic_or)) expr = expr_a + " | " + expr_b; definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y)); continue; } - if (cell->type.in("$logic_not")) + if (cell->type.in(ID($logic_not))) { - int width_a = GetSize(cell->getPort("\\A")); - int width_y = GetSize(cell->getPort("\\Y")); + int width_a = GetSize(cell->getPort(ID::A)); + int width_y = GetSize(cell->getPort(ID::Y)); - string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a); - const char *expr_y = lvalue(cell->getPort("\\Y")); + string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a); + const char *expr_y = lvalue(cell->getPort(ID::Y)); definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y)); continue; } - if (cell->type.in("$mux", "$pmux")) + if (cell->type.in(ID($mux), ID($pmux))) { - int width = GetSize(cell->getPort("\\Y")); - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_b = cell->getPort("\\B"); - SigSpec sig_s = cell->getPort("\\S"); + int width = GetSize(cell->getPort(ID::Y)); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_s = cell->getPort(ID::S); string expr; for (int i = 0; i < GetSize(sig_s); i++) expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width))); expr += rvalue(sig_a); - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str())); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str())); continue; } - if (cell->type == "$dff") + if (cell->type == ID($dff)) { - vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort("\\Q")), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q")))); - assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort("\\Q")), rvalue(cell->getPort("\\D")))); + vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(ID::Q)), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q)))); + assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(ID::Q)), rvalue(cell->getPort(ID::D)))); continue; } - if (cell->type.in("$_BUF_", "$_NOT_")) + if (cell->type.in(ID($_BUF_), ID($_NOT_))) { - string op = cell->type == "$_NOT_" ? "!" : ""; - definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), op.c_str(), rvalue(cell->getPort("\\A")))); + string op = cell->type == ID($_NOT_) ? "!" : ""; + definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op.c_str(), rvalue(cell->getPort(ID::A)))); continue; } - if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) + if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { string op; - if (cell->type.in("$_AND_", "$_NAND_", "$_ANDNOT_")) op = "&"; - if (cell->type.in("$_OR_", "$_NOR_", "$_ORNOT_")) op = "|"; - if (cell->type.in("$_XOR_")) op = "xor"; - if (cell->type.in("$_XNOR_")) op = "xnor"; + if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_))) op = "&"; + if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_))) op = "|"; + if (cell->type.in(ID($_XOR_))) op = "xor"; + if (cell->type.in(ID($_XNOR_))) op = "xnor"; - if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) - definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B")))); + if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) + definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); else - if (cell->type.in("$_NAND_", "$_NOR_")) - definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B")))); + if (cell->type.in(ID($_NAND_), ID($_NOR_))) + definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); else - definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B")))); + definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); continue; } - if (cell->type == "$_MUX_") + if (cell->type == ID($_MUX_)) { - definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A")))); + definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); continue; } - if (cell->type == "$_NMUX_") + if (cell->type == ID($_NMUX_)) { - definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A")))); + definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); continue; } - if (cell->type == "$_AOI3_") + if (cell->type == ID($_AOI3_)) { - definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")))); + definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)))); continue; } - if (cell->type == "$_OAI3_") + if (cell->type == ID($_OAI3_)) { - definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")))); + definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)))); continue; } - if (cell->type == "$_AOI4_") + if (cell->type == ID($_AOI4_)) { - definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); + definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D)))); continue; } - if (cell->type == "$_OAI4_") + if (cell->type == ID($_OAI4_)) { - definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort("\\Y")), - rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); + definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)), + rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D)))); continue; } diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 6738a4bbd..84e93b61b 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -70,14 +70,13 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De idict<IdString, 1> inums; int cell_counter = 0, conn_counter = 0, nc_counter = 0; - for (auto &cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; f << stringf("X%d", cell_counter++); std::vector<RTLIL::SigSpec> port_sigs; - if (design->modules_.count(cell->type) == 0) + if (design->module(cell->type) == nullptr) { log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", log_id(cell->type), log_id(module), log_id(cell)); @@ -88,11 +87,10 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De } else { - RTLIL::Module *mod = design->modules_.at(cell->type); + RTLIL::Module *mod = design->module(cell->type); std::vector<RTLIL::Wire*> ports; - for (auto wire_it : mod->wires_) { - RTLIL::Wire *wire = wire_it.second; + for (auto wire : mod->wires()) { if (wire->port_id == 0) continue; while (int(ports.size()) < wire->port_id) @@ -202,16 +200,15 @@ struct SpiceBackend : public Backend { extra_args(f, filename, args, argidx); if (top_module_name.empty()) - for (auto & mod_it:design->modules_) - if (mod_it.second->get_bool_attribute("\\top")) - top_module_name = mod_it.first.str(); + for (auto module : design->modules()) + if (module->get_bool_attribute(ID::top)) + top_module_name = module->name.str(); *f << stringf("* SPICE netlist generated by %s\n", yosys_version_str); *f << stringf("\n"); - for (auto module_it : design->modules_) + for (auto module : design->modules()) { - RTLIL::Module *module = module_it.second; if (module->get_blackbox_attribute()) continue; @@ -226,8 +223,7 @@ struct SpiceBackend : public Backend { } std::vector<RTLIL::Wire*> ports; - for (auto wire_it : module->wires_) { - RTLIL::Wire *wire = wire_it.second; + for (auto wire : module->wires()) { if (wire->port_id == 0) continue; while (int(ports.size()) < wire->port_id) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 19541f1c4..5467e250b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -73,12 +73,12 @@ void reset_auto_counter(RTLIL::Module *module) reset_auto_counter_id(module->name, false); - for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) - reset_auto_counter_id(it->second->name, true); + for (auto w : module->wires()) + reset_auto_counter_id(w->name, true); - for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) { - reset_auto_counter_id(it->second->name, true); - reset_auto_counter_id(it->second->type, false); + for (auto cell : module->cells()) { + reset_auto_counter_id(cell->name, true); + reset_auto_counter_id(cell->type, false); } for (auto it = module->processes.begin(); it != module->processes.end(); ++it) @@ -378,7 +378,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, if (attr2comment) as_comment = true; for (auto it = attributes.begin(); it != attributes.end(); ++it) { - if (it->first == "\\init" && regattr) continue; + if (it->first == ID::init && regattr) continue; f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf(" = "); if (modattr && (it->second == State::S0 || it->second == Const(0))) @@ -423,9 +423,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); if (reg_wires.count(wire->name)) { f << stringf("%s" "reg%s %s", indent.c_str(), range.c_str(), id(wire->name).c_str()); - if (wire->attributes.count("\\init")) { + if (wire->attributes.count(ID::init)) { f << stringf(" = "); - dump_const(f, wire->attributes.at("\\init")); + dump_const(f, wire->attributes.at(ID::init)); } f << stringf(";\n"); } else if (!wire->port_input && !wire->port_output) @@ -451,9 +451,9 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) + if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort(ID::Q)) { - RTLIL::SigSpec sig = cell->getPort("\\Q"); + RTLIL::SigSpec sig = cell->getPort(ID::Q); if (GetSize(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; @@ -488,7 +488,7 @@ no_special_reg_name: void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); @@ -498,7 +498,7 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "A", true); f << stringf(" %s ", op.c_str()); @@ -509,9 +509,9 @@ void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { - if (cell->type == "$_NOT_") { + if (cell->type == ID($_NOT_)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); f << stringf("~"); dump_attributes(f, "", cell->attributes, ' '); @@ -520,34 +520,34 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) { + if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) + if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_))) f << stringf("~("); dump_cell_expr_port(f, cell, "A", false); f << stringf(" "); - if (cell->type.in("$_AND_", "$_NAND_", "$_ANDNOT_")) + if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_))) f << stringf("&"); - if (cell->type.in("$_OR_", "$_NOR_", "$_ORNOT_")) + if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_))) f << stringf("|"); - if (cell->type.in("$_XOR_", "$_XNOR_")) + if (cell->type.in(ID($_XOR_), ID($_XNOR_))) f << stringf("^"); dump_attributes(f, "", cell->attributes, ' '); f << stringf(" "); - if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) + if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) f << stringf("~("); dump_cell_expr_port(f, cell, "B", false); - if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) + if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) f << stringf(")"); f << stringf(";\n"); return true; } - if (cell->type == "$_MUX_") { + if (cell->type == ID($_MUX_)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); @@ -559,9 +559,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$_NMUX_") { + if (cell->type == ID($_NMUX_)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = !("); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); @@ -573,14 +573,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.in("$_AOI3_", "$_OAI3_")) { + if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); - f << stringf(cell->type == "$_AOI3_" ? " & " : " | "); + f << stringf(cell->type == ID($_AOI3_) ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); - f << stringf(cell->type == "$_AOI3_" ? ") |" : ") &"); + f << stringf(cell->type == ID($_AOI3_) ? ") |" : ") &"); dump_attributes(f, "", cell->attributes, ' '); f << stringf(" "); dump_cell_expr_port(f, cell, "C", false); @@ -588,18 +588,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.in("$_AOI4_", "$_OAI4_")) { + if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); - f << stringf(cell->type == "$_AOI4_" ? " & " : " | "); + f << stringf(cell->type == ID($_AOI4_) ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); - f << stringf(cell->type == "$_AOI4_" ? ") |" : ") &"); + f << stringf(cell->type == ID($_AOI4_) ? ") |" : ") &"); dump_attributes(f, "", cell->attributes, ' '); f << stringf(" ("); dump_cell_expr_port(f, cell, "C", false); - f << stringf(cell->type == "$_AOI4_" ? " & " : " | "); + f << stringf(cell->type == ID($_AOI4_) ? " & " : " | "); dump_cell_expr_port(f, cell, "D", false); f << stringf("));\n"); return true; @@ -608,26 +608,26 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.begins_with("$_DFF_")) { std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); + bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name); if (!out_is_reg_wire) { f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str()); - dump_reg_init(f, cell->getPort("\\Q")); + dump_reg_init(f, cell->getPort(ID::Q)); f << ";\n"; } dump_attributes(f, indent, cell->attributes); f << stringf("%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->getPort("\\C")); + dump_sigspec(f, cell->getPort(ID::C)); if (cell->type[7] != '_') { f << stringf(" or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->getPort("\\R")); + dump_sigspec(f, cell->getPort(ID::R)); } f << stringf(")\n"); if (cell->type[7] != '_') { f << stringf("%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); - dump_sigspec(f, cell->getPort("\\R")); + dump_sigspec(f, cell->getPort(ID::R)); f << stringf(")\n"); f << stringf("%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); f << stringf("%s" " else\n", indent.c_str()); @@ -639,7 +639,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Q")); + dump_sigspec(f, cell->getPort(ID::Q)); f << stringf(" = %s;\n", reg_name.c_str()); } @@ -651,30 +651,30 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); + bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name); if (!out_is_reg_wire) { f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str()); - dump_reg_init(f, cell->getPort("\\Q")); + dump_reg_init(f, cell->getPort(ID::Q)); f << ";\n"; } dump_attributes(f, indent, cell->attributes); f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->getPort("\\C")); + dump_sigspec(f, cell->getPort(ID::C)); f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->getPort("\\R")); + dump_sigspec(f, cell->getPort(ID::R)); f << stringf(")\n"); f << stringf("%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); - dump_sigspec(f, cell->getPort("\\R")); + dump_sigspec(f, cell->getPort(ID::R)); f << stringf(")\n"); f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); f << stringf("%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(")\n"); f << stringf("%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); @@ -685,7 +685,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Q")); + dump_sigspec(f, cell->getPort(ID::Q)); f << stringf(" = %s;\n", reg_name.c_str()); } @@ -697,117 +697,117 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) #define HANDLE_BINOP(_type, _operator) \ if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator); return true; } - HANDLE_UNIOP("$not", "~") - HANDLE_UNIOP("$pos", "+") - HANDLE_UNIOP("$neg", "-") - - HANDLE_BINOP("$and", "&") - HANDLE_BINOP("$or", "|") - HANDLE_BINOP("$xor", "^") - HANDLE_BINOP("$xnor", "~^") - - HANDLE_UNIOP("$reduce_and", "&") - HANDLE_UNIOP("$reduce_or", "|") - HANDLE_UNIOP("$reduce_xor", "^") - HANDLE_UNIOP("$reduce_xnor", "~^") - HANDLE_UNIOP("$reduce_bool", "|") - - HANDLE_BINOP("$shl", "<<") - HANDLE_BINOP("$shr", ">>") - HANDLE_BINOP("$sshl", "<<<") - HANDLE_BINOP("$sshr", ">>>") - - HANDLE_BINOP("$lt", "<") - HANDLE_BINOP("$le", "<=") - HANDLE_BINOP("$eq", "==") - HANDLE_BINOP("$ne", "!=") - HANDLE_BINOP("$eqx", "===") - HANDLE_BINOP("$nex", "!==") - HANDLE_BINOP("$ge", ">=") - HANDLE_BINOP("$gt", ">") - - HANDLE_BINOP("$add", "+") - HANDLE_BINOP("$sub", "-") - HANDLE_BINOP("$mul", "*") - HANDLE_BINOP("$div", "/") - HANDLE_BINOP("$mod", "%") - HANDLE_BINOP("$pow", "**") - - HANDLE_UNIOP("$logic_not", "!") - HANDLE_BINOP("$logic_and", "&&") - HANDLE_BINOP("$logic_or", "||") + HANDLE_UNIOP(ID($not), "~") + HANDLE_UNIOP(ID($pos), "+") + HANDLE_UNIOP(ID($neg), "-") + + HANDLE_BINOP(ID($and), "&") + HANDLE_BINOP(ID($or), "|") + HANDLE_BINOP(ID($xor), "^") + HANDLE_BINOP(ID($xnor), "~^") + + HANDLE_UNIOP(ID($reduce_and), "&") + HANDLE_UNIOP(ID($reduce_or), "|") + HANDLE_UNIOP(ID($reduce_xor), "^") + HANDLE_UNIOP(ID($reduce_xnor), "~^") + HANDLE_UNIOP(ID($reduce_bool), "|") + + HANDLE_BINOP(ID($shl), "<<") + HANDLE_BINOP(ID($shr), ">>") + HANDLE_BINOP(ID($sshl), "<<<") + HANDLE_BINOP(ID($sshr), ">>>") + + HANDLE_BINOP(ID($lt), "<") + HANDLE_BINOP(ID($le), "<=") + HANDLE_BINOP(ID($eq), "==") + HANDLE_BINOP(ID($ne), "!=") + HANDLE_BINOP(ID($eqx), "===") + HANDLE_BINOP(ID($nex), "!==") + HANDLE_BINOP(ID($ge), ">=") + HANDLE_BINOP(ID($gt), ">") + + HANDLE_BINOP(ID($add), "+") + HANDLE_BINOP(ID($sub), "-") + HANDLE_BINOP(ID($mul), "*") + HANDLE_BINOP(ID($div), "/") + HANDLE_BINOP(ID($mod), "%") + HANDLE_BINOP(ID($pow), "**") + + HANDLE_UNIOP(ID($logic_not), "!") + HANDLE_BINOP(ID($logic_and), "&&") + HANDLE_BINOP(ID($logic_or), "||") #undef HANDLE_UNIOP #undef HANDLE_BINOP - if (cell->type == "$shift") + if (cell->type == ID($shift)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - if (cell->getParam("\\B_SIGNED").as_bool()) + if (cell->getParam(ID::B_SIGNED).as_bool()) { f << stringf("$signed("); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(")"); f << stringf(" < 0 ? "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" << - "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" : "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" >> "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); } else { - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" >> "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); } f << stringf(";\n"); return true; } - if (cell->type == "$shiftx") + if (cell->type == ID($shiftx)) { std::string temp_id = next_auto_id(); - f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str()); - dump_sigspec(f, cell->getPort("\\A")); + f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str()); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = %s[", temp_id.c_str()); - if (cell->getParam("\\B_SIGNED").as_bool()) + if (cell->getParam(ID::B_SIGNED).as_bool()) f << stringf("$signed("); - dump_sigspec(f, cell->getPort("\\B")); - if (cell->getParam("\\B_SIGNED").as_bool()) + dump_sigspec(f, cell->getPort(ID::B)); + if (cell->getParam(ID::B_SIGNED).as_bool()) f << stringf(")"); - f << stringf(" +: %d", cell->getParam("\\Y_WIDTH").as_int()); + f << stringf(" +: %d", cell->getParam(ID::Y_WIDTH).as_int()); f << stringf("];\n"); return true; } - if (cell->type == "$mux") + if (cell->type == ID($mux)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(" ? "); dump_attributes(f, "", cell->attributes, ' '); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" : "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); return true; } - if (cell->type == "$pmux") + if (cell->type == ID($pmux)) { - int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->getPort("\\S").size(); + int width = cell->parameters[ID::WIDTH].as_int(); + int s_width = cell->getPort(ID::S).size(); std::string func_name = cellname(cell); f << stringf("%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -839,76 +839,76 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "endfunction\n", indent.c_str()); f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = %s(", func_name.c_str()); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(", "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(", "); - dump_sigspec(f, cell->getPort("\\S")); + dump_sigspec(f, cell->getPort(ID::S)); f << stringf(");\n"); return true; } - if (cell->type == "$tribuf") + if (cell->type == ID($tribuf)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort("\\EN")); + dump_sigspec(f, cell->getPort(ID::EN)); f << stringf(" ? "); - dump_sigspec(f, cell->getPort("\\A")); - f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int()); + dump_sigspec(f, cell->getPort(ID::A)); + f << stringf(" : %d'bz;\n", cell->parameters.at(ID::WIDTH).as_int()); return true; } - if (cell->type == "$slice") + if (cell->type == ID($slice)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_sigspec(f, cell->getPort("\\A")); - f << stringf(" >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); + dump_sigspec(f, cell->getPort(ID::A)); + f << stringf(" >> %d;\n", cell->parameters.at(ID::OFFSET).as_int()); return true; } - if (cell->type == "$concat") + if (cell->type == ID($concat)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = { "); - dump_sigspec(f, cell->getPort("\\B")); + dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" , "); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(" };\n"); return true; } - if (cell->type == "$lut") + if (cell->type == ID($lut)) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); + dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_const(f, cell->parameters.at("\\LUT")); + dump_const(f, cell->parameters.at(ID::LUT)); f << stringf(" >> "); dump_attributes(f, "", cell->attributes, ' '); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); return true; } - if (cell->type == "$dffsr") + if (cell->type == ID($dffsr)) { - SigSpec sig_clk = cell->getPort("\\CLK"); - SigSpec sig_set = cell->getPort("\\SET"); - SigSpec sig_clr = cell->getPort("\\CLR"); - SigSpec sig_d = cell->getPort("\\D"); - SigSpec sig_q = cell->getPort("\\Q"); + SigSpec sig_clk = cell->getPort(ID::CLK); + SigSpec sig_set = cell->getPort(ID::SET); + SigSpec sig_clr = cell->getPort(ID::CLR); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); - int width = cell->parameters["\\WIDTH"].as_int(); - bool pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); - bool pol_set = cell->parameters["\\SET_POLARITY"].as_bool(); - bool pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool(); + int width = cell->parameters[ID::WIDTH].as_int(); + bool pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool(); + bool pol_set = cell->parameters[ID::SET_POLARITY].as_bool(); + bool pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool(); std::string reg_name = cellname(cell); bool out_is_reg_wire = is_reg_wire(sig_q, reg_name); @@ -950,43 +950,43 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.in("$dff", "$adff", "$dffe")) + if (cell->type.in(ID($dff), ID($adff), ID($dffe))) { RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst; bool pol_clk, pol_arst = false, pol_en = false; - sig_clk = cell->getPort("\\CLK"); - pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); + sig_clk = cell->getPort(ID::CLK); + pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool(); - if (cell->type == "$adff") { - sig_arst = cell->getPort("\\ARST"); - pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool(); - val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); + if (cell->type == ID($adff)) { + sig_arst = cell->getPort(ID::ARST); + pol_arst = cell->parameters[ID::ARST_POLARITY].as_bool(); + val_arst = RTLIL::SigSpec(cell->parameters[ID::ARST_VALUE]); } - if (cell->type == "$dffe") { - sig_en = cell->getPort("\\EN"); - pol_en = cell->parameters["\\EN_POLARITY"].as_bool(); + if (cell->type == ID($dffe)) { + sig_en = cell->getPort(ID::EN); + pol_en = cell->parameters[ID::EN_POLARITY].as_bool(); } std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); + bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name); if (!out_is_reg_wire) { - f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); - dump_reg_init(f, cell->getPort("\\Q")); + f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str()); + dump_reg_init(f, cell->getPort(ID::Q)); f << ";\n"; } f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_clk ? "pos" : "neg"); dump_sigspec(f, sig_clk); - if (cell->type == "$adff") { + if (cell->type == ID($adff)) { f << stringf(" or %sedge ", pol_arst ? "pos" : "neg"); dump_sigspec(f, sig_arst); } f << stringf(")\n"); - if (cell->type == "$adff") { + if (cell->type == ID($adff)) { f << stringf("%s" " if (%s", indent.c_str(), pol_arst ? "" : "!"); dump_sigspec(f, sig_arst); f << stringf(")\n"); @@ -996,7 +996,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" " else\n", indent.c_str()); } - if (cell->type == "$dffe") { + if (cell->type == ID($dffe)) { f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!"); dump_sigspec(f, sig_en); f << stringf(")\n"); @@ -1008,27 +1008,27 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Q")); + dump_sigspec(f, cell->getPort(ID::Q)); f << stringf(" = %s;\n", reg_name.c_str()); } return true; } - if (cell->type == "$dlatch") + if (cell->type == ID($dlatch)) { RTLIL::SigSpec sig_en; bool pol_en = false; - sig_en = cell->getPort("\\EN"); - pol_en = cell->parameters["\\EN_POLARITY"].as_bool(); + sig_en = cell->getPort(ID::EN); + pol_en = cell->parameters[ID::EN_POLARITY].as_bool(); std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); + bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name); if (!out_is_reg_wire) { - f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); - dump_reg_init(f, cell->getPort("\\Q")); + f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str()); + dump_reg_init(f, cell->getPort(ID::Q)); f << ";\n"; } @@ -1044,22 +1044,22 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Q")); + dump_sigspec(f, cell->getPort(ID::Q)); f << stringf(" = %s;\n", reg_name.c_str()); } return true; } - if (cell->type == "$mem") + if (cell->type == ID($mem)) { - RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string(); - std::string mem_id = id(cell->parameters["\\MEMID"].decode_string()); - int abits = cell->parameters["\\ABITS"].as_int(); - int size = cell->parameters["\\SIZE"].as_int(); - int offset = cell->parameters["\\OFFSET"].as_int(); - int width = cell->parameters["\\WIDTH"].as_int(); - bool use_init = !(RTLIL::SigSpec(cell->parameters["\\INIT"]).is_fully_undef()); + RTLIL::IdString memid = cell->parameters[ID::MEMID].decode_string(); + std::string mem_id = id(cell->parameters[ID::MEMID].decode_string()); + int abits = cell->parameters[ID::ABITS].as_int(); + int size = cell->parameters[ID::SIZE].as_int(); + int offset = cell->parameters[ID::OFFSET].as_int(); + int width = cell->parameters[ID::WIDTH].as_int(); + bool use_init = !(RTLIL::SigSpec(cell->parameters[ID::INIT]).is_fully_undef()); // for memory block make something like: // reg [7:0] memid [3:0]; @@ -1099,7 +1099,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { for (int i=0; i<size; i++) { - RTLIL::Const element = cell->parameters["\\INIT"].extract(i*width, width); + RTLIL::Const element = cell->parameters[ID::INIT].extract(i*width, width); for (int j=0; j<element.size(); j++) { switch (element[element.size()-j-1]) @@ -1123,7 +1123,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) for (int i=0; i<size; i++) { f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i); - dump_const(f, cell->parameters["\\INIT"].extract(i*width, width)); + dump_const(f, cell->parameters[ID::INIT].extract(i*width, width)); f << stringf(";\n"); } f << stringf("%s" "end\n", indent.c_str()); @@ -1137,19 +1137,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) // create a list of reg declarations std::vector<std::string> lof_reg_declarations; - int nread_ports = cell->parameters["\\RD_PORTS"].as_int(); + int nread_ports = cell->parameters[ID::RD_PORTS].as_int(); RTLIL::SigSpec sig_rd_clk, sig_rd_en, sig_rd_data, sig_rd_addr; bool use_rd_clk, rd_clk_posedge, rd_transparent; // read ports for (int i=0; i < nread_ports; i++) { - sig_rd_clk = cell->getPort("\\RD_CLK").extract(i); - sig_rd_en = cell->getPort("\\RD_EN").extract(i); - sig_rd_data = cell->getPort("\\RD_DATA").extract(i*width, width); - sig_rd_addr = cell->getPort("\\RD_ADDR").extract(i*abits, abits); - use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool(); - rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool(); - rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool(); + sig_rd_clk = cell->getPort(ID::RD_CLK).extract(i); + sig_rd_en = cell->getPort(ID::RD_EN).extract(i); + sig_rd_data = cell->getPort(ID::RD_DATA).extract(i*width, width); + sig_rd_addr = cell->getPort(ID::RD_ADDR).extract(i*abits, abits); + use_rd_clk = cell->parameters[ID::RD_CLK_ENABLE].extract(i).as_bool(); + rd_clk_posedge = cell->parameters[ID::RD_CLK_POLARITY].extract(i).as_bool(); + rd_transparent = cell->parameters[ID::RD_TRANSPARENT].extract(i).as_bool(); if (use_rd_clk) { { @@ -1221,18 +1221,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } - int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int(); + int nwrite_ports = cell->parameters[ID::WR_PORTS].as_int(); RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en; bool wr_clk_posedge; // write ports for (int i=0; i < nwrite_ports; i++) { - sig_wr_clk = cell->getPort("\\WR_CLK").extract(i); - sig_wr_data = cell->getPort("\\WR_DATA").extract(i*width, width); - sig_wr_addr = cell->getPort("\\WR_ADDR").extract(i*abits, abits); - sig_wr_en = cell->getPort("\\WR_EN").extract(i*width, width); - wr_clk_posedge = cell->parameters["\\WR_CLK_POLARITY"].extract(i).as_bool(); + sig_wr_clk = cell->getPort(ID::WR_CLK).extract(i); + sig_wr_data = cell->getPort(ID::WR_DATA).extract(i*width, width); + sig_wr_addr = cell->getPort(ID::WR_ADDR).extract(i*abits, abits); + sig_wr_en = cell->getPort(ID::WR_EN).extract(i*width, width); + wr_clk_posedge = cell->parameters[ID::WR_CLK_POLARITY].extract(i).as_bool(); { std::ostringstream os; dump_sigspec(os, sig_wr_clk); @@ -1319,66 +1319,66 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.in("$assert", "$assume", "$cover")) + if (cell->type.in(ID($assert), ID($assume), ID($cover))) { f << stringf("%s" "always @* if (", indent.c_str()); - dump_sigspec(f, cell->getPort("\\EN")); + dump_sigspec(f, cell->getPort(ID::EN)); f << stringf(") %s(", cell->type.c_str()+1); - dump_sigspec(f, cell->getPort("\\A")); + dump_sigspec(f, cell->getPort(ID::A)); f << stringf(");\n"); return true; } - if (cell->type.in("$specify2", "$specify3")) + if (cell->type.in(ID($specify2), ID($specify3))) { f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str()); - SigSpec en = cell->getPort("\\EN"); + SigSpec en = cell->getPort(ID::EN); if (en != State::S1) { f << stringf("if ("); - dump_sigspec(f, cell->getPort("\\EN")); + dump_sigspec(f, cell->getPort(ID::EN)); f << stringf(") "); } f << "("; - if (cell->type == "$specify3" && cell->getParam("\\EDGE_EN").as_bool()) - f << (cell->getParam("\\EDGE_POL").as_bool() ? "posedge ": "negedge "); + if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool()) + f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge "); - dump_sigspec(f, cell->getPort("\\SRC")); + dump_sigspec(f, cell->getPort(ID::SRC)); f << " "; - if (cell->getParam("\\SRC_DST_PEN").as_bool()) - f << (cell->getParam("\\SRC_DST_POL").as_bool() ? "+": "-"); - f << (cell->getParam("\\FULL").as_bool() ? "*> ": "=> "); + if (cell->getParam(ID::SRC_DST_PEN).as_bool()) + f << (cell->getParam(ID::SRC_DST_POL).as_bool() ? "+": "-"); + f << (cell->getParam(ID::FULL).as_bool() ? "*> ": "=> "); - if (cell->type == "$specify3") { + if (cell->type == ID($specify3)) { f << "("; - dump_sigspec(f, cell->getPort("\\DST")); + dump_sigspec(f, cell->getPort(ID::DST)); f << " "; - if (cell->getParam("\\DAT_DST_PEN").as_bool()) - f << (cell->getParam("\\DAT_DST_POL").as_bool() ? "+": "-"); + if (cell->getParam(ID::DAT_DST_PEN).as_bool()) + f << (cell->getParam(ID::DAT_DST_POL).as_bool() ? "+": "-"); f << ": "; - dump_sigspec(f, cell->getPort("\\DAT")); + dump_sigspec(f, cell->getPort(ID::DAT)); f << ")"; } else { - dump_sigspec(f, cell->getPort("\\DST")); + dump_sigspec(f, cell->getPort(ID::DST)); } bool bak_decimal = decimal; decimal = 1; f << ") = ("; - dump_const(f, cell->getParam("\\T_RISE_MIN")); + dump_const(f, cell->getParam(ID::T_RISE_MIN)); f << ":"; - dump_const(f, cell->getParam("\\T_RISE_TYP")); + dump_const(f, cell->getParam(ID::T_RISE_TYP)); f << ":"; - dump_const(f, cell->getParam("\\T_RISE_MAX")); + dump_const(f, cell->getParam(ID::T_RISE_MAX)); f << ", "; - dump_const(f, cell->getParam("\\T_FALL_MIN")); + dump_const(f, cell->getParam(ID::T_FALL_MIN)); f << ":"; - dump_const(f, cell->getParam("\\T_FALL_TYP")); + dump_const(f, cell->getParam(ID::T_FALL_TYP)); f << ":"; - dump_const(f, cell->getParam("\\T_FALL_MAX")); + dump_const(f, cell->getParam(ID::T_FALL_MAX)); f << ");\n"; decimal = bak_decimal; @@ -1387,49 +1387,49 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$specrule") + if (cell->type == ID($specrule)) { f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str()); - string spec_type = cell->getParam("\\TYPE").decode_string(); + IdString spec_type = cell->getParam(ID::TYPE).decode_string(); f << stringf("%s(", spec_type.c_str()); - if (cell->getParam("\\SRC_PEN").as_bool()) - f << (cell->getParam("\\SRC_POL").as_bool() ? "posedge ": "negedge "); - dump_sigspec(f, cell->getPort("\\SRC")); + if (cell->getParam(ID::SRC_PEN).as_bool()) + f << (cell->getParam(ID::SRC_POL).as_bool() ? "posedge ": "negedge "); + dump_sigspec(f, cell->getPort(ID::SRC)); - if (cell->getPort("\\SRC_EN") != State::S1) { + if (cell->getPort(ID::SRC_EN) != State::S1) { f << " &&& "; - dump_sigspec(f, cell->getPort("\\SRC_EN")); + dump_sigspec(f, cell->getPort(ID::SRC_EN)); } f << ", "; - if (cell->getParam("\\DST_PEN").as_bool()) - f << (cell->getParam("\\DST_POL").as_bool() ? "posedge ": "negedge "); - dump_sigspec(f, cell->getPort("\\DST")); + if (cell->getParam(ID::DST_PEN).as_bool()) + f << (cell->getParam(ID::DST_POL).as_bool() ? "posedge ": "negedge "); + dump_sigspec(f, cell->getPort(ID::DST)); - if (cell->getPort("\\DST_EN") != State::S1) { + if (cell->getPort(ID::DST_EN) != State::S1) { f << " &&& "; - dump_sigspec(f, cell->getPort("\\DST_EN")); + dump_sigspec(f, cell->getPort(ID::DST_EN)); } bool bak_decimal = decimal; decimal = 1; f << ", "; - dump_const(f, cell->getParam("\\T_LIMIT_MIN")); + dump_const(f, cell->getParam(ID::T_LIMIT_MIN)); f << ": "; - dump_const(f, cell->getParam("\\T_LIMIT_TYP")); + dump_const(f, cell->getParam(ID::T_LIMIT_TYP)); f << ": "; - dump_const(f, cell->getParam("\\T_LIMIT_MAX")); + dump_const(f, cell->getParam(ID::T_LIMIT_MAX)); - if (spec_type == "$setuphold" || spec_type == "$recrem" || spec_type == "$fullskew") { + if (spec_type.in(ID($setuphold), ID($recrem), ID($fullskew))) { f << ", "; - dump_const(f, cell->getParam("\\T_LIMIT2_MIN")); + dump_const(f, cell->getParam(ID::T_LIMIT2_MIN)); f << ": "; - dump_const(f, cell->getParam("\\T_LIMIT2_TYP")); + dump_const(f, cell->getParam(ID::T_LIMIT2_TYP)); f << ": "; - dump_const(f, cell->getParam("\\T_LIMIT2_MAX")); + dump_const(f, cell->getParam(ID::T_LIMIT2_MAX)); } f << ");\n"; @@ -1513,9 +1513,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } - if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { + if (siminit && reg_ct.count(cell->type) && cell->hasPort(ID::Q)) { std::stringstream ss; - dump_reg_init(ss, cell->getPort("\\Q")); + dump_reg_init(ss, cell->getPort(ID::Q)); if (!ss.str().empty()) { f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str()); f << ss.str(); @@ -1698,9 +1698,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) active_initdata.clear(); for (auto wire : module->wires()) - if (wire->attributes.count("\\init")) { + if (wire->attributes.count(ID::init)) { SigSpec sig = active_sigmap(wire); - Const val = wire->attributes.at("\\init"); + Const val = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++) if (val[i] == State::S0 || val[i] == State::S1) active_initdata[sig[i]] = val[i]; @@ -1719,13 +1719,12 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) if (!noexpr) { std::set<std::pair<RTLIL::Wire*,int>> reg_bits; - for (auto &it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = it.second; - if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q")) + if (!reg_ct.count(cell->type) || !cell->hasPort(ID::Q)) continue; - RTLIL::SigSpec sig = cell->getPort("\\Q"); + RTLIL::SigSpec sig = cell->getPort(ID::Q); if (sig.is_chunk()) { RTLIL::SigChunk chunk = sig.as_chunk(); @@ -1734,9 +1733,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i)); } } - for (auto &it : module->wires_) + for (auto wire : module->wires()) { - RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0) goto this_wire_aint_reg; @@ -1751,8 +1749,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { keep_running = false; - for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) { - RTLIL::Wire *wire = it->second; + for (auto wire : module->wires()) { if (wire->port_id == port_id) { if (port_id != 1) f << stringf(", "); @@ -1764,14 +1761,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } f << stringf(");\n"); - for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) - dump_wire(f, indent + " ", it->second); + for (auto w : module->wires()) + dump_wire(f, indent + " ", w); for (auto it = module->memories.begin(); it != module->memories.end(); ++it) dump_memory(f, indent + " ", it->second); - for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) - dump_cell(f, indent + " ", it->second); + for (auto cell : module->cells()) + dump_cell(f, indent + " ", cell); for (auto it = module->processes.begin(); it != module->processes.end(); ++it) dump_process(f, indent + " ", it->second); @@ -1892,31 +1889,31 @@ struct VerilogBackend : public Backend { reg_wires.clear(); reg_ct.clear(); - reg_ct.insert("$dff"); - reg_ct.insert("$adff"); - reg_ct.insert("$dffe"); - reg_ct.insert("$dlatch"); - - reg_ct.insert("$_DFF_N_"); - reg_ct.insert("$_DFF_P_"); - - reg_ct.insert("$_DFF_NN0_"); - reg_ct.insert("$_DFF_NN1_"); - reg_ct.insert("$_DFF_NP0_"); - reg_ct.insert("$_DFF_NP1_"); - reg_ct.insert("$_DFF_PN0_"); - reg_ct.insert("$_DFF_PN1_"); - reg_ct.insert("$_DFF_PP0_"); - reg_ct.insert("$_DFF_PP1_"); - - reg_ct.insert("$_DFFSR_NNN_"); - reg_ct.insert("$_DFFSR_NNP_"); - reg_ct.insert("$_DFFSR_NPN_"); - reg_ct.insert("$_DFFSR_NPP_"); - reg_ct.insert("$_DFFSR_PNN_"); - reg_ct.insert("$_DFFSR_PNP_"); - reg_ct.insert("$_DFFSR_PPN_"); - reg_ct.insert("$_DFFSR_PPP_"); + reg_ct.insert(ID($dff)); + reg_ct.insert(ID($adff)); + reg_ct.insert(ID($dffe)); + reg_ct.insert(ID($dlatch)); + + reg_ct.insert(ID($_DFF_N_)); + reg_ct.insert(ID($_DFF_P_)); + + reg_ct.insert(ID($_DFF_NN0_)); + reg_ct.insert(ID($_DFF_NN1_)); + reg_ct.insert(ID($_DFF_NP0_)); + reg_ct.insert(ID($_DFF_NP1_)); + reg_ct.insert(ID($_DFF_PN0_)); + reg_ct.insert(ID($_DFF_PN1_)); + reg_ct.insert(ID($_DFF_PP0_)); + reg_ct.insert(ID($_DFF_PP1_)); + + reg_ct.insert(ID($_DFFSR_NNN_)); + reg_ct.insert(ID($_DFFSR_NNP_)); + reg_ct.insert(ID($_DFFSR_NPN_)); + reg_ct.insert(ID($_DFFSR_NPP_)); + reg_ct.insert(ID($_DFFSR_PNN_)); + reg_ct.insert(ID($_DFFSR_PNP_)); + reg_ct.insert(ID($_DFFSR_PPN_)); + reg_ct.insert(ID($_DFFSR_PPP_)); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -1995,16 +1992,16 @@ struct VerilogBackend : public Backend { design->sort(); *f << stringf("/* Generated by %s */\n", yosys_version_str); - for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) { - if (it->second->get_blackbox_attribute() != blackboxes) + for (auto module : design->modules()) { + if (module->get_blackbox_attribute() != blackboxes) continue; - if (selected && !design->selected_whole_module(it->first)) { - if (design->selected_module(it->first)) - log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first)); + if (selected && !design->selected_whole_module(module->name)) { + if (design->selected_module(module->name)) + log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name)); continue; } - log("Dumping module `%s'.\n", it->first.c_str()); - dump_module(*f, "", it->second); + log("Dumping module `%s'.\n", module->name.c_str()); + dump_module(*f, "", module); } auto_name_map.clear(); diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc index 34373487d..756b7faac 100644 --- a/examples/cxx-api/evaldemo.cc +++ b/examples/cxx-api/evaldemo.cc @@ -29,8 +29,8 @@ struct EvalDemoPass : public Pass if (module == nullptr) log_error("No top module found!\n"); - Wire *wire_a = module->wire("\\A"); - Wire *wire_y = module->wire("\\Y"); + Wire *wire_a = module->wire(ID::A); + Wire *wire_y = module->wire(ID::Y); if (wire_a == nullptr) log_error("No wire A found!\n"); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index a42569301..92cf92fa8 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -30,7 +30,9 @@ #include <libkern/OSByteOrder.h> #define __builtin_bswap32 OSSwapInt32 #endif +#ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS +#endif #include <inttypes.h> #include "kernel/yosys.h" @@ -117,7 +119,7 @@ struct ConstEvalAig sig2deps[output].insert(output); RTLIL::Cell *cell = sig2driver.at(output); - RTLIL::SigBit sig_a = cell->getPort("\\A"); + RTLIL::SigBit sig_a = cell->getPort(ID::A); sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation // that may occur does so here, and // not mid insertion (below) @@ -125,8 +127,8 @@ struct ConstEvalAig if (!inputs.count(sig_a)) compute_deps(sig_a, inputs); - if (cell->type == "$_AND_") { - RTLIL::SigSpec sig_b = cell->getPort("\\B"); + if (cell->type == ID($_AND_)) { + RTLIL::SigSpec sig_b = cell->getPort(ID::B); sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation // that may occur does so here, and // not mid insertion (below) @@ -135,34 +137,34 @@ struct ConstEvalAig if (!inputs.count(sig_b)) compute_deps(sig_b, inputs); } - else if (cell->type == "$_NOT_") { + else if (cell->type == ID($_NOT_)) { } else log_abort(); } bool eval(RTLIL::Cell *cell) { - RTLIL::SigBit sig_y = cell->getPort("\\Y"); + RTLIL::SigBit sig_y = cell->getPort(ID::Y); if (values_map.count(sig_y)) return true; - RTLIL::SigBit sig_a = cell->getPort("\\A"); + RTLIL::SigBit sig_a = cell->getPort(ID::A); if (!eval(sig_a)) return false; RTLIL::State eval_ret = RTLIL::Sx; - if (cell->type == "$_NOT_") { + if (cell->type == ID($_NOT_)) { if (sig_a == State::S0) eval_ret = State::S1; else if (sig_a == State::S1) eval_ret = State::S0; } - else if (cell->type == "$_AND_") { + else if (cell->type == ID($_AND_)) { if (sig_a == State::S0) { eval_ret = State::S0; goto eval_end; } { - RTLIL::SigBit sig_b = cell->getPort("\\B"); + RTLIL::SigBit sig_b = cell->getPort(ID::B); if (!eval(sig_b)) return false; if (sig_b == State::S0) { @@ -444,7 +446,7 @@ void AigerReader::parse_xaiger() } } else if (c == 'r') { - uint32_t dataSize = parse_xaiger_literal(f); + uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); flopNum = parse_xaiger_literal(f); log_debug("flopNum = %u\n", flopNum); log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); @@ -478,9 +480,9 @@ void AigerReader::parse_xaiger() log_assert(boxUniqueId > 0); uint32_t oldBoxNum = parse_xaiger_literal(f); RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId)); - cell->setPort("\\i", SigSpec(State::S0, boxInputs)); - cell->setPort("\\o", SigSpec(State::S0, boxOutputs)); - cell->attributes["\\abc9_box_seq"] = oldBoxNum; + cell->setPort(ID(i), SigSpec(State::S0, boxInputs)); + cell->setPort(ID(o), SigSpec(State::S0, boxOutputs)); + cell->attributes[ID::abc9_box_seq] = oldBoxNum; boxes.emplace_back(cell); } } @@ -548,18 +550,18 @@ void AigerReader::parse_aiger_ascii() log_error("Line %u cannot be interpreted as a latch!\n", line_count); if (l3 == 0) - q_wire->attributes["\\init"] = State::S0; + q_wire->attributes[ID::init] = State::S0; else if (l3 == 1) - q_wire->attributes["\\init"] = State::S1; + q_wire->attributes[ID::init] = State::S1; else if (l3 == l1) { - //q_wire->attributes["\\init"] = RTLIL::Sx; + //q_wire->attributes[ID::init] = RTLIL::Sx; } else log_error("Line %u has invalid reset literal for latch!\n", line_count); } else { // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = State::S0; + q_wire->attributes[ID::init] = State::S0; } latches.push_back(q_wire); } @@ -673,18 +675,18 @@ void AigerReader::parse_aiger_binary() log_error("Line %u cannot be interpreted as a latch!\n", line_count); if (l3 == 0) - q_wire->attributes["\\init"] = State::S0; + q_wire->attributes[ID::init] = State::S0; else if (l3 == 1) - q_wire->attributes["\\init"] = State::S1; + q_wire->attributes[ID::init] = State::S1; else if (l3 == l1) { - //q_wire->attributes["\\init"] = RTLIL::Sx; + //q_wire->attributes[ID::init] = RTLIL::Sx; } else log_error("Line %u has invalid reset literal for latch!\n", line_count); } else { // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = State::S0; + q_wire->attributes[ID::init] = State::S0; } latches.push_back(q_wire); } @@ -747,7 +749,7 @@ void AigerReader::post_process() { unsigned ci_count = 0, co_count = 0; for (auto cell : boxes) { - for (auto &bit : cell->connections_.at("\\i")) { + for (auto &bit : cell->connections_.at(ID(i))) { log_assert(bit == State::S0); log_assert(co_count < outputs.size()); bit = outputs[co_count++]; @@ -755,7 +757,7 @@ void AigerReader::post_process() log_assert(bit.wire->port_output); bit.wire->port_output = false; } - for (auto &bit : cell->connections_.at("\\o")) { + for (auto &bit : cell->connections_.at(ID(o))) { log_assert(bit == State::S0); log_assert((piNum + ci_count) < inputs.size()); bit = inputs[piNum + ci_count++]; @@ -776,10 +778,10 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - auto ff = module->addCell(NEW_ID, "$__ABC9_FF_"); - ff->setPort("\\D", d); - ff->setPort("\\Q", q); - ff->attributes["\\abc9_mergeability"] = mergeability[i]; + auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_)); + ff->setPort(ID::D, d); + ff->setPort(ID::Q, q); + ff->attributes[ID::abc9_mergeability] = mergeability[i]; } dict<RTLIL::IdString, int> wideports_cache; @@ -866,7 +868,7 @@ void AigerReader::post_process() int init; mf >> init; if (init < 2) - wire->attributes["\\init"] = init; + wire->attributes[ID::init] = init; } else if (type == "box") { RTLIL::Cell* cell = module->cell(stringf("$box%d", variable)); @@ -929,8 +931,8 @@ void AigerReader::post_process() design->add(module); for (auto cell : module->cells().to_vector()) { - if (cell->type != "$lut") continue; - auto y_port = cell->getPort("\\Y").as_bit(); + if (cell->type != ID($lut)) continue; + auto y_port = cell->getPort(ID::Y).as_bit(); if (y_port.wire->width == 1) module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str())); else diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 650c7a937..2b6002548 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -952,9 +952,9 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast current_module = new AstModule; current_module->ast = NULL; current_module->name = ast->str; - current_module->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, + current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column); - current_module->set_bool_attribute("\\cells_not_processed"); + current_module->set_bool_attribute(ID::cells_not_processed); current_ast_mod = ast; AstNode *ast_before_simplify; @@ -1007,61 +1007,61 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast log("--- END OF AST DUMP ---\n"); } - if (flag_nowb && ast->attributes.count("\\whitebox")) { - delete ast->attributes.at("\\whitebox"); - ast->attributes.erase("\\whitebox"); + if (flag_nowb && ast->attributes.count(ID::whitebox)) { + delete ast->attributes.at(ID::whitebox); + ast->attributes.erase(ID::whitebox); } - if (ast->attributes.count("\\lib_whitebox")) { + if (ast->attributes.count(ID::lib_whitebox)) { if (!flag_lib || flag_nowb) { - delete ast->attributes.at("\\lib_whitebox"); - ast->attributes.erase("\\lib_whitebox"); + delete ast->attributes.at(ID::lib_whitebox); + ast->attributes.erase(ID::lib_whitebox); } else { - if (ast->attributes.count("\\whitebox")) { - delete ast->attributes.at("\\whitebox"); - ast->attributes.erase("\\whitebox"); + if (ast->attributes.count(ID::whitebox)) { + delete ast->attributes.at(ID::whitebox); + ast->attributes.erase(ID::whitebox); } - AstNode *n = ast->attributes.at("\\lib_whitebox"); - ast->attributes["\\whitebox"] = n; - ast->attributes.erase("\\lib_whitebox"); + AstNode *n = ast->attributes.at(ID::lib_whitebox); + ast->attributes[ID::whitebox] = n; + ast->attributes.erase(ID::lib_whitebox); } } - if (!blackbox_module && ast->attributes.count("\\blackbox")) { - AstNode *n = ast->attributes.at("\\blackbox"); + if (!blackbox_module && ast->attributes.count(ID::blackbox)) { + AstNode *n = ast->attributes.at(ID::blackbox); if (n->type != AST_CONSTANT) log_file_error(ast->filename, ast->location.first_line, "Got blackbox attribute with non-constant value!\n"); blackbox_module = n->asBool(); } - if (blackbox_module && ast->attributes.count("\\whitebox")) { - AstNode *n = ast->attributes.at("\\whitebox"); + if (blackbox_module && ast->attributes.count(ID::whitebox)) { + AstNode *n = ast->attributes.at(ID::whitebox); if (n->type != AST_CONSTANT) log_file_error(ast->filename, ast->location.first_line, "Got whitebox attribute with non-constant value!\n"); blackbox_module = !n->asBool(); } - if (ast->attributes.count("\\noblackbox")) { + if (ast->attributes.count(ID::noblackbox)) { if (blackbox_module) { - AstNode *n = ast->attributes.at("\\noblackbox"); + AstNode *n = ast->attributes.at(ID::noblackbox); if (n->type != AST_CONSTANT) log_file_error(ast->filename, ast->location.first_line, "Got noblackbox attribute with non-constant value!\n"); blackbox_module = !n->asBool(); } - delete ast->attributes.at("\\noblackbox"); - ast->attributes.erase("\\noblackbox"); + delete ast->attributes.at(ID::noblackbox); + ast->attributes.erase(ID::noblackbox); } if (blackbox_module) { - if (ast->attributes.count("\\whitebox")) { - delete ast->attributes.at("\\whitebox"); - ast->attributes.erase("\\whitebox"); + if (ast->attributes.count(ID::whitebox)) { + delete ast->attributes.at(ID::whitebox); + ast->attributes.erase(ID::whitebox); } - if (ast->attributes.count("\\lib_whitebox")) { - delete ast->attributes.at("\\lib_whitebox"); - ast->attributes.erase("\\lib_whitebox"); + if (ast->attributes.count(ID::lib_whitebox)) { + delete ast->attributes.at(ID::lib_whitebox); + ast->attributes.erase(ID::lib_whitebox); } std::vector<AstNode*> new_children; @@ -1082,8 +1082,8 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ast->children.swap(new_children); - if (ast->attributes.count("\\blackbox") == 0) { - ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false); + if (ast->attributes.count(ID::blackbox) == 0) { + ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false); } } @@ -1124,7 +1124,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast } if (ast->type == AST_INTERFACE) - current_module->set_bool_attribute("\\is_interface"); + current_module->set_bool_attribute(ID::is_interface); current_module->ast = ast_before_simplify; current_module->nolatches = flag_nolatches; current_module->nomeminit = flag_nomeminit; @@ -1179,12 +1179,13 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump for (auto n : design->verilog_globals) (*it)->children.push_back(n->clone()); - for (auto n : design->verilog_packages){ - for (auto o : n->children) { + // append nodes from previous packages using package-qualified names + for (auto &n : design->verilog_packages) { + for (auto &o : n->children) { AstNode *cloned_node = o->clone(); - log("cloned node %s\n", type2str(cloned_node->type).c_str()); - if (cloned_node->type == AST_ENUM){ - for (auto e : cloned_node->children){ + // log("cloned node %s\n", type2str(cloned_node->type).c_str()); + if (cloned_node->type == AST_ENUM) { + for (auto &e : cloned_node->children) { log_assert(e->type == AST_ENUM_ITEM); e->str = n->str + std::string("::") + e->str.substr(1); } @@ -1211,7 +1212,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump continue; } else { log("Replacing existing%s module `%s' at %s:%d.%d-%d.%d.\n", - existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", + existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column); design->remove(existing_mod); } @@ -1220,6 +1221,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump design->add(process_module(*it, defer)); } else if ((*it)->type == AST_PACKAGE) { + // process enum/other declarations + (*it)->simplify(true, false, false, 1, -1, false, false); design->verilog_packages.push_back((*it)->clone()); } else { @@ -1281,9 +1284,9 @@ AstNode * AST::find_modport(AstNode *intf, std::string name) // Iterate over all wires in an interface and add them as wires in the AST module: void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport) { - for (auto &wire_it : intfmodule->wires_){ - AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true))); - std::string origname = log_id(wire_it.first); + for (auto w : intfmodule->wires()){ + AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true))); + std::string origname = log_id(w->name); std::string newname = intfname + "." + origname; wire->str = newname; if (modport != NULL) { @@ -1317,7 +1320,7 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule // When an interface instance is found in a module, the whole RTLIL for the module will be rederived again // from AST. The interface members are copied into the AST module with the prefix of the interface. -void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces) +void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module*> &local_interfaces) { loadconfig(); @@ -1326,9 +1329,9 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT for (auto &intf : local_interfaces) { std::string intfname = intf.first.str(); RTLIL::Module *intfmodule = intf.second; - for (auto &wire_it : intfmodule->wires_){ - AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true))); - std::string newname = log_id(wire_it.first); + for (auto w : intfmodule->wires()){ + AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true))); + std::string newname = log_id(w->name); newname = intfname + "." + newname; wire->str = newname; new_ast->children.push_back(wire); @@ -1352,7 +1355,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT std::pair<std::string,std::string> res = split_modport_from_type(ch->str); std::string interface_type = res.first; std::string interface_modport = res.second; // Is "", if no modport - if (design->modules_.count(interface_type) > 0) { + if (design->module(interface_type) != nullptr) { // Add a cell to the module corresponding to the interface port such that // it can further propagated down if needed: AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE); @@ -1362,7 +1365,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT new_ast->children.push_back(cell_for_intf); // Get all members of this non-overridden dummy interface instance: - RTLIL::Module *intfmodule = design->modules_[interface_type]; // All interfaces should at this point in time (assuming + RTLIL::Module *intfmodule = design->module(interface_type); // All interfaces should at this point in time (assuming // reprocess_module is called from the hierarchy pass) be // present in design->modules_ AstModule *ast_module_of_interface = (AstModule*)intfmodule; @@ -1382,12 +1385,12 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT std::string original_name = this->name.str(); std::string changed_name = original_name + "_before_replacing_local_interfaces"; design->rename(this, changed_name); - this->set_bool_attribute("\\to_delete"); + this->set_bool_attribute(ID::to_delete); // Check if the module was the top module. If it was, we need to remove the top attribute and put it on the // new module. - if (this->get_bool_attribute("\\initial_top")) { - this->attributes.erase("\\initial_top"); + if (this->get_bool_attribute(ID::initial_top)) { + this->attributes.erase(ID::initial_top); is_top = true; } @@ -1397,15 +1400,15 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT design->add(newmod); RTLIL::Module* mod = design->module(original_name); if (is_top) - mod->set_bool_attribute("\\top"); + mod->set_bool_attribute(ID::top); // Set the attribute "interfaces_replaced_in_module" so that it does not happen again. - mod->set_bool_attribute("\\interfaces_replaced_in_module"); + mod->set_bool_attribute(ID::interfaces_replaced_in_module); } // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces // This method is used to explode the interface when the interface is a port of the module (not instantiated inside) -RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool /*mayfail*/) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/) { AstNode *new_ast = NULL; std::string modname = derive_common(design, parameters, &new_ast); @@ -1457,13 +1460,20 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R // Now that the interfaces have been exploded, we can delete the dummy port related to every interface. for(auto &intf : interfaces) { - if(mod->wires_.count(intf.first)) { - mod->wires_.erase(intf.first); + if(mod->wire(intf.first) != nullptr) { + // Normally, removing wires would be batched together as it's an + // expensive operation, however, in this case doing so would mean + // that a cell with the same name cannot be created (below)... + // Since we won't expect many interfaces to exist in a module, + // we can let this slide... + pool<RTLIL::Wire*> to_remove; + to_remove.insert(mod->wire(intf.first)); + mod->remove(to_remove); mod->fixup_ports(); - // We copy the cell of the interface to the sub-module such that it can further be found if it is propagated - // down to sub-sub-modules etc. - RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name); - new_subcell->set_bool_attribute("\\is_interface"); + // We copy the cell of the interface to the sub-module such that it + // can further be found if it is propagated down to sub-sub-modules etc. + RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name); + new_subcell->set_bool_attribute(ID::is_interface); } else { log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str()); @@ -1472,7 +1482,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R // If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module': if (interfaces.size() > 0) { - mod->set_bool_attribute("\\interfaces_replaced_in_module"); + mod->set_bool_attribute(ID::interfaces_replaced_in_module); } } else { @@ -1484,9 +1494,9 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R } // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces -RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool /*mayfail*/) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool /*mayfail*/) { - bool quiet = lib || attributes.count(ID(blackbox)) || attributes.count(ID(whitebox)); + bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox); AstNode *new_ast = NULL; std::string modname = derive_common(design, parameters, &new_ast, quiet); @@ -1504,7 +1514,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R } // create a new parametric module (when needed) and return the name of the generated module -std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet) +std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet) { std::string stripped_name = name.str(); @@ -1518,18 +1528,18 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString if (child->type != AST_PARAMETER) continue; para_counter++; - std::string para_id = child->str; - if (parameters.count(para_id) > 0) { + auto it = parameters.find(child->str); + if (it != parameters.end()) { if (!quiet) - log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str]))); - para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); + log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); + para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second)); continue; } - para_id = stringf("$%d", para_counter); - if (parameters.count(para_id) > 0) { + it = parameters.find(stringf("$%d", para_counter)); + if (it != parameters.end()) { if (!quiet) - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); - para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); + log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); + para_info += stringf("%s=%s", child->str.c_str(), log_signal(it->second)); continue; } } @@ -1549,46 +1559,52 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str()); loadconfig(); + pool<IdString> rewritten; + rewritten.reserve(GetSize(parameters)); + AstNode *new_ast = ast->clone(); para_counter = 0; for (auto child : new_ast->children) { if (child->type != AST_PARAMETER) continue; para_counter++; - std::string para_id = child->str; - if (parameters.count(para_id) > 0) { + auto it = parameters.find(child->str); + if (it != parameters.end()) { if (!quiet) - log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str]))); + log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); goto rewrite_parameter; } - para_id = stringf("$%d", para_counter); - if (parameters.count(para_id) > 0) { + it = parameters.find(stringf("$%d", para_counter)); + if (it != parameters.end()) { if (!quiet) - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); + log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); goto rewrite_parameter; } continue; rewrite_parameter: delete child->children.at(0); - if ((parameters[para_id].flags & RTLIL::CONST_FLAG_REAL) != 0) { + if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) { child->children[0] = new AstNode(AST_REALVALUE); - child->children[0]->realvalue = std::stod(parameters[para_id].decode_string()); - } else if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0) - child->children[0] = AstNode::mkconst_str(parameters[para_id].decode_string()); + child->children[0]->realvalue = std::stod(it->second.decode_string()); + } else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0) + child->children[0] = AstNode::mkconst_str(it->second.decode_string()); else - child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0); - parameters.erase(para_id); + child->children[0] = AstNode::mkconst_bits(it->second.bits, (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); + rewritten.insert(it->first); } - for (auto param : parameters) { - AstNode *defparam = new AstNode(AST_DEFPARAM, new AstNode(AST_IDENTIFIER)); - defparam->children[0]->str = param.first.str(); - if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0) - defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string())); - else - defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); - new_ast->children.push_back(defparam); - } + if (GetSize(rewritten) < GetSize(parameters)) + for (const auto ¶m : parameters) { + if (rewritten.count(param.first)) + continue; + AstNode *defparam = new AstNode(AST_DEFPARAM, new AstNode(AST_IDENTIFIER)); + defparam->children[0]->str = param.first.str(); + if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0) + defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string())); + else + defparam->children.push_back(AstNode::mkconst_bits(param.second.bits, (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); + new_ast->children.push_back(defparam); + } (*new_ast_out) = new_ast; return modname; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index e27ab10c2..3dd40238f 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -312,10 +312,10 @@ namespace AST AstNode *ast; bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire; ~AstModule() YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE; - std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet = false); - void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) YS_OVERRIDE; + std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet = false); + void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) YS_OVERRIDE; RTLIL::Module *clone() const YS_OVERRIDE; void loadconfig() const; }; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 54d8a11fa..c0539252c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -41,16 +41,14 @@ using namespace AST; using namespace AST_INTERNAL; // helper function for creating RTLIL code for unary operations -static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) +static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) { - std::stringstream sstr; - sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); - - RTLIL::Cell *cell = current_module->addCell(sstr.str(), type); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++); + RTLIL::Cell *cell = current_module->addCell(name, type); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); if (gen_attributes) for (auto &attr : that->attributes) { @@ -59,12 +57,12 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size()); - cell->setPort("\\A", arg); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size()); + cell->setPort(ID::A, arg); - cell->parameters["\\Y_WIDTH"] = result_width; - cell->setPort("\\Y", wire); + cell->parameters[ID::Y_WIDTH] = result_width; + cell->setPort(ID::Y, wire); return wire; } @@ -76,14 +74,12 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s return; } - std::stringstream sstr; - sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); - - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos"); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++); + RTLIL::Cell *cell = current_module->addCell(name, ID($pos)); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); if (that != NULL) for (auto &attr : that->attributes) { @@ -92,26 +88,24 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); - cell->setPort("\\A", sig); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size()); + cell->setPort(ID::A, sig); - cell->parameters["\\Y_WIDTH"] = width; - cell->setPort("\\Y", wire); + cell->parameters[ID::Y_WIDTH] = width; + cell->setPort(ID::Y, wire); sig = wire; } // helper function for creating RTLIL code for binary operations -static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) +static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { - std::stringstream sstr; - sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); - - RTLIL::Cell *cell = current_module->addCell(sstr.str(), type); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++); + RTLIL::Cell *cell = current_module->addCell(name, type); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) @@ -119,17 +113,17 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed); - cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed); + cell->parameters[ID::B_SIGNED] = RTLIL::Const(that->children[1]->is_signed); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size()); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size()); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size()); + cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size()); - cell->setPort("\\A", left); - cell->setPort("\\B", right); + cell->setPort(ID::A, left); + cell->setPort(ID::B, right); - cell->parameters["\\Y_WIDTH"] = result_width; - cell->setPort("\\Y", wire); + cell->parameters[ID::Y_WIDTH] = result_width; + cell->setPort(ID::Y, wire); return wire; } @@ -141,11 +135,11 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const std::stringstream sstr; sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux"); - cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux)); + cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); - wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); + wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) @@ -153,12 +147,12 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->parameters["\\WIDTH"] = RTLIL::Const(left.size()); + cell->parameters[ID::WIDTH] = RTLIL::Const(left.size()); - cell->setPort("\\A", right); - cell->setPort("\\B", left); - cell->setPort("\\S", cond); - cell->setPort("\\Y", wire); + cell->setPort(ID::A, right); + cell->setPort(ID::B, left); + cell->setPort(ID::S, cond); + cell->setPort(ID::Y, wire); return wire; } @@ -199,7 +193,7 @@ struct AST_INTERNAL::ProcessGenerator { // generate process and simple root case proc = new RTLIL::Process; - proc->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); + proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++); for (auto &attr : always->attributes) { if (attr.second->type != AST_CONSTANT) @@ -221,7 +215,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto child : always->children) { if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && - child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) { + child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) { found_global_syncs = true; } if (child->type == AST_EDGE) { @@ -245,7 +239,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto child : always->children) if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) { if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast && - child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) + child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) continue; found_clocked_sync = true; if (found_global_syncs || found_anyedge_syncs) @@ -267,7 +261,7 @@ struct AST_INTERNAL::ProcessGenerator } // create initial assignments for the temporary signals - if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) { + if ((flag_nolatches || always->get_bool_attribute(ID::nolatches) || current_module->get_bool_attribute(ID::nolatches)) && !found_clocked_sync) { subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from))); } else { addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from); @@ -335,7 +329,7 @@ struct AST_INTERNAL::ProcessGenerator } while (current_module->wires_.count(wire_name) > 0); RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width); - wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column); chunk.wire = wire; chunk.offset = 0; @@ -420,7 +414,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto &lvalue_c : lvalue.chunks()) { RTLIL::SigSpec lhs = lvalue_c; RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width); - if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync")) + if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync)) rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size()); remove_unwanted_lvalue_bits(lhs, rhs); actions.push_back(RTLIL::SigSig(lhs, rhs)); @@ -470,7 +464,7 @@ struct AST_INTERNAL::ProcessGenerator case AST_CASE: { RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; - sw->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column); + sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column); sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap()); current_case->switches.push_back(sw); @@ -504,7 +498,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::CaseRule *backup_case = current_case; current_case = new RTLIL::CaseRule; - current_case->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column); + current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column); last_generated_case = current_case; addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue); for (auto node : child->children) { @@ -525,7 +519,7 @@ struct AST_INTERNAL::ProcessGenerator subst_rvalue_map.restore(); } - if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) { + if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) { #if 0 // this is a valid transformation, but as optimization it is premature. // better: add a default case that assigns 'x' to everything, and let later @@ -842,7 +836,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this // cases this variable is used to hold the type of the cell that should // be instantiated for this type of AST node. - std::string type_name; + IdString type_name; current_filename = filename; @@ -873,19 +867,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // This is used by the hierarchy pass to know when it can replace interface connection with the individual // signals. RTLIL::Wire *wire = current_module->addWire(str, 1); - wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->start_offset = 0; wire->port_id = port_id; wire->port_input = true; wire->port_output = true; - wire->set_bool_attribute("\\is_interface"); + wire->set_bool_attribute(ID::is_interface); if (children.size() > 0) { for(size_t i=0; i<children.size();i++) { if(children[i]->type == AST_INTERFACEPORTTYPE) { std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str); - wire->attributes["\\interface_type"] = res.first; + wire->attributes[ID::interface_type] = res.first; if (res.second != "") - wire->attributes["\\interface_modport"] = res.second; + wire->attributes[ID::interface_modport] = res.second; break; } } @@ -910,8 +904,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Wire *wire = current_module->addWire(str, GetSize(val)); current_module->connect(wire, val); - wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); - wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1; + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1; for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) @@ -932,7 +926,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); - wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->start_offset = range_right; wire->port_id = port_id; wire->port_input = is_input; @@ -945,8 +939,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->attributes[attr.first] = attr.second->asAttrConst(); } - if (is_wand) wire->set_bool_attribute("\\wand"); - if (is_wor) wire->set_bool_attribute("\\wor"); + if (is_wand) wire->set_bool_attribute(ID::wand); + if (is_wor) wire->set_bool_attribute(ID::wor); } break; @@ -963,7 +957,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str()); RTLIL::Memory *memory = new RTLIL::Memory; - memory->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); memory->name = str; memory->width = children[0]->range_left - children[0]->range_right + 1; if (children[1]->range_right < children[1]->range_left) { @@ -1018,7 +1012,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) { RTLIL::Wire *wire = current_module->addWire(str); - wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->name = str; if (flag_autowire) log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str()); @@ -1033,7 +1027,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) { RTLIL::Wire *current_wire = current_module->wire(str); - if (current_wire->get_bool_attribute("\\is_interface")) + if (current_wire->get_bool_attribute(ID::is_interface)) is_interface = true; // Ignore } @@ -1052,16 +1046,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // This makes it possible for the hierarchy pass to see what are interface connections and then replace them // with the individual signals: if (is_interface) { - RTLIL::Wire *dummy_wire; - std::string dummy_wire_name = "$dummywireforinterface" + str; - if (current_module->wires_.count(dummy_wire_name)) - dummy_wire = current_module->wires_[dummy_wire_name]; - else { + IdString dummy_wire_name = stringf("$dummywireforinterface%s", str.c_str()); + RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name); + if (!dummy_wire) { dummy_wire = current_module->addWire(dummy_wire_name); - dummy_wire->set_bool_attribute("\\is_interface"); + dummy_wire->set_bool_attribute(ID::is_interface); } - RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire); - return tmp; + return dummy_wire; } wire = current_module->wires_[str]; @@ -1097,7 +1088,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } if (GetSize(shift_val) >= 32) fake_ast->children[1]->is_signed = true; - RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val); + RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val); delete left_at_zero_ast; delete right_at_zero_ast; delete fake_ast; @@ -1181,9 +1172,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for unary operations: $not, $pos, $neg - if (0) { case AST_BIT_NOT: type_name = "$not"; } - if (0) { case AST_POS: type_name = "$pos"; } - if (0) { case AST_NEG: type_name = "$neg"; } + if (0) { case AST_BIT_NOT: type_name = ID($not); } + if (0) { case AST_POS: type_name = ID($pos); } + if (0) { case AST_NEG: type_name = ID($neg); } { RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint); is_signed = children[0]->is_signed; @@ -1196,10 +1187,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $and, $or, $xor, $xnor - if (0) { case AST_BIT_AND: type_name = "$and"; } - if (0) { case AST_BIT_OR: type_name = "$or"; } - if (0) { case AST_BIT_XOR: type_name = "$xor"; } - if (0) { case AST_BIT_XNOR: type_name = "$xnor"; } + if (0) { case AST_BIT_AND: type_name = ID($and); } + if (0) { case AST_BIT_OR: type_name = ID($or); } + if (0) { case AST_BIT_XOR: type_name = ID($xor); } + if (0) { case AST_BIT_XNOR: type_name = ID($xnor); } { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); @@ -1213,10 +1204,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor - if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; } - if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; } - if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; } - if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; } + if (0) { case AST_REDUCE_AND: type_name = ID($reduce_and); } + if (0) { case AST_REDUCE_OR: type_name = ID($reduce_or); } + if (0) { case AST_REDUCE_XOR: type_name = ID($reduce_xor); } + if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); } { RTLIL::SigSpec arg = children[0]->genRTLIL(); RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg); @@ -1225,7 +1216,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // generate cells for unary operations: $reduce_bool // (this is actually just an $reduce_or, but for clarity a different cell type is used) - if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; } + if (0) { case AST_REDUCE_BOOL: type_name = ID($reduce_bool); } { RTLIL::SigSpec arg = children[0]->genRTLIL(); RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg; @@ -1233,10 +1224,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $shl, $shr, $sshl, $sshr - if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; } - if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; } - if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; } - if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; } + if (0) { case AST_SHIFT_LEFT: type_name = ID($shl); } + if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); } + if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); } + if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); } { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); @@ -1260,19 +1251,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = width_hint > 0 ? width_hint : left.size(); is_signed = children[0]->is_signed; if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed) - return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right); - return binop2rtlil(this, "$pow", width, left, right); + return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right); + return binop2rtlil(this, ID($pow), width, left, right); } // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt - if (0) { case AST_LT: type_name = "$lt"; } - if (0) { case AST_LE: type_name = "$le"; } - if (0) { case AST_EQ: type_name = "$eq"; } - if (0) { case AST_NE: type_name = "$ne"; } - if (0) { case AST_EQX: type_name = "$eqx"; } - if (0) { case AST_NEX: type_name = "$nex"; } - if (0) { case AST_GE: type_name = "$ge"; } - if (0) { case AST_GT: type_name = "$gt"; } + if (0) { case AST_LT: type_name = ID($lt); } + if (0) { case AST_LE: type_name = ID($le); } + if (0) { case AST_EQ: type_name = ID($eq); } + if (0) { case AST_NE: type_name = ID($ne); } + if (0) { case AST_EQX: type_name = ID($eqx); } + if (0) { case AST_NEX: type_name = ID($nex); } + if (0) { case AST_GE: type_name = ID($ge); } + if (0) { case AST_GT: type_name = ID($gt); } { int width = max(width_hint, 1); width_hint = -1, sign_hint = true; @@ -1285,11 +1276,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $add, $sub, $mul, $div, $mod - if (0) { case AST_ADD: type_name = "$add"; } - if (0) { case AST_SUB: type_name = "$sub"; } - if (0) { case AST_MUL: type_name = "$mul"; } - if (0) { case AST_DIV: type_name = "$div"; } - if (0) { case AST_MOD: type_name = "$mod"; } + if (0) { case AST_ADD: type_name = ID($add); } + if (0) { case AST_SUB: type_name = ID($sub); } + if (0) { case AST_MUL: type_name = ID($mul); } + if (0) { case AST_DIV: type_name = ID($div); } + if (0) { case AST_MOD: type_name = ID($mod); } { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); @@ -1315,8 +1306,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $logic_and, $logic_or - if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; } - if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; } + if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); } + if (0) { case AST_LOGIC_OR: type_name = ID($logic_or); } { RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL(); @@ -1327,7 +1318,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_LOGIC_NOT: { RTLIL::SigSpec arg = children[0]->genRTLIL(); - return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg); + return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg); } // generate multiplexer for ternary operator (aka ?:-operator) @@ -1353,7 +1344,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); if (cond.size() > 1) - cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false); + cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false); int width = max(val1.size(), val2.size()); is_signed = children[1]->is_signed && children[2]->is_signed; @@ -1374,11 +1365,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) std::stringstream sstr; sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd"); - cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd)); + cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width); - wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line); + wire->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line); int mem_width, mem_size, addr_bits; is_signed = id2ast->is_signed; @@ -1386,18 +1377,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec addr_sig = children[0]->genRTLIL(); - cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort("\\ADDR", addr_sig); - cell->setPort("\\DATA", RTLIL::SigSpec(wire)); + cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(ID::ADDR, addr_sig); + cell->setPort(ID::DATA, RTLIL::SigSpec(wire)); - cell->parameters["\\MEMID"] = RTLIL::Const(str); - cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); - cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width); + cell->parameters[ID::MEMID] = RTLIL::Const(str); + cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig)); + cell->parameters[ID::WIDTH] = RTLIL::Const(wire->width); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); - cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0); + cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0); if (!sign_hint) is_signed = false; @@ -1412,8 +1403,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) std::stringstream sstr; sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit"); - cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit)); + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); int mem_width, mem_size, addr_bits; id2ast->meminfo(mem_width, mem_size, addr_bits); @@ -1423,26 +1414,26 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (children[2]->type != AST_CONSTANT) log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n"); num_words = int(children[2]->asInt(false)); - cell->parameters["\\WORDS"] = RTLIL::Const(num_words); + cell->parameters[ID::WORDS] = RTLIL::Const(num_words); } SigSpec addr_sig = children[0]->genRTLIL(); - cell->setPort("\\ADDR", addr_sig); - cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words)); + cell->setPort(ID::ADDR, addr_sig); + cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words)); - cell->parameters["\\MEMID"] = RTLIL::Const(str); - cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); - cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width); + cell->parameters[ID::MEMID] = RTLIL::Const(str); + cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig)); + cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width); if (type == AST_MEMWR) { - cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort("\\EN", children[2]->genRTLIL()); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); + cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort(ID::EN, children[2]->genRTLIL()); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0); } - cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1); + cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1); } break; @@ -1453,12 +1444,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_FAIR: case AST_COVER: { - const char *celltype = nullptr; - if (type == AST_ASSERT) celltype = "$assert"; - if (type == AST_ASSUME) celltype = "$assume"; - if (type == AST_LIVE) celltype = "$live"; - if (type == AST_FAIR) celltype = "$fair"; - if (type == AST_COVER) celltype = "$cover"; + IdString celltype; + if (type == AST_ASSERT) celltype = ID($assert); + if (type == AST_ASSUME) celltype = ID($assume); + if (type == AST_LIVE) celltype = ID($live); + if (type == AST_FAIR) celltype = ID($fair); + if (type == AST_COVER) celltype = ID($cover); log_assert(children.size() == 2); @@ -1471,16 +1462,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) en = current_module->ReduceBool(NEW_ID, en); IdString cellname; - if (str.empty()) { - std::stringstream sstr; - sstr << celltype << "$" << filename << ":" << location.first_line << "$" << (autoidx++); - cellname = sstr.str(); - } else { + if (str.empty()) + cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++); + else cellname = str; - } RTLIL::Cell *cell = current_module->addCell(cellname, celltype); - cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) @@ -1488,8 +1476,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->attributes[attr.first] = attr.second->asAttrConst(); } - cell->setPort("\\A", check); - cell->setPort("\\EN", en); + cell->setPort(ID::A, check); + cell->setPort(ID::EN, en); } break; @@ -1525,9 +1513,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str()); RTLIL::Cell *cell = current_module->addCell(str, ""); - cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass - cell->set_bool_attribute("\\module_not_derived"); + cell->set_bool_attribute(ID::module_not_derived); for (auto it = children.begin(); it != children.end(); it++) { AstNode *child = *it; @@ -1575,29 +1563,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - if (cell->type == "$specify2") { - int src_width = GetSize(cell->getPort("\\SRC")); - int dst_width = GetSize(cell->getPort("\\DST")); - bool full = cell->getParam("\\FULL").as_bool(); + if (cell->type == ID($specify2)) { + int src_width = GetSize(cell->getPort(ID::SRC)); + int dst_width = GetSize(cell->getPort(ID::DST)); + bool full = cell->getParam(ID::FULL).as_bool(); if (!full && src_width != dst_width) log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n"); - cell->setParam("\\SRC_WIDTH", Const(src_width)); - cell->setParam("\\DST_WIDTH", Const(dst_width)); + cell->setParam(ID::SRC_WIDTH, Const(src_width)); + cell->setParam(ID::DST_WIDTH, Const(dst_width)); } - else if (cell->type == "$specify3") { - int dat_width = GetSize(cell->getPort("\\DAT")); - int dst_width = GetSize(cell->getPort("\\DST")); + else if (cell->type == ID($specify3)) { + int dat_width = GetSize(cell->getPort(ID::DAT)); + int dst_width = GetSize(cell->getPort(ID::DST)); if (dat_width != dst_width) log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n"); - int src_width = GetSize(cell->getPort("\\SRC")); - cell->setParam("\\SRC_WIDTH", Const(src_width)); - cell->setParam("\\DST_WIDTH", Const(dst_width)); + int src_width = GetSize(cell->getPort(ID::SRC)); + cell->setParam(ID::SRC_WIDTH, Const(src_width)); + cell->setParam(ID::DST_WIDTH, Const(dst_width)); } - else if (cell->type == "$specrule") { - int src_width = GetSize(cell->getPort("\\SRC")); - int dst_width = GetSize(cell->getPort("\\DST")); - cell->setParam("\\SRC_WIDTH", Const(src_width)); - cell->setParam("\\DST_WIDTH", Const(dst_width)); + else if (cell->type == ID($specrule)) { + int src_width = GetSize(cell->getPort(ID::SRC)); + int dst_width = GetSize(cell->getPort(ID::DST)); + cell->setParam(ID::SRC_WIDTH, Const(src_width)); + cell->setParam(ID::DST_WIDTH, Const(dst_width)); } } break; @@ -1668,19 +1656,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); Cell *cell = current_module->addCell(myid, str.substr(1)); - cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); - cell->parameters["\\WIDTH"] = width; + cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + cell->parameters[ID::WIDTH] = width; - if (attributes.count("\\reg")) { - auto &attr = attributes.at("\\reg"); + if (attributes.count(ID::reg)) { + auto &attr = attributes.at(ID::reg); if (attr->type != AST_CONSTANT) log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n"); - cell->attributes["\\reg"] = attr->asAttrConst(); + cell->attributes[ID::reg] = attr->asAttrConst(); } Wire *wire = current_module->addWire(myid + "_wire", width); - wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); - cell->setPort("\\Y", wire); + wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); + cell->setPort(ID::Y, wire); is_signed = sign_hint; return SigSpec(wire); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 04c02d893..b87af0f8c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -172,7 +172,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, deep_recursion_warning = true; while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { } - if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg")) + if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg)) { dict<AstNode*, pool<std::string>> mem2reg_places; dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags; @@ -187,10 +187,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, bool this_nomeminit = flag_nomeminit; log_assert((memflags & ~0x00ffff00) == 0); - if (mem->get_bool_attribute("\\nomem2reg")) + if (mem->get_bool_attribute(ID::nomem2reg)) continue; - if (mem->get_bool_attribute("\\nomeminit") || get_bool_attribute("\\nomeminit")) + if (mem->get_bool_attribute(ID::nomeminit) || get_bool_attribute(ID::nomeminit)) this_nomeminit = true; if (memflags & AstNode::MEM2REG_FL_FORCED) @@ -248,7 +248,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, reg->is_reg = true; reg->is_signed = node->is_signed; for (auto &it : node->attributes) - if (it.first != ID(mem2reg)) + if (it.first != ID::mem2reg) reg->attributes.emplace(it.first, it.second->clone()); reg->filename = node->filename; reg->location = node->location; @@ -345,9 +345,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { for (auto c : node->children[0]->children) { if (!c->is_simple_const_expr()) { - if (attributes.count("\\dynports")) - delete attributes.at("\\dynports"); - attributes["\\dynports"] = AstNode::mkconst_int(1, true); + if (attributes.count(ID::dynports)) + delete attributes.at(ID::dynports); + attributes[ID::dynports] = AstNode::mkconst_int(1, true); } } } @@ -432,7 +432,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) did_something = true; if (node->type == AST_ENUM) { - for (auto enode : node->children){ + for (auto enode YS_ATTRIBUTE(unused) : node->children){ log_assert(enode->type==AST_ENUM_ITEM); while (node->simplify(true, false, false, 1, -1, false, in_param)) did_something = true; @@ -1219,7 +1219,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true))); wire->str = wire_id; if (current_block) - wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); current_ast_mod->children.push_back(wire); while (wire->simplify(true, false, false, 1, -1, false, false)) { } @@ -1727,13 +1727,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } did_something = true; newNode = new AstNode(AST_CASE, shift_expr); - for (int i = 0; i <= source_width-result_width; i++) { + for (int i = 0; i < source_width; i++) { int start_bit = children[0]->id2ast->range_right + i; AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true)); AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); + int end_bit = std::min(start_bit+result_width,source_width) - 1; lvalue->children.push_back(new AstNode(AST_RANGE, - mkconst_int(start_bit+result_width-1, true), mkconst_int(start_bit, true))); + mkconst_int(end_bit, true), mkconst_int(start_bit, true))); cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone()))); newNode->children.push_back(cond); } @@ -1811,6 +1812,7 @@ skip_dynamic_range_lvalue_expansion:; newNode->children.push_back(assign_en); AstNode *assertnode = new AstNode(type); + assertnode->location = location; assertnode->str = str; assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); @@ -1855,7 +1857,7 @@ skip_dynamic_range_lvalue_expansion:; wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); current_ast_mod->children.push_back(wire_tmp); current_scope[wire_tmp->str] = wire_tmp; - wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false); while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { } wire_tmp->is_logic = true; @@ -1897,6 +1899,9 @@ skip_dynamic_range_lvalue_expansion:; bool mem_signed = children[0]->id2ast->is_signed; children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits); + newNode = new AstNode(AST_BLOCK); + AstNode *defNode = new AstNode(AST_BLOCK); + int data_range_left = children[0]->id2ast->children[0]->range_left; int data_range_right = children[0]->id2ast->children[0]->range_right; int mem_data_range_offset = std::min(data_range_left, data_range_right); @@ -1906,31 +1911,6 @@ skip_dynamic_range_lvalue_expansion:; children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint); addr_bits = std::max(addr_bits, addr_width_hint); - AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); - wire_addr->str = id_addr; - wire_addr->was_checked = true; - current_ast_mod->children.push_back(wire_addr); - current_scope[wire_addr->str] = wire_addr; - while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } - - AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); - wire_data->str = id_data; - wire_data->was_checked = true; - wire_data->is_signed = mem_signed; - current_ast_mod->children.push_back(wire_data); - current_scope[wire_data->str] = wire_data; - while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } - - AstNode *wire_en = nullptr; - if (current_always->type != AST_INITIAL) { - wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); - wire_en->str = id_en; - wire_en->was_checked = true; - current_ast_mod->children.push_back(wire_en); - current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } - } - std::vector<RTLIL::State> x_bits_addr, x_bits_data, set_bits_en; for (int i = 0; i < addr_bits; i++) x_bits_addr.push_back(RTLIL::State::Sx); @@ -1939,32 +1919,79 @@ skip_dynamic_range_lvalue_expansion:; for (int i = 0; i < mem_width; i++) set_bits_en.push_back(RTLIL::State::S1); - AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); - assign_addr->children[0]->str = id_addr; - assign_addr->children[0]->was_checked = true; + AstNode *node_addr = nullptr; + if (children[0]->children[0]->children[0]->isConst()) { + node_addr = children[0]->children[0]->children[0]->clone(); + } else { + AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); + wire_addr->str = id_addr; + wire_addr->was_checked = true; + current_ast_mod->children.push_back(wire_addr); + current_scope[wire_addr->str] = wire_addr; + while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } - AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); - assign_data->children[0]->str = id_data; - assign_data->children[0]->was_checked = true; + AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); + assign_addr->children[0]->str = id_addr; + assign_addr->children[0]->was_checked = true; + defNode->children.push_back(assign_addr); - AstNode *assign_en = nullptr; - if (current_always->type != AST_INITIAL) { - assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); + assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone()); + assign_addr->children[0]->str = id_addr; + assign_addr->children[0]->was_checked = true; + newNode->children.push_back(assign_addr); + + node_addr = new AstNode(AST_IDENTIFIER); + node_addr->str = id_addr; + } + + AstNode *node_data = nullptr; + if (children[0]->children.size() == 1 && children[1]->isConst()) { + node_data = children[1]->clone(); + } else { + AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); + wire_data->str = id_data; + wire_data->was_checked = true; + wire_data->is_signed = mem_signed; + current_ast_mod->children.push_back(wire_data); + current_scope[wire_data->str] = wire_data; + while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } + + AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); + assign_data->children[0]->str = id_data; + assign_data->children[0]->was_checked = true; + defNode->children.push_back(assign_data); + + node_data = new AstNode(AST_IDENTIFIER); + node_data->str = id_data; + } + + AstNode *node_en = nullptr; + if (current_always->type == AST_INITIAL) { + node_en = AstNode::mkconst_int(1, false); + } else { + AstNode *wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); + wire_en->str = id_en; + wire_en->was_checked = true; + current_ast_mod->children.push_back(wire_en); + current_scope[wire_en->str] = wire_en; + while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } + + AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); assign_en->children[0]->str = id_en; assign_en->children[0]->was_checked = true; - } + defNode->children.push_back(assign_en); - AstNode *default_signals = new AstNode(AST_BLOCK); - default_signals->children.push_back(assign_addr); - default_signals->children.push_back(assign_data); - if (current_always->type != AST_INITIAL) - default_signals->children.push_back(assign_en); - current_top_block->children.insert(current_top_block->children.begin(), default_signals); + node_en = new AstNode(AST_IDENTIFIER); + node_en->str = id_en; + } - assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone()); - assign_addr->children[0]->str = id_addr; - assign_addr->children[0]->was_checked = true; + if (!defNode->children.empty()) + current_top_block->children.insert(current_top_block->children.begin(), defNode); + else + delete defNode; + AstNode *assign_data = nullptr; + AstNode *assign_en = nullptr; if (children[0]->children.size() == 2) { if (children[0]->children[1]->range_valid) @@ -2025,9 +2052,11 @@ skip_dynamic_range_lvalue_expansion:; } else { - assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone()); - assign_data->children[0]->str = id_data; - assign_data->children[0]->was_checked = true; + if (!(children[0]->children.size() == 1 && children[1]->isConst())) { + assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone()); + assign_data->children[0]->str = id_data; + assign_data->children[0]->was_checked = true; + } if (current_always->type != AST_INITIAL) { assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); @@ -2035,28 +2064,20 @@ skip_dynamic_range_lvalue_expansion:; assign_en->children[0]->was_checked = true; } } - - newNode = new AstNode(AST_BLOCK); - newNode->children.push_back(assign_addr); - newNode->children.push_back(assign_data); - if (current_always->type != AST_INITIAL) + if (assign_data) + newNode->children.push_back(assign_data); + if (assign_en) newNode->children.push_back(assign_en); - AstNode *wrnode = new AstNode(current_always->type == AST_INITIAL ? AST_MEMINIT : AST_MEMWR); - wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); - wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); - if (current_always->type != AST_INITIAL) - wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); - else - wrnode->children.push_back(AstNode::mkconst_int(1, false)); + AstNode *wrnode = new AstNode(current_always->type == AST_INITIAL ? AST_MEMINIT : AST_MEMWR, node_addr, node_data, node_en); wrnode->str = children[0]->str; wrnode->id2ast = children[0]->id2ast; - wrnode->children[0]->str = id_addr; - wrnode->children[1]->str = id_data; - if (current_always->type != AST_INITIAL) - wrnode->children[2]->str = id_en; current_ast_mod->children.push_back(wrnode); + if (newNode->children.empty()) { + delete newNode; + newNode = new AstNode(); + } goto apply_newNode; } @@ -2656,7 +2677,7 @@ skip_dynamic_range_lvalue_expansion:; wire->is_input = false; wire->is_output = false; wire->is_reg = true; - wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); if (child->type == AST_ENUM_ITEM) wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"]; @@ -3344,10 +3365,10 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg } // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' - if (type == AST_MEMORY && (get_bool_attribute("\\mem2reg") || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg)) + if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg)) mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED; - if (type == AST_MODULE && get_bool_attribute("\\mem2reg")) + if (type == AST_MODULE && get_bool_attribute(ID::mem2reg)) children_flags |= AstNode::MEM2REG_FL_ALL; dict<AstNode*, uint32_t> *proc_flags_p = NULL; @@ -3510,7 +3531,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_addr->str = id_addr; wire_addr->is_reg = true; wire_addr->was_checked = true; - wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_addr); while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } @@ -3519,7 +3540,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_data->is_reg = true; wire_data->was_checked = true; wire_data->is_signed = mem_signed; - wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_data); while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } @@ -3590,7 +3611,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_addr->is_reg = true; wire_addr->was_checked = true; if (block) - wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_addr); while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } @@ -3600,7 +3621,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, wire_data->was_checked = true; wire_data->is_signed = mem_signed; if (block) - wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); + wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_data); while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index cab210605..7cc157e49 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -176,7 +176,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (!strcmp(cmd, ".blackbox")) { - module->attributes["\\blackbox"] = RTLIL::Const(1); + module->attributes[ID::blackbox] = RTLIL::Const(1); continue; } @@ -215,17 +215,17 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool vector<Cell*> remove_cells; for (auto cell : module->cells()) - if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) { - module->connect(cell->getPort("\\Y"), cell->getPort("\\A")); + if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) { + module->connect(cell->getPort(ID::Y), cell->getPort(ID::A)); remove_cells.push_back(cell); } for (auto cell : remove_cells) module->remove(cell); - Wire *true_wire = module->wire("$true"); - Wire *false_wire = module->wire("$false"); - Wire *undef_wire = module->wire("$undef"); + Wire *true_wire = module->wire(ID($true)); + Wire *false_wire = module->wire(ID($false)); + Wire *undef_wire = module->wire(ID($undef)); if (true_wire != nullptr) module->rename(true_wire, stringf("$true$%d", ++blif_maxnum)); @@ -337,7 +337,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool } if (init != nullptr && (init[0] == '0' || init[0] == '1')) - blif_wire(q)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1); + blif_wire(q)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1); if (clock == nullptr) goto no_latch_clock; @@ -356,8 +356,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q)); } else { cell = module->addCell(NEW_ID, dff_name); - cell->setPort("\\D", blif_wire(d)); - cell->setPort("\\Q", blif_wire(q)); + cell->setPort(ID::D, blif_wire(d)); + cell->setPort(ID::Q, blif_wire(q)); } } @@ -476,7 +476,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool finished_parsing_constval: if (state == RTLIL::State::Sa) state = RTLIL::State::S0; - if (output_sig.as_wire()->name == "$undef") + if (output_sig.as_wire()->name == ID($undef)) state = RTLIL::State::Sx; module->connect(RTLIL::SigSig(output_sig, state)); goto continue_without_read; @@ -484,23 +484,23 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (sop_mode) { - sopcell = module->addCell(NEW_ID, "$sop"); - sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); - sopcell->parameters["\\DEPTH"] = 0; - sopcell->parameters["\\TABLE"] = RTLIL::Const(); - sopcell->setPort("\\A", input_sig); - sopcell->setPort("\\Y", output_sig); + sopcell = module->addCell(NEW_ID, ID($sop)); + sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); + sopcell->parameters[ID::DEPTH] = 0; + sopcell->parameters[ID::TABLE] = RTLIL::Const(); + sopcell->setPort(ID::A, input_sig); + sopcell->setPort(ID::Y, output_sig); sopmode = -1; lastcell = sopcell; } else { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); - cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); - cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->setPort("\\A", input_sig); - cell->setPort("\\Y", output_sig); - lutptr = &cell->parameters.at("\\LUT"); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut)); + cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size()); + cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); + cell->setPort(ID::A, input_sig); + cell->setPort(ID::Y, output_sig); + lutptr = &cell->parameters.at(ID::LUT); lut_default_state = RTLIL::State::Sx; lastcell = cell; } @@ -523,32 +523,32 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (sopcell) { - log_assert(sopcell->parameters["\\WIDTH"].as_int() == input_len); - sopcell->parameters["\\DEPTH"] = sopcell->parameters["\\DEPTH"].as_int() + 1; + log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len); + sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1; for (int i = 0; i < input_len; i++) switch (input[i]) { case '0': - sopcell->parameters["\\TABLE"].bits.push_back(State::S1); - sopcell->parameters["\\TABLE"].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits.push_back(State::S1); + sopcell->parameters[ID::TABLE].bits.push_back(State::S0); break; case '1': - sopcell->parameters["\\TABLE"].bits.push_back(State::S0); - sopcell->parameters["\\TABLE"].bits.push_back(State::S1); + sopcell->parameters[ID::TABLE].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits.push_back(State::S1); break; default: - sopcell->parameters["\\TABLE"].bits.push_back(State::S0); - sopcell->parameters["\\TABLE"].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits.push_back(State::S0); + sopcell->parameters[ID::TABLE].bits.push_back(State::S0); break; } if (sopmode == -1) { sopmode = (*output == '1'); if (!sopmode) { - SigSpec outnet = sopcell->getPort("\\Y"); + SigSpec outnet = sopcell->getPort(ID::Y); SigSpec tempnet = module->addWire(NEW_ID); module->addNotGate(NEW_ID, tempnet, outnet); - sopcell->setPort("\\Y", tempnet); + sopcell->setPort(ID::Y, tempnet); } } else log_assert(sopmode == (*output == '1')); diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 14de95e07..6f0c3fefa 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -55,37 +55,37 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_"); - cell->setPort("\\A", A); - cell->setPort("\\Y", module->addWire(NEW_ID)); - return cell->getPort("\\Y"); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_)); + cell->setPort(ID::A, A); + cell->setPort(ID::Y, module->addWire(NEW_ID)); + return cell->getPort(ID::Y); } static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_"); - cell->setPort("\\A", A); - cell->setPort("\\B", B); - cell->setPort("\\Y", module->addWire(NEW_ID)); - return cell->getPort("\\Y"); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_XOR_)); + cell->setPort(ID::A, A); + cell->setPort(ID::B, B); + cell->setPort(ID::Y, module->addWire(NEW_ID)); + return cell->getPort(ID::Y); } static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_"); - cell->setPort("\\A", A); - cell->setPort("\\B", B); - cell->setPort("\\Y", module->addWire(NEW_ID)); - return cell->getPort("\\Y"); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_AND_)); + cell->setPort(ID::A, A); + cell->setPort(ID::B, B); + cell->setPort(ID::Y, module->addWire(NEW_ID)); + return cell->getPort(ID::Y); } static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_"); - cell->setPort("\\A", A); - cell->setPort("\\B", B); - cell->setPort("\\Y", module->addWire(NEW_ID)); - return cell->getPort("\\Y"); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_OR_)); + cell->setPort(ID::A, A); + cell->setPort(ID::B, B); + cell->setPort(ID::Y, module->addWire(NEW_ID)); + return cell->getPort(ID::Y); } static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token) @@ -241,32 +241,32 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node) rerun_invert_rollback = false; for (auto &it : module->cells_) { - if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) { - clk_sig = it.second->getPort("\\A"); + if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) { + clk_sig = it.second->getPort(ID::A); clk_polarity = !clk_polarity; rerun_invert_rollback = true; } - if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) { - clear_sig = it.second->getPort("\\A"); + if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) { + clear_sig = it.second->getPort(ID::A); clear_polarity = !clear_polarity; rerun_invert_rollback = true; } - if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) { - preset_sig = it.second->getPort("\\A"); + if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) { + preset_sig = it.second->getPort(ID::A); preset_polarity = !preset_polarity; rerun_invert_rollback = true; } } } - RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_"); - cell->setPort("\\A", iq_sig); - cell->setPort("\\Y", iqn_sig); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_)); + cell->setPort(ID::A, iq_sig); + cell->setPort(ID::Y, iqn_sig); cell = module->addCell(NEW_ID, ""); - cell->setPort("\\D", data_sig); - cell->setPort("\\Q", iq_sig); - cell->setPort("\\C", clk_sig); + cell->setPort(ID::D, data_sig); + cell->setPort(ID::Q, iq_sig); + cell->setPort(ID::C, clk_sig); if (clear_sig.size() == 0 && preset_sig.size() == 0) { cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); @@ -274,18 +274,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node) if (clear_sig.size() == 1 && preset_sig.size() == 0) { cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'); - cell->setPort("\\R", clear_sig); + cell->setPort(ID::R, clear_sig); } if (clear_sig.size() == 0 && preset_sig.size() == 1) { cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N'); - cell->setPort("\\R", preset_sig); + cell->setPort(ID::R, preset_sig); } if (clear_sig.size() == 1 && preset_sig.size() == 1) { cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'); - cell->setPort("\\S", preset_sig); - cell->setPort("\\R", clear_sig); + cell->setPort(ID::S, preset_sig); + cell->setPort(ID::R, clear_sig); } log_assert(!cell->type.empty()); @@ -324,27 +324,27 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno rerun_invert_rollback = false; for (auto &it : module->cells_) { - if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) { - enable_sig = it.second->getPort("\\A"); + if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) { + enable_sig = it.second->getPort(ID::A); enable_polarity = !enable_polarity; rerun_invert_rollback = true; } - if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) { - clear_sig = it.second->getPort("\\A"); + if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) { + clear_sig = it.second->getPort(ID::A); clear_polarity = !clear_polarity; rerun_invert_rollback = true; } - if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) { - preset_sig = it.second->getPort("\\A"); + if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) { + preset_sig = it.second->getPort(ID::A); preset_polarity = !preset_polarity; rerun_invert_rollback = true; } } } - RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_"); - cell->setPort("\\A", iq_sig); - cell->setPort("\\Y", iqn_sig); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_)); + cell->setPort(ID::A, iq_sig); + cell->setPort(ID::Y, iqn_sig); if (clear_sig.size() == 1) { @@ -353,25 +353,25 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno if (clear_polarity == true || clear_polarity != enable_polarity) { - RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_"); - inv->setPort("\\A", clear_sig); - inv->setPort("\\Y", module->addWire(NEW_ID)); + RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_)); + inv->setPort(ID::A, clear_sig); + inv->setPort(ID::Y, module->addWire(NEW_ID)); if (clear_polarity == true) - clear_negative = inv->getPort("\\Y"); + clear_negative = inv->getPort(ID::Y); if (clear_polarity != enable_polarity) - clear_enable = inv->getPort("\\Y"); + clear_enable = inv->getPort(ID::Y); } - RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_"); - data_gate->setPort("\\A", data_sig); - data_gate->setPort("\\B", clear_negative); - data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID)); + RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_)); + data_gate->setPort(ID::A, data_sig); + data_gate->setPort(ID::B, clear_negative); + data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); - RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_"); - enable_gate->setPort("\\A", enable_sig); - enable_gate->setPort("\\B", clear_enable); - enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID)); + RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); + enable_gate->setPort(ID::A, enable_sig); + enable_gate->setPort(ID::B, clear_enable); + enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); } if (preset_sig.size() == 1) @@ -381,31 +381,31 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno if (preset_polarity == false || preset_polarity != enable_polarity) { - RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_"); - inv->setPort("\\A", preset_sig); - inv->setPort("\\Y", module->addWire(NEW_ID)); + RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_)); + inv->setPort(ID::A, preset_sig); + inv->setPort(ID::Y, module->addWire(NEW_ID)); if (preset_polarity == false) - preset_positive = inv->getPort("\\Y"); + preset_positive = inv->getPort(ID::Y); if (preset_polarity != enable_polarity) - preset_enable = inv->getPort("\\Y"); + preset_enable = inv->getPort(ID::Y); } - RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_"); - data_gate->setPort("\\A", data_sig); - data_gate->setPort("\\B", preset_positive); - data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID)); + RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_)); + data_gate->setPort(ID::A, data_sig); + data_gate->setPort(ID::B, preset_positive); + data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); - RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_"); - enable_gate->setPort("\\A", enable_sig); - enable_gate->setPort("\\B", preset_enable); - enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID)); + RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_)); + enable_gate->setPort(ID::A, enable_sig); + enable_gate->setPort(ID::B, preset_enable); + enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); } cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')); - cell->setPort("\\D", data_sig); - cell->setPort("\\Q", iq_sig); - cell->setPort("\\E", enable_sig); + cell->setPort(ID::D, data_sig); + cell->setPort(ID::Q, iq_sig); + cell->setPort(ID::E, enable_sig); return true; } @@ -550,13 +550,13 @@ struct LibertyFrontend : public Frontend { if (design->has(cell_name)) { Module *existing_mod = design->module(cell_name); - if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { + if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { log_error("Re-definition of cell/module %s!\n", log_id(cell_name)); } else if (flag_nooverwrite) { log("Ignoring re-definition of module %s.\n", log_id(cell_name)); continue; } else { - log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name)); + log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name)); design->remove(existing_mod); } } @@ -570,7 +570,7 @@ struct LibertyFrontend : public Frontend { module->name = cell_name; if (flag_lib) - module->set_bool_attribute("\\blackbox"); + module->set_bool_attribute(ID::blackbox); for (auto &attr : attributes) module->attributes[attr] = 1; diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index add17c243..a23f7548e 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -157,7 +157,7 @@ struct RpcServer { struct RpcModule : RTLIL::Module { std::shared_ptr<RpcServer> server; - RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool /*mayfail*/) YS_OVERRIDE { + RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool /*mayfail*/) YS_OVERRIDE { std::string stripped_name = name.str(); if (stripped_name.compare(0, 9, "$abstract") == 0) stripped_name = stripped_name.substr(9); @@ -216,7 +216,7 @@ struct RpcModule : RTLIL::Module { module.second->name = mangled_name; module.second->design = design; - module.second->attributes.erase("\\top"); + module.second->attributes.erase(ID::top); design->modules_[mangled_name] = module.second; derived_design->modules_.erase(module.first); } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ae5815f8e..519151310 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -155,7 +155,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att Att *attr; if (obj->Linefile()) - attributes["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile())); + attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile())); // FIXME: Parse numeric attributes FOREACH_ATTRIBUTE(obj, mi, attr) { @@ -738,7 +738,7 @@ void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBi SigSpec dbits; for (auto cell : candidates) { - SigBit bit = sigmap(cell->getPort("\\D")); + SigBit bit = sigmap(cell->getPort(ID::D)); dbits_db[bit].insert(cell); dbits.append(bit); } @@ -764,7 +764,7 @@ void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBi if (verific_verbose) log(" replacing old ff %s on bit %d.\n", log_id(old_ff), i); - SigBit old_q = old_ff->getPort("\\Q"); + SigBit old_q = old_ff->getPort(ID::Q); SigBit new_q = sig_q[i]; sigmap.add(old_q, new_q); @@ -783,8 +783,8 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates) for (auto cell : candidates) { - SigBit clock = cell->getPort("\\CLK"); - bool clock_pol = cell->getParam("\\CLK_POLARITY").as_bool(); + SigBit clock = cell->getPort(ID::CLK); + bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool(); database[make_pair(clock, int(clock_pol))].insert(cell); } @@ -822,7 +822,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (is_blackbox(nl)) { log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); - module->set_bool_attribute("\\blackbox"); + module->set_bool_attribute(ID::blackbox); } else { log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } @@ -952,17 +952,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se ascii_initdata++; } if (initval_valid) { - RTLIL::Cell *cell = module->addCell(new_verific_id(net), "$meminit"); - cell->parameters["\\WORDS"] = 1; + RTLIL::Cell *cell = module->addCell(new_verific_id(net), ID($meminit)); + cell->parameters[ID::WORDS] = 1; if (net->GetOrigTypeRange()->LeftRangeBound() < net->GetOrigTypeRange()->RightRangeBound()) - cell->setPort("\\ADDR", word_idx); + cell->setPort(ID::ADDR, word_idx); else - cell->setPort("\\ADDR", memory->size - word_idx - 1); - cell->setPort("\\DATA", initval); - cell->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); - cell->parameters["\\ABITS"] = 32; - cell->parameters["\\WIDTH"] = memory->width; - cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1); + cell->setPort(ID::ADDR, memory->size - word_idx - 1); + cell->setPort(ID::DATA, initval); + cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str()); + cell->parameters[ID::ABITS] = 32; + cell->parameters[ID::WIDTH] = memory->width; + cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1); } } } @@ -1079,7 +1079,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se } if (initval_valid) - wire->attributes["\\init"] = initval; + wire->attributes[ID::init] = initval; } else { @@ -1133,8 +1133,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se SigBit bit = net_map_at(it.first); log_assert(bit.wire); - if (bit.wire->attributes.count("\\init")) - initval = bit.wire->attributes.at("\\init"); + if (bit.wire->attributes.count(ID::init)) + initval = bit.wire->attributes.at(ID::init); while (GetSize(initval) < GetSize(bit.wire)) initval.bits.push_back(State::Sx); @@ -1144,7 +1144,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (it.second == '1') initval.bits.at(bit.offset) = State::S1; - bit.wire->attributes["\\init"] = initval; + bit.wire->attributes[ID::init] = initval; } for (auto net : anyconst_nets) @@ -1212,17 +1212,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : - RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memrd"); - cell->parameters["\\MEMID"] = memory->name.str(); - cell->parameters["\\CLK_ENABLE"] = false; - cell->parameters["\\CLK_POLARITY"] = true; - cell->parameters["\\TRANSPARENT"] = false; - cell->parameters["\\ABITS"] = GetSize(addr); - cell->parameters["\\WIDTH"] = GetSize(data); - cell->setPort("\\CLK", RTLIL::State::Sx); - cell->setPort("\\EN", RTLIL::State::Sx); - cell->setPort("\\ADDR", addr); - cell->setPort("\\DATA", data); + RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd)); + cell->parameters[ID::MEMID] = memory->name.str(); + cell->parameters[ID::CLK_ENABLE] = false; + cell->parameters[ID::CLK_POLARITY] = true; + cell->parameters[ID::TRANSPARENT] = false; + cell->parameters[ID::ABITS] = GetSize(addr); + cell->parameters[ID::WIDTH] = GetSize(data); + cell->setPort(ID::CLK, RTLIL::State::Sx); + cell->setPort(ID::EN, RTLIL::State::Sx); + cell->setPort(ID::ADDR, addr); + cell->setPort(ID::DATA, data); } continue; } @@ -1242,21 +1242,21 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : - RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memwr"); - cell->parameters["\\MEMID"] = memory->name.str(); - cell->parameters["\\CLK_ENABLE"] = false; - cell->parameters["\\CLK_POLARITY"] = true; - cell->parameters["\\PRIORITY"] = 0; - cell->parameters["\\ABITS"] = GetSize(addr); - cell->parameters["\\WIDTH"] = GetSize(data); - cell->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data))); - cell->setPort("\\CLK", RTLIL::State::S0); - cell->setPort("\\ADDR", addr); - cell->setPort("\\DATA", data); + RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr)); + cell->parameters[ID::MEMID] = memory->name.str(); + cell->parameters[ID::CLK_ENABLE] = false; + cell->parameters[ID::CLK_POLARITY] = true; + cell->parameters[ID::PRIORITY] = 0; + cell->parameters[ID::ABITS] = GetSize(addr); + cell->parameters[ID::WIDTH] = GetSize(data); + cell->setPort(ID::EN, RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data))); + cell->setPort(ID::CLK, RTLIL::State::S0); + cell->setPort(ID::ADDR, addr); + cell->setPort(ID::DATA, data); if (inst->Type() == OPER_CLOCKED_WRITE_PORT) { - cell->parameters["\\CLK_ENABLE"] = true; - cell->setPort("\\CLK", net_map_at(inst->GetClock())); + cell->parameters[ID::CLK_ENABLE] = true; + cell->setPort(ID::CLK, net_map_at(inst->GetClock())); } } continue; @@ -1431,7 +1431,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::Cell *cell = module->addCell(inst_name, inst_type); if (inst->IsPrimitive() && mode_keep) - cell->attributes["\\keep"] = 1; + cell->attributes[ID::keep] = 1; dict<IdString, vector<SigBit>> cell_port_conns; @@ -1514,10 +1514,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se for (auto wire : module->wires()) { - if (!wire->attributes.count("\\init")) + if (!wire->attributes.count(ID::init)) continue; - Const &initval = wire->attributes.at("\\init"); + Const &initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initval); i++) { if (initval[i] != State::S0 && initval[i] != State::S1) @@ -1528,7 +1528,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se } if (initval.is_fully_undef()) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); } } } @@ -1652,10 +1652,10 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const if (GetSize(init_value) != 0) { log_assert(GetSize(sig_q) == GetSize(init_value)); if (sig_q.is_wire()) { - sig_q.as_wire()->attributes["\\init"] = init_value; + sig_q.as_wire()->attributes[ID::init] = init_value; } else { Wire *w = module->addWire(NEW_ID, GetSize(sig_q)); - w->attributes["\\init"] = init_value; + w->attributes[ID::init] = init_value; module->connect(sig_q, w); sig_q = w; } diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index 6a8462b41..cf9b9531e 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -10,7 +10,7 @@ frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc -frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l +frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l frontends/verilog/verilog_parser.tab.cc $(Q) mkdir -p $(dir $@) $(P) flex -o frontends/verilog/verilog_lexer.cc $< diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 49281f7e7..230dfadbf 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -139,6 +139,9 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le data.resize(len_in_bits, msb); } + if (len_in_bits == 0) + log_file_error(current_filename, get_line_num(), "Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n"); + if (len > len_in_bits) log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n", len_in_bits, len, current_filename.c_str(), get_line_num()); diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 161253a99..7905ea598 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -32,8 +32,10 @@ * */ +#include "preproc.h" #include "verilog_frontend.h" #include "kernel/log.h" +#include <assert.h> #include <stdarg.h> #include <stdio.h> #include <string.h> @@ -199,6 +201,175 @@ static std::string next_token(bool pass_newline = false) return token; } +struct macro_arg_t +{ + macro_arg_t(const std::string &name_, const char *default_value_) + : name(name_), + has_default(default_value_ != nullptr), + default_value(default_value_ ? default_value_ : "") + {} + + std::string name; + bool has_default; + std::string default_value; +}; + +static bool all_white(const std::string &str) +{ + for (char c : str) + if (!isspace(c)) + return false; + return true; +} + +struct arg_map_t +{ + arg_map_t() + {} + + void add_arg(const std::string &name, const char *default_value) + { + if (find(name)) { + log_error("Duplicate macro arguments with name `%s'.\n", name.c_str()); + } + + name_to_pos[name] = args.size(); + args.push_back(macro_arg_t(name, default_value)); + } + + // Find an argument by name; return nullptr if it doesn't exist. If pos is not null, write + // the argument's position to it on success. + const macro_arg_t *find(const std::string &name, int *pos = nullptr) const + { + auto it = name_to_pos.find(name); + if (it == name_to_pos.end()) + return nullptr; + + if (pos) *pos = it->second; + return &args[it->second]; + } + + // Construct the name for the local macro definition we use for the given argument + // (something like macro_foobar_arg2). This doesn't include the leading backtick. + static std::string str_token(const std::string ¯o_name, int pos) + { + return stringf("macro_%s_arg%d", macro_name.c_str(), pos); + } + + // Return definitions for the macro arguments (so that substituting in the macro body and + // then performing macro expansion will do argument substitution properly). + std::vector<std::pair<std::string, std::string>> + get_vals(const std::string ¯o_name, const std::vector<std::string> &arg_vals) const + { + std::vector<std::pair<std::string, std::string>> ret; + for (int i = 0; i < GetSize(args); ++ i) { + // The SystemVerilog rules are: + // + // - If the call site specifies an argument and it's not whitespace, use + // it. + // + // - Otherwise, if the argument has a default value, use it. + // + // - Otherwise, if the call site specified whitespace, use that. + // + // - Otherwise, error. + const std::string *dflt = nullptr; + if (args[i].has_default) + dflt = &args[i].default_value; + + const std::string *given = nullptr; + if (i < GetSize(arg_vals)) + given = &arg_vals[i]; + + const std::string *val = nullptr; + if (given && (! (dflt && all_white(*given)))) + val = given; + else if (dflt) + val = dflt; + else if (given) + val = given; + else + log_error("Cannot expand macro `%s by giving only %d argument%s " + "(argument %d has no default).\n", + macro_name.c_str(), GetSize(arg_vals), + (GetSize(arg_vals) == 1 ? "" : "s"), i + 1); + + assert(val); + ret.push_back(std::make_pair(str_token(macro_name, i), * val)); + } + return ret; + } + + + std::vector<macro_arg_t> args; + std::map<std::string, int> name_to_pos; +}; + +struct define_body_t +{ + define_body_t(const std::string &body, const arg_map_t *args = nullptr) + : body(body), + has_args(args != nullptr), + args(args ? *args : arg_map_t()) + {} + + std::string body; + bool has_args; + arg_map_t args; +}; + +define_map_t::define_map_t() +{ + add("YOSYS", "1"); + add(formal_mode ? "FORMAL" : "SYNTHESIS", "1"); +} + +// We must define this destructor here (rather than relying on the default), because we need to +// define it somewhere we've got a complete definition of define_body_t. +define_map_t::~define_map_t() +{} + +void +define_map_t::add(const std::string &name, const std::string &txt, const arg_map_t *args) +{ + defines[name] = std::unique_ptr<define_body_t>(new define_body_t(txt, args)); +} + +void define_map_t::merge(const define_map_t &map) +{ + for (const auto &pr : map.defines) { + // These contortions are so that we take a copy of each definition body in + // map.defines. + defines[pr.first] = std::unique_ptr<define_body_t>(new define_body_t(*pr.second)); + } +} + +const define_body_t *define_map_t::find(const std::string &name) const +{ + auto it = defines.find(name); + return (it == defines.end()) ? nullptr : it->second.get(); +} + +void define_map_t::erase(const std::string &name) +{ + defines.erase(name); +} + +void define_map_t::clear() +{ + defines.clear(); +} + +void define_map_t::log() const +{ + for (auto &it : defines) { + const std::string &name = it.first; + const define_body_t &body = *it.second; + Yosys::log("`define %s%s %s\n", + name.c_str(), body.has_args ? "()" : "", body.body.c_str()); + } +} + static void input_file(std::istream &f, std::string filename) { char buffer[513]; @@ -215,11 +386,59 @@ static void input_file(std::istream &f, std::string filename) input_buffer.insert(it, "\n`file_pop\n"); } +// Read tokens to get one argument (either a macro argument at a callsite or a default argument in a +// macro definition). Writes the argument to dest. Returns true if we finished with ')' (the end of +// the argument list); false if we finished with ','. +static bool read_argument(std::string &dest) +{ + std::vector<char> openers; + for (;;) { + skip_spaces(); + std::string tok = next_token(true); + if (tok == ")") { + if (openers.empty()) + return true; + if (openers.back() != '(') + log_error("Mismatched brackets in macro argument: %c and %c.\n", + openers.back(), tok[0]); + + openers.pop_back(); + dest += tok; + continue; + } + if (tok == "]") { + char opener = openers.empty() ? '(' : openers.back(); + if (opener != '[') + log_error("Mismatched brackets in macro argument: %c and %c.\n", + opener, tok[0]); + + openers.pop_back(); + dest += tok; + continue; + } + if (tok == "}") { + char opener = openers.empty() ? '(' : openers.back(); + if (opener != '{') + log_error("Mismatched brackets in macro argument: %c and %c.\n", + opener, tok[0]); + + openers.pop_back(); + dest += tok; + continue; + } + + if (tok == "," && openers.empty()) { + return false; + } + + if (tok == "(" || tok == "[" || tok == "{") + openers.push_back(tok[0]); -static bool try_expand_macro(std::set<std::string> &defines_with_args, - std::map<std::string, std::string> &defines_map, - std::string &tok - ) + dest += tok; + } +} + +static bool try_expand_macro(define_map_t &defines, std::string &tok) { if (tok == "`\"") { std::string literal("\""); @@ -229,54 +448,272 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args, if (ntok == "`\"") { insert_input(literal+"\""); return true; - } else if (!try_expand_macro(defines_with_args, defines_map, ntok)) { + } else if (!try_expand_macro(defines, ntok)) { literal += ntok; } } return false; // error - unmatched `" - } else if (tok.size() > 1 && tok[0] == '`' && defines_map.count(tok.substr(1)) > 0) { - std::string name = tok.substr(1); - // printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str()); - std::string skipped_spaces = skip_spaces(); - tok = next_token(false); - if (tok == "(" && defines_with_args.count(name) > 0) { - int level = 1; - std::vector<std::string> args; - args.push_back(std::string()); - while (1) - { - skip_spaces(); - tok = next_token(true); - if (tok == ")" || tok == "}" || tok == "]") - level--; - if (level == 0) - break; - if (level == 1 && tok == ",") - args.push_back(std::string()); - else - args.back() += tok; - if (tok == "(" || tok == "{" || tok == "[") - level++; - } - for (int i = 0; i < GetSize(args); i++) - defines_map[stringf("macro_%s_arg%d", name.c_str(), i+1)] = args[i]; - } else { - insert_input(tok); - insert_input(skipped_spaces); - } - insert_input(defines_map[name]); - return true; - } else if (tok == "``") { + } + + if (tok == "``") { // Swallow `` in macro expansion return true; - } else return false; + } + + if (tok.size() <= 1 || tok[0] != '`') + return false; + + // This token looks like a macro name (`foo). + std::string macro_name = tok.substr(1); + const define_body_t *body = defines.find(tok.substr(1)); + + if (! body) { + // Apparently not a name we know. + return false; + } + + std::string name = tok.substr(1); + std::string skipped_spaces = skip_spaces(); + tok = next_token(false); + if (tok == "(" && body->has_args) { + std::vector<std::string> args; + bool done = false; + while (!done) { + std::string arg; + done = read_argument(arg); + args.push_back(arg); + } + for (const auto &pr : body->args.get_vals(name, args)) { + defines.add(pr.first, pr.second); + } + } else { + insert_input(tok); + insert_input(skipped_spaces); + } + insert_input(body->body); + return true; } -std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map, - dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs) +// Read the arguments for a `define preprocessor directive with formal arguments. This is called +// just after reading the token containing "(". Returns the number of newlines to emit afterwards to +// keep line numbers in sync, together with the map from argument name to data (pos and default +// value). +static std::pair<int, arg_map_t> +read_define_args() { - std::set<std::string> defines_with_args; - std::map<std::string, std::string> defines_map(pre_defines_map); + // Each argument looks like one of the following: + // + // identifier + // identifier = default_text + // identifier = + // + // The first example is an argument with no default value. The second is an argument whose + // default value is default_text. The third is an argument with default value the empty + // string. + + int newline_count = 0; + arg_map_t args; + + // FSM state. + // + // 0: At start of identifier + // 1: After identifier (stored in arg_name) + // 2: After closing paren + int state = 0; + + std::string arg_name, default_val; + + skip_spaces(); + for (;;) { + if (state == 2) + // We've read the closing paren. + break; + + std::string tok = next_token(); + + // Cope with escaped EOLs + if (tok == "\\") { + char ch = next_char(); + if (ch == '\n') { + // Eat the \, the \n and any trailing space and keep going. + skip_spaces(); + continue; + } else { + // There aren't any other situations where a backslash makes sense. + log_error("Backslash in macro arguments (not at end of line).\n"); + } + } + + switch (state) { + case 0: + // At start of argument. If the token is ')', we've presumably just seen + // something like "`define foo() ...". Set state to 2 to finish. Otherwise, + // the token should be a valid simple identifier, but we'll allow anything + // here. + if (tok == ")") { + state = 2; + } else { + arg_name = tok; + state = 1; + } + skip_spaces(); + break; + + case 1: + // After argument. The token should either be an equals sign or a comma or + // closing paren. + if (tok == "=") { + std::string default_val; + //Read an argument into default_val and set state to 2 if we're at + // the end; 0 if we hit a comma. + state = read_argument(default_val) ? 2 : 0; + args.add_arg(arg_name, default_val.c_str()); + skip_spaces(); + break; + } + if (tok == ",") { + // Take the identifier as an argument with no default value. + args.add_arg(arg_name, nullptr); + state = 0; + skip_spaces(); + break; + } + if (tok == ")") { + // As with comma, but set state to 2 (end of args) + args.add_arg(arg_name, nullptr); + state = 2; + skip_spaces(); + break; + } + log_error("Trailing contents after identifier in macro argument `%s': " + "expected '=', ',' or ')'.\n", + arg_name.c_str()); + + default: + // The only FSM states are 0-2 and we dealt with 2 at the start of the loop. + __builtin_unreachable(); + } + } + + return std::make_pair(newline_count, args); +} + +// Read a `define preprocessor directive. This is called just after reading the token containing +// "`define". +static void +read_define(const std::string &filename, + define_map_t &defines_map, + define_map_t &global_defines_cache) +{ + std::string name, value; + arg_map_t args; + + skip_spaces(); + name = next_token(true); + + bool here_doc_mode = false; + int newline_count = 0; + + // The FSM state starts at 0. If it sees space (or enters here_doc_mode), it assumes this is + // a macro without formal arguments and jumps to state 1. + // + // In state 0, if it sees an opening parenthesis, it assumes this is a macro with formal + // arguments. It reads the arguments with read_define_args() and then jumps to state 2. + // + // In states 1 or 2, the FSM reads tokens to the end of line (or end of here_doc): this is + // the body of the macro definition. + int state = 0; + + if (skip_spaces() != "") + state = 1; + + for (;;) { + std::string tok = next_token(); + if (tok.empty()) + break; + + // printf("define-tok: >>%s<<\n", tok != "\n" ? tok.c_str() : "NEWLINE"); + + if (tok == "\"\"\"") { + here_doc_mode = !here_doc_mode; + continue; + } + + if (state == 0 && tok == "(") { + auto pr = read_define_args(); + newline_count += pr.first; + args = pr.second; + + state = 2; + continue; + } + + // This token isn't an opening parenthesis immediately following the macro name, so + // it's presumably at or after the start of the macro body. If state isn't already 2 + // (which would mean we'd parsed an argument list), set it to 1. + if (state == 0) { + state = 1; + } + + if (tok == "\n") { + if (here_doc_mode) { + value += " "; + newline_count++; + } else { + return_char('\n'); + break; + } + continue; + } + + if (tok == "\\") { + char ch = next_char(); + if (ch == '\n') { + value += " "; + newline_count++; + } else { + value += std::string("\\"); + return_char(ch); + } + continue; + } + + // Is this token the name of a macro argument? If so, replace it with a magic symbol + // that we'll replace with the argument value. + int arg_pos; + if (args.find(tok, &arg_pos)) { + value += '`' + args.str_token(name, arg_pos); + continue; + } + + // This token is nothing special. Insert it verbatim into the macro body. + value += tok; + } + + // Append some newlines so that we don't mess up line counts in error messages. + while (newline_count-- > 0) + return_char('\n'); + + if (strchr("abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789", name[0])) { + // printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str()); + defines_map.add(name, value, (state == 2) ? &args : nullptr); + global_defines_cache.add(name, value, (state == 2) ? &args : nullptr); + } else { + log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str()); + } +} + +std::string +frontend_verilog_preproc(std::istream &f, + std::string filename, + const define_map_t &pre_defines, + define_map_t &global_defines_cache, + const std::list<std::string> &include_dirs) +{ + define_map_t defines; + defines.merge(pre_defines); + defines.merge(global_defines_cache); + std::vector<std::string> filename_stack; int ifdef_fail_level = 0; bool in_elseif = false; @@ -287,18 +724,6 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons input_file(f, filename); - defines_map["YOSYS"] = "1"; - defines_map[formal_mode ? "FORMAL" : "SYNTHESIS"] = "1"; - - for (auto &it : pre_defines_map) - defines_map[it.first] = it.second; - - for (auto &it : global_defines_cache) { - if (it.second.second) - defines_with_args.insert(it.first); - defines_map[it.first] = it.second.first; - } - while (!input_buffer.empty()) { std::string tok = next_token(); @@ -325,7 +750,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons std::string name = next_token(true); if (ifdef_fail_level == 0) ifdef_fail_level = 1, in_elseif = true; - else if (ifdef_fail_level == 1 && defines_map.count(name) != 0) + else if (ifdef_fail_level == 1 && defines.find(name)) ifdef_fail_level = 0, in_elseif = true; continue; } @@ -333,7 +758,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons if (tok == "`ifdef") { skip_spaces(); std::string name = next_token(true); - if (ifdef_fail_level > 0 || defines_map.count(name) == 0) + if (ifdef_fail_level > 0 || !defines.find(name)) ifdef_fail_level++; continue; } @@ -341,7 +766,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons if (tok == "`ifndef") { skip_spaces(); std::string name = next_token(true); - if (ifdef_fail_level > 0 || defines_map.count(name) != 0) + if (ifdef_fail_level > 0 || defines.find(name)) ifdef_fail_level++; continue; } @@ -355,7 +780,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons if (tok == "`include") { skip_spaces(); std::string fn = next_token(true); - while (try_expand_macro(defines_with_args, defines_map, fn)) { + while (try_expand_macro(defines, fn)) { fn = next_token(); } while (1) { @@ -433,74 +858,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons } if (tok == "`define") { - std::string name, value; - std::map<std::string, int> args; - skip_spaces(); - name = next_token(true); - bool here_doc_mode = false; - int newline_count = 0; - int state = 0; - if (skip_spaces() != "") - state = 3; - while (!tok.empty()) { - tok = next_token(); - if (tok == "\"\"\"") { - here_doc_mode = !here_doc_mode; - continue; - } - if (state == 0 && tok == "(") { - state = 1; - skip_spaces(); - } else - if (state == 1) { - if (tok == ")") - state = 2; - else if (tok != ",") { - int arg_idx = args.size()+1; - args[tok] = arg_idx; - } - skip_spaces(); - } else { - if (state != 2) - state = 3; - if (tok == "\n") { - if (here_doc_mode) { - value += " "; - newline_count++; - } else { - return_char('\n'); - break; - } - } else - if (tok == "\\") { - char ch = next_char(); - if (ch == '\n') { - value += " "; - newline_count++; - } else { - value += std::string("\\"); - return_char(ch); - } - } else - if (args.count(tok) > 0) - value += stringf("`macro_%s_arg%d", name.c_str(), args.at(tok)); - else - value += tok; - } - } - while (newline_count-- > 0) - return_char('\n'); - if (strchr("abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789", name[0])) { - // printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str()); - defines_map[name] = value; - if (state == 2) - defines_with_args.insert(name); - else - defines_with_args.erase(name); - global_defines_cache[name] = std::pair<std::string, bool>(value, state == 2); - } else { - log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str()); - } + read_define(filename, defines, global_defines_cache); continue; } @@ -509,8 +867,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons skip_spaces(); name = next_token(true); // printf("undef: >>%s<<\n", name.c_str()); - defines_map.erase(name); - defines_with_args.erase(name); + defines.erase(name); global_defines_cache.erase(name); continue; } @@ -525,13 +882,12 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons } if (tok == "`resetall") { - defines_map.clear(); - defines_with_args.clear(); + defines.clear(); global_defines_cache.clear(); continue; } - if (try_expand_macro(defines_with_args, defines_map, tok)) + if (try_expand_macro(defines, tok)) continue; output_code.push_back(tok); diff --git a/frontends/verilog/preproc.h b/frontends/verilog/preproc.h new file mode 100644 index 000000000..673d633c0 --- /dev/null +++ b/frontends/verilog/preproc.h @@ -0,0 +1,77 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * The Verilog preprocessor. + * + */ +#ifndef VERILOG_PREPROC_H +#define VERILOG_PREPROC_H + +#include "kernel/yosys.h" + +#include <iosfwd> +#include <list> +#include <memory> +#include <string> + +YOSYS_NAMESPACE_BEGIN + +struct define_body_t; +struct arg_map_t; + +struct define_map_t +{ + define_map_t(); + ~ define_map_t(); + + // Add a definition, overwriting any existing definition for name. + void add(const std::string &name, const std::string &txt, const arg_map_t *args = nullptr); + + // Merge in another map of definitions (which take precedence + // over anything currently defined). + void merge(const define_map_t &map); + + // Find a definition by name. If no match, returns null. + const define_body_t *find(const std::string &name) const; + + // Erase a definition by name (no effect if not defined). + void erase(const std::string &name); + + // Clear any existing definitions + void clear(); + + // Print a list of definitions, using the log function + void log() const; + + std::map<std::string, std::unique_ptr<define_body_t>> defines; +}; + + +struct define_map_t; + +std::string +frontend_verilog_preproc(std::istream &f, + std::string filename, + const define_map_t &pre_defines, + define_map_t &global_defines_cache, + const std::list<std::string> &include_dirs); + +YOSYS_NAMESPACE_END + +#endif diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 42eabc02d..6879e0943 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -27,6 +27,7 @@ */ #include "verilog_frontend.h" +#include "preproc.h" #include "kernel/yosys.h" #include "libs/sha1/sha1.h" #include <stdarg.h> @@ -47,6 +48,23 @@ static void error_on_dpi_function(AST::AstNode *node) error_on_dpi_function(child); } +static void add_package_types(std::map<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list) +{ + // prime the parser's user type lookup table with the package qualified names + // of typedefed names in the packages seen so far. + for (const auto &pkg : package_list) { + log_assert(pkg->type==AST::AST_PACKAGE); + for (const auto &node: pkg->children) { + if (node->type == AST::AST_TYPEDEF) { + std::string s = pkg->str + "::" + node->str.substr(1); + user_types[s] = node; + } + } + } + user_type_stack.clear(); + user_type_stack.push_back(new UserTypeMap()); +} + struct VerilogFrontend : public Frontend { VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { } void help() YS_OVERRIDE @@ -237,7 +255,8 @@ struct VerilogFrontend : public Frontend { bool flag_defer = false; bool flag_noblackbox = false; bool flag_nowb = false; - std::map<std::string, std::string> defines_map; + define_map_t defines_map; + std::list<std::string> include_dirs; std::list<std::string> attributes; @@ -353,7 +372,7 @@ struct VerilogFrontend : public Frontend { } if (arg == "-lib") { lib_mode = true; - defines_map["BLACKBOX"] = string(); + defines_map.add("BLACKBOX", ""); continue; } if (arg == "-nowb") { @@ -405,7 +424,7 @@ struct VerilogFrontend : public Frontend { value = name.substr(equal+1); name = name.substr(0, equal); } - defines_map[name] = value; + defines_map.add(name, value); continue; } if (arg.compare(0, 2, "-D") == 0) { @@ -414,7 +433,7 @@ struct VerilogFrontend : public Frontend { std::string value; if (equal != std::string::npos) value = arg.substr(equal+1); - defines_map[name] = value; + defines_map.add(name, value); continue; } if (arg == "-I" && argidx+1 < args.size()) { @@ -444,12 +463,15 @@ struct VerilogFrontend : public Frontend { std::string code_after_preproc; if (!flag_nopp) { - code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, design->verilog_defines, include_dirs); + code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs); if (flag_ppdump) log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str()); lexin = new std::istringstream(code_after_preproc); } + // make package typedefs available to parser + add_package_types(pkg_user_types, design->verilog_packages); + frontend_verilog_yyset_lineno(1); frontend_verilog_yyrestart(NULL); frontend_verilog_yyparse(); @@ -468,6 +490,7 @@ struct VerilogFrontend : public Frontend { AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); + if (!flag_nopp) delete lexin; @@ -572,7 +595,7 @@ struct VerilogDefines : public Pass { value = name.substr(equal+1); name = name.substr(0, equal); } - design->verilog_defines[name] = std::pair<std::string, bool>(value, false); + design->verilog_defines->add(name, value); continue; } if (arg.compare(0, 2, "-D") == 0) { @@ -581,27 +604,25 @@ struct VerilogDefines : public Pass { std::string value; if (equal != std::string::npos) value = arg.substr(equal+1); - design->verilog_defines[name] = std::pair<std::string, bool>(value, false); + design->verilog_defines->add(name, value); continue; } if (arg == "-U" && argidx+1 < args.size()) { std::string name = args[++argidx]; - design->verilog_defines.erase(name); + design->verilog_defines->erase(name); continue; } if (arg.compare(0, 2, "-U") == 0) { std::string name = arg.substr(2); - design->verilog_defines.erase(name); + design->verilog_defines->erase(name); continue; } if (arg == "-reset") { - design->verilog_defines.clear(); + design->verilog_defines->clear(); continue; } if (arg == "-list") { - for (auto &it : design->verilog_defines) { - log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str()); - } + design->verilog_defines->log(); continue; } break; diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index a2e06f0e4..444cc7297 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -45,6 +45,13 @@ namespace VERILOG_FRONTEND // this function converts a Verilog constant to an AST_CONSTANT node AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false); + // names of locally typedef'ed types in a stack + typedef std::map<std::string, AST::AstNode*> UserTypeMap; + extern std::vector<UserTypeMap *> user_type_stack; + + // names of package typedef'ed types + extern std::map<std::string, AST::AstNode*> pkg_user_types; + // state of `default_nettype extern bool default_nettype_wire; @@ -79,10 +86,6 @@ namespace VERILOG_FRONTEND extern std::istream *lexin; } -// the pre-processor -std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map, - dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs); - YOSYS_NAMESPACE_END // the usual bison/flex stuff diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index d22a18458..f6a3ac4db 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -99,6 +99,18 @@ YYLTYPE old_location; #define YY_BUF_SIZE 65536 extern int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param); + +static bool isUserType(std::string &s) +{ + // check current scope then outer scopes for a name + for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) { + if ((*it)->count(s) > 0) { + return true; + } + } + return false; +} + %} %option yylineno @@ -372,9 +384,34 @@ supply1 { return TOK_SUPPLY1; } "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } +[a-zA-Z_][a-zA-Z0-9_]*::[a-zA-Z_$][a-zA-Z0-9_$]* { + // package qualifier + auto s = std::string("\\") + yytext; + if (pkg_user_types.count(s) > 0) { + // package qualified typedefed name + yylval->string = new std::string(s); + return TOK_PKG_USER_TYPE; + } + else { + // backup before :: just return first part + size_t len = strchr(yytext, ':') - yytext; + yyless(len); + yylval->string = new std::string(std::string("\\") + yytext); + return TOK_ID; + } +} + [a-zA-Z_$][a-zA-Z0-9_$]* { - yylval->string = new std::string(std::string("\\") + yytext); - return TOK_ID; + auto s = std::string("\\") + yytext; + if (isUserType(s)) { + // previously typedefed name + yylval->string = new std::string(s); + return TOK_USER_TYPE; + } + else { + yylval->string = new std::string(std::string("\\") + yytext); + return TOK_ID; + } } [a-zA-Z_$][a-zA-Z0-9_$\.]* { diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d04b32509..3bffa3986 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -54,6 +54,8 @@ namespace VERILOG_FRONTEND { std::map<std::string, AstNode*> *attr_list, default_attr_list; std::stack<std::map<std::string, AstNode*> *> attr_list_stack; std::map<std::string, AstNode*> *albuf; + std::vector<UserTypeMap*> user_type_stack; + std::map<std::string, AstNode*> pkg_user_types; std::vector<AstNode*> ast_stack; struct AstNode *astbuf1, *astbuf2, *astbuf3; struct AstNode *current_function_or_task; @@ -125,6 +127,40 @@ struct specify_rise_fall { specify_triple fall; }; +static void addTypedefNode(std::string *name, AstNode *node) +{ + log_assert(node); + auto *tnode = new AstNode(AST_TYPEDEF, node); + tnode->str = *name; + auto user_types = user_type_stack.back(); + (*user_types)[*name] = tnode; + if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) { + // typedef inside a package so we need the qualified name + auto qname = current_ast_mod->str + "::" + (*name).substr(1); + pkg_user_types[qname] = tnode; + } + delete name; + ast_stack.back()->children.push_back(tnode); +} + +static void enterTypeScope() +{ + auto user_types = new UserTypeMap(); + user_type_stack.push_back(user_types); +} + +static void exitTypeScope() +{ + user_type_stack.pop_back(); +} + +static bool isInLocalScope(const std::string *name) +{ + // tests if a name was declared in the current block scope + auto user_types = user_type_stack.back(); + return (user_types->count(*name) > 0); +} + static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true) { auto range = new AstNode(AST_RANGE); @@ -167,6 +203,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL +%token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM @@ -190,6 +227,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned = %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number +%type <string> type_name %type <ast> opt_enum_init %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff %type <al> attr case_attr @@ -330,10 +368,15 @@ hierarchical_id: }; hierarchical_type_id: - '(' hierarchical_id ')' { $$ = $2; }; + TOK_USER_TYPE + | TOK_PKG_USER_TYPE // package qualified type name + | '(' TOK_USER_TYPE ')' { $$ = $2; } // non-standard grammar + ; module: - attr TOK_MODULE TOK_ID { + attr TOK_MODULE { + enterTypeScope(); + } TOK_ID { do_not_require_port_stubs = false; AstNode *mod = new AstNode(AST_MODULE); ast_stack.back()->children.push_back(mod); @@ -341,9 +384,9 @@ module: current_ast_mod = mod; port_stubs.clear(); port_counter = 0; - mod->str = *$3; + mod->str = *$4; append_attr(mod, $1); - delete $3; + delete $4; } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE { if (port_stubs.size() != 0) frontend_verilog_yyerror("Missing details for module port `%s'.", @@ -352,6 +395,7 @@ module: ast_stack.pop_back(); log_assert(ast_stack.size() == 1); current_ast_mod = NULL; + exitTypeScope(); }; module_para_opt: @@ -392,9 +436,9 @@ module_arg_opt_assignment: wire->str = ast_stack.back()->children.back()->str; if (ast_stack.back()->children.back()->is_input) { AstNode *n = ast_stack.back()->children.back(); - if (n->attributes.count("\\defaultvalue")) - delete n->attributes.at("\\defaultvalue"); - n->attributes["\\defaultvalue"] = $2; + if (n->attributes.count(ID::defaultvalue)) + delete n->attributes.at(ID::defaultvalue); + n->attributes[ID::defaultvalue] = $2; } else if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic) ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); @@ -455,16 +499,19 @@ module_arg: }; package: - attr TOK_PACKAGE TOK_ID { + attr TOK_PACKAGE { + enterTypeScope(); + } TOK_ID { AstNode *mod = new AstNode(AST_PACKAGE); ast_stack.back()->children.push_back(mod); ast_stack.push_back(mod); current_ast_mod = mod; - mod->str = *$3; + mod->str = *$4; append_attr(mod, $1); } ';' package_body TOK_ENDPACKAGE { ast_stack.pop_back(); current_ast_mod = NULL; + exitTypeScope(); }; package_body: @@ -477,7 +524,9 @@ package_body_stmt: localparam_decl; interface: - TOK_INTERFACE TOK_ID { + TOK_INTERFACE { + enterTypeScope(); + } TOK_ID { do_not_require_port_stubs = false; AstNode *intf = new AstNode(AST_INTERFACE); ast_stack.back()->children.push_back(intf); @@ -485,8 +534,8 @@ interface: current_ast_mod = intf; port_stubs.clear(); port_counter = 0; - intf->str = *$2; - delete $2; + intf->str = *$3; + delete $3; } module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE { if (port_stubs.size() != 0) frontend_verilog_yyerror("Missing details for module port `%s'.", @@ -494,6 +543,7 @@ interface: ast_stack.pop_back(); log_assert(ast_stack.size() == 1); current_ast_mod = NULL; + exitTypeScope(); }; interface_body: @@ -1461,24 +1511,24 @@ wire_name_and_opt_assign: bool attr_anyseq = false; bool attr_allconst = false; bool attr_allseq = false; - if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) { - delete ast_stack.back()->children.back()->attributes.at("\\anyconst"); - ast_stack.back()->children.back()->attributes.erase("\\anyconst"); + if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) { + delete ast_stack.back()->children.back()->attributes.at(ID::anyconst); + ast_stack.back()->children.back()->attributes.erase(ID::anyconst); attr_anyconst = true; } - if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) { - delete ast_stack.back()->children.back()->attributes.at("\\anyseq"); - ast_stack.back()->children.back()->attributes.erase("\\anyseq"); + if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) { + delete ast_stack.back()->children.back()->attributes.at(ID::anyseq); + ast_stack.back()->children.back()->attributes.erase(ID::anyseq); attr_anyseq = true; } - if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) { - delete ast_stack.back()->children.back()->attributes.at("\\allconst"); - ast_stack.back()->children.back()->attributes.erase("\\allconst"); + if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) { + delete ast_stack.back()->children.back()->attributes.at(ID::allconst); + ast_stack.back()->children.back()->attributes.erase(ID::allconst); attr_allconst = true; } - if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) { - delete ast_stack.back()->children.back()->attributes.at("\\allseq"); - ast_stack.back()->children.back()->attributes.erase("\\allseq"); + if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) { + delete ast_stack.back()->children.back()->attributes.at(ID::allseq); + ast_stack.back()->children.back()->attributes.erase(ID::allseq); attr_allseq = true; } if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) { @@ -1494,7 +1544,7 @@ wire_name_and_opt_assign: fcall->str = "\\$allconst"; if (attr_allseq) fcall->str = "\\$allseq"; - fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str)); + fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall)); } } | @@ -1502,9 +1552,9 @@ wire_name_and_opt_assign: AstNode *wire = new AstNode(AST_IDENTIFIER); wire->str = ast_stack.back()->children.back()->str; if (astbuf1->is_input) { - if (astbuf1->attributes.count("\\defaultvalue")) - delete astbuf1->attributes.at("\\defaultvalue"); - astbuf1->attributes["\\defaultvalue"] = $3; + if (astbuf1->attributes.count(ID::defaultvalue)) + delete astbuf1->attributes.at(ID::defaultvalue); + astbuf1->attributes[ID::defaultvalue] = $3; } else if (astbuf1->is_reg || astbuf1->is_logic){ AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3); @@ -1591,8 +1641,12 @@ assign_expr: ast_stack.back()->children.push_back(node); }; +type_name: TOK_ID // first time seen + | TOK_USER_TYPE { if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); } + ; + typedef_decl: - TOK_TYPEDEF wire_type range TOK_ID range_or_multirange ';' { + TOK_TYPEDEF wire_type range type_name range_or_multirange ';' { astbuf1 = $2; astbuf2 = $3; if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { @@ -1625,13 +1679,10 @@ typedef_decl: } astbuf1->children.push_back(rangeNode); } - - ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1)); - ast_stack.back()->children.back()->str = *$4; + addTypedefNode($4, astbuf1); } | - TOK_TYPEDEF enum_type TOK_ID ';' { - ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1)); - ast_stack.back()->children.back()->str = *$3; + TOK_TYPEDEF enum_type type_name ';' { + addTypedefNode($3, astbuf1); } ; @@ -1788,7 +1839,7 @@ cell_port: attr TOK_WILDCARD_CONNECT { if (!sv_mode) frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode."); - astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false); + astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false); }; always_comb_or_latch: @@ -1812,7 +1863,7 @@ always_stmt: AstNode *node = new AstNode(AST_ALWAYS); append_attr(node, $1); if ($2) - node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false); + node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false); ast_stack.back()->children.push_back(node); ast_stack.push_back(node); } always_cond { @@ -1832,9 +1883,9 @@ always_stmt: AstNode *node = new AstNode(AST_ALWAYS); append_attr(node, $1); if ($2) - node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false); + node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false); else - node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false); + node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false); ast_stack.back()->children.push_back(node); ast_stack.push_back(node); AstNode *block = new AstNode(AST_BLOCK); @@ -1955,6 +2006,7 @@ assert: delete $5; } else { AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5); + SET_AST_NODE_LOC(node, @1, @6); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -1967,6 +2019,7 @@ assert: delete $5; } else { AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5); + SET_AST_NODE_LOC(node, @1, @6); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -1979,6 +2032,7 @@ assert: delete $6; } else { AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6); + SET_AST_NODE_LOC(node, @1, @7); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -1991,6 +2045,7 @@ assert: delete $6; } else { AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6); + SET_AST_NODE_LOC(node, @1, @7); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2000,6 +2055,7 @@ assert: } | opt_sva_label TOK_COVER opt_property '(' expr ')' ';' { AstNode *node = new AstNode(AST_COVER, $5); + SET_AST_NODE_LOC(node, @1, @6); if ($1 != nullptr) { node->str = *$1; delete $1; @@ -2008,6 +2064,7 @@ assert: } | opt_sva_label TOK_COVER opt_property '(' ')' ';' { AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false)); + SET_AST_NODE_LOC(node, @1, @5); if ($1 != nullptr) { node->str = *$1; delete $1; @@ -2016,6 +2073,7 @@ assert: } | opt_sva_label TOK_COVER ';' { AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false)); + SET_AST_NODE_LOC(node, @1, @2); if ($1 != nullptr) { node->str = *$1; delete $1; @@ -2027,6 +2085,7 @@ assert: delete $5; } else { AstNode *node = new AstNode(AST_ASSUME, $5); + SET_AST_NODE_LOC(node, @1, @6); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2041,6 +2100,7 @@ assert: delete $6; } else { AstNode *node = new AstNode(AST_FAIR, $6); + SET_AST_NODE_LOC(node, @1, @7); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2053,35 +2113,45 @@ assert: assert_property: opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5)); + AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5); + SET_AST_NODE_LOC(node, @1, @6); + ast_stack.back()->children.push_back(node); if ($1 != nullptr) { ast_stack.back()->children.back()->str = *$1; delete $1; } } | opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); + AstNode *node = new AstNode(AST_ASSUME, $5); + SET_AST_NODE_LOC(node, @1, @6); + ast_stack.back()->children.push_back(node); if ($1 != nullptr) { ast_stack.back()->children.back()->str = *$1; delete $1; } } | opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6)); + AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6); + SET_AST_NODE_LOC(node, @1, @7); + ast_stack.back()->children.push_back(node); if ($1 != nullptr) { ast_stack.back()->children.back()->str = *$1; delete $1; } } | opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); + AstNode *node = new AstNode(AST_FAIR, $6); + SET_AST_NODE_LOC(node, @1, @7); + ast_stack.back()->children.push_back(node); if ($1 != nullptr) { ast_stack.back()->children.back()->str = *$1; delete $1; } } | opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5)); + AstNode *node = new AstNode(AST_COVER, $5); + SET_AST_NODE_LOC(node, @1, @6); + ast_stack.back()->children.push_back(node); if ($1 != nullptr) { ast_stack.back()->children.back()->str = *$1; delete $1; @@ -2091,7 +2161,9 @@ assert_property: if (norestrict_mode) { delete $5; } else { - ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); + AstNode *node = new AstNode(AST_ASSUME, $5); + SET_AST_NODE_LOC(node, @1, @6); + ast_stack.back()->children.push_back(node); if ($1 != nullptr) { ast_stack.back()->children.back()->str = *$1; delete $1; @@ -2102,7 +2174,9 @@ assert_property: if (norestrict_mode) { delete $6; } else { - ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); + AstNode *node = new AstNode(AST_FAIR, $6); + SET_AST_NODE_LOC(node, @1, @7); + ast_stack.back()->children.push_back(node); if ($1 != nullptr) { ast_stack.back()->children.back()->str = *$1; delete $1; @@ -2157,20 +2231,21 @@ behavioral_stmt: } opt_arg_list ';'{ ast_stack.pop_back(); } | - attr TOK_BEGIN opt_label { + attr TOK_BEGIN { + enterTypeScope(); + } opt_label { AstNode *node = new AstNode(AST_BLOCK); ast_stack.back()->children.push_back(node); ast_stack.push_back(node); append_attr(node, $1); - if ($3 != NULL) - node->str = *$3; + if ($4 != NULL) + node->str = *$4; } behavioral_stmt_list TOK_END opt_label { - if ($3 != NULL && $7 != NULL && *$3 != *$7) - frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1); - if ($3 != NULL) - delete $3; - if ($7 != NULL) - delete $7; + exitTypeScope(); + if ($4 != NULL && $8 != NULL && *$4 != *$8) + frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1); + delete $4; + delete $8; ast_stack.pop_back(); } | attr TOK_FOR '(' { @@ -2248,6 +2323,8 @@ behavioral_stmt: ast_stack.pop_back(); }; + ; + unique_case_attr: /* empty */ { $$ = false; @@ -2278,12 +2355,12 @@ case_type: opt_synopsys_attr: opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE { - if (ast_stack.back()->attributes.count("\\full_case") == 0) - ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false); + if (ast_stack.back()->attributes.count(ID::full_case) == 0) + ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false); } | opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE { - if (ast_stack.back()->attributes.count("\\parallel_case") == 0) - ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false); + if (ast_stack.back()->attributes.count(ID::parallel_case) == 0) + ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false); } | /* empty */; @@ -2445,6 +2522,7 @@ gen_stmt: } simple_behavioral_stmt ';' expr { ast_stack.back()->children.push_back($6); } ';' simple_behavioral_stmt ')' gen_stmt_block { + SET_AST_NODE_LOC(ast_stack.back(), @1, @11); ast_stack.pop_back(); } | TOK_IF '(' expr ')' { @@ -2453,6 +2531,7 @@ gen_stmt: ast_stack.push_back(node); ast_stack.back()->children.push_back($3); } gen_stmt_block opt_gen_else { + SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); } | case_type '(' expr ')' { @@ -2461,18 +2540,21 @@ gen_stmt: ast_stack.push_back(node); } gen_case_body TOK_ENDCASE { case_type_stack.pop_back(); + SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); } | - TOK_BEGIN opt_label { + TOK_BEGIN { + enterTypeScope(); + } opt_label { AstNode *node = new AstNode(AST_GENBLOCK); - node->str = $2 ? *$2 : std::string(); + node->str = $3 ? *$3 : std::string(); ast_stack.back()->children.push_back(node); ast_stack.push_back(node); } module_gen_body TOK_END opt_label { - if ($2 != NULL) - delete $2; - if ($6 != NULL) - delete $6; + exitTypeScope(); + delete $3; + delete $7; + SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); } | TOK_MSG_TASKS { @@ -2482,6 +2564,7 @@ gen_stmt: ast_stack.back()->children.push_back(node); ast_stack.push_back(node); } opt_arg_list ';'{ + SET_AST_NODE_LOC(ast_stack.back(), @1, @3); ast_stack.pop_back(); }; @@ -2491,6 +2574,7 @@ gen_stmt_block: ast_stack.back()->children.push_back(node); ast_stack.push_back(node); } gen_stmt_or_module_body_stmt { + SET_AST_NODE_LOC(ast_stack.back(), @2, @2); ast_stack.pop_back(); }; diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 02854edb2..2c82b1bca 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -268,9 +268,9 @@ Aig::Aig(Cell *cell) cell->parameters.sort(); for (auto p : cell->parameters) { - if (p.first == ID(A_WIDTH) && mkname_a_signed) { + if (p.first == ID::A_WIDTH && mkname_a_signed) { name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); - } else if (p.first == ID(B_WIDTH) && mkname_b_signed) { + } else if (p.first == ID::B_WIDTH && mkname_b_signed) { name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); } else { mkname_last = name; @@ -280,11 +280,11 @@ Aig::Aig(Cell *cell) mkname_a_signed = false; mkname_b_signed = false; mkname_is_signed = false; - if (p.first == ID(A_SIGNED)) { + if (p.first == ID::A_SIGNED) { mkname_a_signed = true; mkname_is_signed = p.second.as_bool(); } - if (p.first == ID(B_SIGNED)) { + if (p.first == ID::B_SIGNED) { mkname_b_signed = true; mkname_is_signed = p.second.as_bool(); } @@ -320,7 +320,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($mux), ID($_MUX_))) { - int S = mk.inport(ID(S)); + int S = mk.inport(ID::S); for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { int A = mk.inport(ID::A, i); int B = mk.inport(ID::B, i); @@ -390,8 +390,8 @@ Aig::Aig(Cell *cell) int width = GetSize(cell->getPort(ID::Y)); vector<int> A = mk.inport_vec(ID::A, width); vector<int> B = mk.inport_vec(ID::B, width); - int carry = mk.inport(ID(CI)); - int binv = mk.inport(ID(BI)); + int carry = mk.inport(ID::CI); + int binv = mk.inport(ID::BI); for (auto &n : B) n = mk.xor_gate(n, binv); vector<int> X(width), CO(width); @@ -399,8 +399,8 @@ Aig::Aig(Cell *cell) for (int i = 0; i < width; i++) X[i] = mk.xor_gate(A[i], B[i]); mk.outport_vec(Y, ID::Y); - mk.outport_vec(X, ID(X)); - mk.outport_vec(CO, ID(CO)); + mk.outport_vec(X, ID::X); + mk.outport_vec(CO, ID::CO); goto optimize; } @@ -422,7 +422,7 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); + int C = mk.inport(ID::C); int Y = mk.nor_gate(mk.and_gate(A, B), C); mk.outport(Y, ID::Y); goto optimize; @@ -432,7 +432,7 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); + int C = mk.inport(ID::C); int Y = mk.nand_gate(mk.or_gate(A, B), C); mk.outport(Y, ID::Y); goto optimize; @@ -442,8 +442,8 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); - int D = mk.inport(ID(D)); + int C = mk.inport(ID::C); + int D = mk.inport(ID::D); int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D)); mk.outport(Y, ID::Y); goto optimize; @@ -453,8 +453,8 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); - int D = mk.inport(ID(D)); + int C = mk.inport(ID::C); + int D = mk.inport(ID::D); int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); mk.outport(Y, ID::Y); goto optimize; diff --git a/kernel/celledges.cc b/kernel/celledges.cc index d0bb99e83..54e0168e2 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -24,29 +24,25 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int y_width = GetSize(cell->getPort(ID::Y)); for (int i = 0; i < y_width; i++) { if (i < a_width) - db->add_edge(cell, A, i, Y, i, -1); + db->add_edge(cell, ID::A, i, ID::Y, i, -1); else if (is_signed && a_width > 0) - db->add_edge(cell, A, a_width-1, Y, i, -1); + db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1); } } void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int y_width = GetSize(cell->getPort(ID::Y)); if (cell->type == ID($and) && !is_signed) { if (a_width > b_width) @@ -58,41 +54,37 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < y_width; i++) { if (i < a_width) - db->add_edge(cell, A, i, Y, i, -1); + db->add_edge(cell, ID::A, i, ID::Y, i, -1); else if (is_signed && a_width > 0) - db->add_edge(cell, A, a_width-1, Y, i, -1); + db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1); if (i < b_width) - db->add_edge(cell, B, i, Y, i, -1); + db->add_edge(cell, ID::B, i, ID::Y, i, -1); else if (is_signed && b_width > 0) - db->add_edge(cell, B, b_width-1, Y, i, -1); + db->add_edge(cell, ID::B, b_width-1, ID::Y, i, -1); } } void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int y_width = GetSize(cell->getPort(ID::Y)); if (is_signed && a_width == 1) y_width = std::min(y_width, 1); for (int i = 0; i < y_width; i++) for (int k = 0; k <= i && k < a_width; k++) - db->add_edge(cell, A, k, Y, i, -1); + db->add_edge(cell, ID::A, k, ID::Y, i, -1); } void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int y_width = GetSize(cell->getPort(ID::Y)); if (!is_signed && cell->type != ID($sub)) { int ab_width = std::max(a_width, b_width); @@ -104,55 +96,49 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int k = 0; k <= i; k++) { if (k < a_width) - db->add_edge(cell, A, k, Y, i, -1); + db->add_edge(cell, ID::A, k, ID::Y, i, -1); if (k < b_width) - db->add_edge(cell, B, k, Y, i, -1); + db->add_edge(cell, ID::B, k, ID::Y, i, -1); } } } void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, Y = ID::Y; - - int a_width = GetSize(cell->getPort(A)); + int a_width = GetSize(cell->getPort(ID::A)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, A, i, Y, 0, -1); + db->add_edge(cell, ID::A, i, ID::Y, 0, -1); } void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, Y = ID::Y; - - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, A, i, Y, 0, -1); + db->add_edge(cell, ID::A, i, ID::Y, 0, -1); for (int i = 0; i < b_width; i++) - db->add_edge(cell, B, i, Y, 0, -1); + db->add_edge(cell, ID::B, i, ID::Y, 0, -1); } void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; - - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); - int s_width = GetSize(cell->getPort(S)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int s_width = GetSize(cell->getPort(ID::S)); for (int i = 0; i < a_width; i++) { - db->add_edge(cell, A, i, Y, i, -1); + db->add_edge(cell, ID::A, i, ID::Y, i, -1); for (int k = i; k < b_width; k += a_width) - db->add_edge(cell, B, k, Y, i, -1); + db->add_edge(cell, ID::B, k, ID::Y, i, -1); for (int k = 0; k < s_width; k++) - db->add_edge(cell, S, k, Y, i, -1); + db->add_edge(cell, ID::S, k, ID::Y, i, -1); } } diff --git a/kernel/celltypes.h b/kernel/celltypes.h index bc96fd602..450865ce9 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -84,26 +84,22 @@ struct CellTypes { setup_internals_eval(); - IdString A = ID::A, B = ID::B, EN = ID(EN), Y = ID::Y; - IdString SRC = ID(SRC), DST = ID(DST), DAT = ID(DAT); - IdString EN_SRC = ID(EN_SRC), EN_DST = ID(EN_DST); - - setup_type(ID($tribuf), {A, EN}, {Y}, true); - - setup_type(ID($assert), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($assume), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($live), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($fair), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($cover), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($initstate), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($anyconst), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($anyseq), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($allconst), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($allseq), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($equiv), {A, B}, {Y}, true); - setup_type(ID($specify2), {EN, SRC, DST}, pool<RTLIL::IdString>(), true); - setup_type(ID($specify3), {EN, SRC, DST, DAT}, pool<RTLIL::IdString>(), true); - setup_type(ID($specrule), {EN_SRC, EN_DST, SRC, DST}, pool<RTLIL::IdString>(), true); + setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true); + + setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true); + setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true); + setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true); } void setup_internals_eval() @@ -121,134 +117,109 @@ struct CellTypes ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($logic_and), ID($logic_or), ID($concat), ID($macc) }; - IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; - IdString P = ID(P), G = ID(G), C = ID(C), X = ID(X); - IdString BI = ID(BI), CI = ID(CI), CO = ID(CO), EN = ID(EN); for (auto type : unary_ops) - setup_type(type, {A}, {Y}, true); + setup_type(type, {ID::A}, {ID::Y}, true); for (auto type : binary_ops) - setup_type(type, {A, B}, {Y}, true); + setup_type(type, {ID::A, ID::B}, {ID::Y}, true); for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)})) - setup_type(type, {A, B, S}, {Y}, true); + setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true); - setup_type(ID($lcu), {P, G, CI}, {CO}, true); - setup_type(ID($alu), {A, B, CI, BI}, {X, Y, CO}, true); - setup_type(ID($fa), {A, B, C}, {X, Y}, true); + setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true); + setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true); + setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true); } void setup_internals_ff() { - IdString SET = ID(SET), CLR = ID(CLR), CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); - IdString Q = ID(Q), D = ID(D); - - setup_type(ID($sr), {SET, CLR}, {Q}); - setup_type(ID($ff), {D}, {Q}); - setup_type(ID($dff), {CLK, D}, {Q}); - setup_type(ID($dffe), {CLK, EN, D}, {Q}); - setup_type(ID($dffsr), {CLK, SET, CLR, D}, {Q}); - setup_type(ID($adff), {CLK, ARST, D}, {Q}); - setup_type(ID($dlatch), {EN, D}, {Q}); - setup_type(ID($dlatchsr), {EN, SET, CLR, D}, {Q}); - + setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q}); + setup_type(ID($ff), {ID::D}, {ID::Q}); + setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q}); + setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q}); + setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q}); + setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q}); + setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q}); + setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q}); } void setup_internals_mem() { setup_internals_ff(); - IdString CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); - IdString ADDR = ID(ADDR), DATA = ID(DATA), RD_EN = ID(RD_EN); - IdString RD_CLK = ID(RD_CLK), RD_ADDR = ID(RD_ADDR), WR_CLK = ID(WR_CLK), WR_EN = ID(WR_EN); - IdString WR_ADDR = ID(WR_ADDR), WR_DATA = ID(WR_DATA), RD_DATA = ID(RD_DATA); - IdString CTRL_IN = ID(CTRL_IN), CTRL_OUT = ID(CTRL_OUT); - - setup_type(ID($memrd), {CLK, EN, ADDR}, {DATA}); - setup_type(ID($memwr), {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>()); - setup_type(ID($meminit), {ADDR, DATA}, pool<RTLIL::IdString>()); - setup_type(ID($mem), {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA}); + setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA}); + setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>()); + setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>()); + setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}); - setup_type(ID($fsm), {CLK, ARST, CTRL_IN}, {CTRL_OUT}); + setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT}); } void setup_stdcells() { setup_stdcells_eval(); - IdString A = ID::A, E = ID(E), Y = ID::Y; - - setup_type(ID($_TBUF_), {A, E}, {Y}, true); + setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true); } void setup_stdcells_eval() { - IdString A = ID::A, B = ID::B, C = ID(C), D = ID(D); - IdString E = ID(E), F = ID(F), G = ID(G), H = ID(H); - IdString I = ID(I), J = ID(J), K = ID(K), L = ID(L); - IdString M = ID(M), N = ID(N), O = ID(O), P = ID(P); - IdString S = ID(S), T = ID(T), U = ID(U), V = ID(V); - IdString Y = ID::Y; - - setup_type(ID($_BUF_), {A}, {Y}, true); - setup_type(ID($_NOT_), {A}, {Y}, true); - setup_type(ID($_AND_), {A, B}, {Y}, true); - setup_type(ID($_NAND_), {A, B}, {Y}, true); - setup_type(ID($_OR_), {A, B}, {Y}, true); - setup_type(ID($_NOR_), {A, B}, {Y}, true); - setup_type(ID($_XOR_), {A, B}, {Y}, true); - setup_type(ID($_XNOR_), {A, B}, {Y}, true); - setup_type(ID($_ANDNOT_), {A, B}, {Y}, true); - setup_type(ID($_ORNOT_), {A, B}, {Y}, true); - setup_type(ID($_MUX_), {A, B, S}, {Y}, true); - setup_type(ID($_NMUX_), {A, B, S}, {Y}, true); - setup_type(ID($_MUX4_), {A, B, C, D, S, T}, {Y}, true); - setup_type(ID($_MUX8_), {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true); - setup_type(ID($_MUX16_), {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true); - setup_type(ID($_AOI3_), {A, B, C}, {Y}, true); - setup_type(ID($_OAI3_), {A, B, C}, {Y}, true); - setup_type(ID($_AOI4_), {A, B, C, D}, {Y}, true); - setup_type(ID($_OAI4_), {A, B, C, D}, {Y}, true); + setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true); + setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true); + setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true); + setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true); + setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true); + setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true); + setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true); + setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true); + setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true); + setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true); + setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true); } void setup_stdcells_mem() { - IdString S = ID(S), R = ID(R), C = ID(C); - IdString D = ID(D), Q = ID(Q), E = ID(E); - std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'}; for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q}); + setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q}); - setup_type(ID($_FF_), {D}, {Q}); + setup_type(ID($_FF_), {ID::D}, {ID::Q}); for (auto c1 : list_np) - setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q}); + setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q}); + setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) - setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q}); + setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q}); + setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}); for (auto c1 : list_np) - setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q}); + setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q}); + setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}); } void clear() @@ -300,7 +271,7 @@ struct CellTypes signed1 = false, signed2 = false; } -#define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len); +#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len); HANDLE_CELL_TYPE(not) HANDLE_CELL_TYPE(and) HANDLE_CELL_TYPE(or) @@ -371,8 +342,8 @@ struct CellTypes { if (cell->type == ID($slice)) { RTLIL::Const ret; - int width = cell->parameters.at(ID(Y_WIDTH)).as_int(); - int offset = cell->parameters.at(ID(OFFSET)).as_int(); + int width = cell->parameters.at(ID::Y_WIDTH).as_int(); + int offset = cell->parameters.at(ID::OFFSET).as_int(); ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width); return ret; } @@ -385,9 +356,9 @@ struct CellTypes if (cell->type == ID($lut)) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); + int width = cell->parameters.at(ID::WIDTH).as_int(); - std::vector<RTLIL::State> t = cell->parameters.at(ID(LUT)).bits; + std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits; while (GetSize(t) < (1 << width)) t.push_back(State::S0); t.resize(1 << width); @@ -411,9 +382,9 @@ struct CellTypes if (cell->type == ID($sop)) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - int depth = cell->parameters.at(ID(DEPTH)).as_int(); - std::vector<RTLIL::State> t = cell->parameters.at(ID(TABLE)).bits; + int width = cell->parameters.at(ID::WIDTH).as_int(); + int depth = cell->parameters.at(ID::DEPTH).as_int(); + std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits; while (GetSize(t) < width*depth*2) t.push_back(State::S0); @@ -447,9 +418,9 @@ struct CellTypes return default_ret; } - bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); - bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); - int result_len = cell->parameters.count(ID(Y_WIDTH)) > 0 ? cell->parameters[ID(Y_WIDTH)].as_int() : -1; + bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool(); + bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool(); + int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1; return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp); } diff --git a/kernel/consteval.h b/kernel/consteval.h index 7a83d28e7..ff8cf86d6 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -91,10 +91,10 @@ struct ConstEval { if (cell->type == ID($lcu)) { - RTLIL::SigSpec sig_p = cell->getPort(ID(P)); - RTLIL::SigSpec sig_g = cell->getPort(ID(G)); - RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); - RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID(CO)))); + RTLIL::SigSpec sig_p = cell->getPort(ID::P); + RTLIL::SigSpec sig_g = cell->getPort(ID::G); + RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); + RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO))); if (sig_co.is_fully_const()) return true; @@ -133,8 +133,8 @@ struct ConstEval if (sig_y.is_fully_const()) return true; - if (cell->hasPort(ID(S))) { - sig_s = cell->getPort(ID(S)); + if (cell->hasPort(ID::S)) { + sig_s = cell->getPort(ID::S); if (!eval(sig_s, undef, cell)) return false; } @@ -200,8 +200,8 @@ struct ConstEval } else if (cell->type == ID($fa)) { - RTLIL::SigSpec sig_c = cell->getPort(ID(C)); - RTLIL::SigSpec sig_x = cell->getPort(ID(X)); + RTLIL::SigSpec sig_c = cell->getPort(ID::C); + RTLIL::SigSpec sig_x = cell->getPort(ID::X); int width = GetSize(sig_c); if (!eval(sig_a, undef, cell)) @@ -229,11 +229,11 @@ struct ConstEval } else if (cell->type == ID($alu)) { - bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); - bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); + bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool(); + bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool(); - RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); - RTLIL::SigSpec sig_bi = cell->getPort(ID(BI)); + RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); + RTLIL::SigSpec sig_bi = cell->getPort(ID::BI); if (!eval(sig_a, undef, cell)) return false; @@ -247,8 +247,8 @@ struct ConstEval if (!eval(sig_bi, undef, cell)) return false; - RTLIL::SigSpec sig_x = cell->getPort(ID(X)); - RTLIL::SigSpec sig_co = cell->getPort(ID(CO)); + RTLIL::SigSpec sig_x = cell->getPort(ID::X); + RTLIL::SigSpec sig_co = cell->getPort(ID::CO); bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); sig_a.extend_u0(GetSize(sig_y), signed_a); @@ -309,10 +309,10 @@ struct ConstEval RTLIL::SigSpec sig_c, sig_d; if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { - if (cell->hasPort(ID(C))) - sig_c = cell->getPort(ID(C)); - if (cell->hasPort(ID(D))) - sig_d = cell->getPort(ID(D)); + if (cell->hasPort(ID::C)) + sig_c = cell->getPort(ID::C); + if (cell->hasPort(ID::D)) + sig_d = cell->getPort(ID::D); } if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) diff --git a/kernel/constids.inc b/kernel/constids.inc new file mode 100644 index 000000000..68a5782fd --- /dev/null +++ b/kernel/constids.inc @@ -0,0 +1,213 @@ +X(A) +X(abc9_box) +X(abc9_box_id) +X(abc9_box_seq) +X(abc9_carry) +X(abc9_flop) +X(abc9_holes) +X(abc9_init) +X(abc9_lut) +X(abc9_mergeability) +X(abc9_scc) +X(abc9_scc_id) +X(abcgroup) +X(ABITS) +X(ADDR) +X(allconst) +X(allseq) +X(always_comb) +X(always_ff) +X(always_latch) +X(anyconst) +X(anyseq) +X(ARST) +X(ARST_POLARITY) +X(ARST_VALUE) +X(A_SIGNED) +X(A_WIDTH) +X(B) +X(BI) +X(blackbox) +X(B_SIGNED) +X(B_WIDTH) +X(C) +X(cells_not_processed) +X(CFG_ABITS) +X(CFG_DBITS) +X(CFG_INIT) +X(CI) +X(CLK) +X(clkbuf_driver) +X(clkbuf_inhibit) +X(clkbuf_inv) +X(clkbuf_sink) +X(CLK_ENABLE) +X(CLK_POLARITY) +X(CLR) +X(CLR_POLARITY) +X(CO) +X(CONFIG) +X(CONFIG_WIDTH) +X(CTRL_IN) +X(CTRL_IN_WIDTH) +X(CTRL_OUT) +X(CTRL_OUT_WIDTH) +X(D) +X(DAT) +X(DATA) +X(DAT_DST_PEN) +X(DAT_DST_POL) +X(defaultvalue) +X(DELAY) +X(DEPTH) +X(DST) +X(DST_EN) +X(DST_PEN) +X(DST_POL) +X(DST_WIDTH) +X(dynports) +X(E) +X(EDGE_EN) +X(EDGE_POL) +X(EN) +X(EN_DST) +X(EN_POLARITY) +X(EN_SRC) +X(equiv_merged) +X(equiv_region) +X(extract_order) +X(F) +X(fsm_encoding) +X(fsm_export) +X(FULL) +X(full_case) +X(G) +X(gclk) +X(gentb_clock) +X(gentb_constant) +X(gentb_skip) +X(H) +X(hdlname) +X(hierconn) +X(I) +X(INIT) +X(init) +X(initial_top) +X(interface_modport) +X(interfaces_replaced_in_module) +X(interface_type) +X(invertible_pin) +X(iopad_external_pin) +X(is_interface) +X(J) +X(K) +X(keep) +X(keep_hierarchy) +X(L) +X(lib_whitebox) +X(localparam) +X(LUT) +X(lut_keep) +X(M) +X(maximize) +X(mem2reg) +X(MEMID) +X(minimize) +X(module_not_derived) +X(N) +X(NAME) +X(noblackbox) +X(nolatches) +X(nomem2init) +X(nomem2reg) +X(nomeminit) +X(nosync) +X(O) +X(OFFSET) +X(onehot) +X(P) +X(parallel_case) +X(parameter) +X(PRIORITY) +X(Q) +X(qwp_position) +X(R) +X(RD_ADDR) +X(RD_CLK) +X(RD_CLK_ENABLE) +X(RD_CLK_POLARITY) +X(RD_DATA) +X(RD_EN) +X(RD_PORTS) +X(RD_TRANSPARENT) +X(reg) +X(S) +X(SET) +X(SET_POLARITY) +X(SIZE) +X(SRC) +X(src) +X(SRC_DST_PEN) +X(SRC_DST_POL) +X(SRC_EN) +X(SRC_PEN) +X(SRC_POL) +X(SRC_WIDTH) +X(STATE_BITS) +X(STATE_NUM) +X(STATE_NUM_LOG2) +X(STATE_RST) +X(STATE_TABLE) +X(submod) +X(S_WIDTH) +X(T) +X(TABLE) +X(techmap_autopurge) +X(_TECHMAP_BITS_CONNMAP_) +X(_TECHMAP_CELLTYPE_) +X(techmap_celltype) +X(techmap_maccmap) +X(_TECHMAP_REPLACE_) +X(techmap_simplemap) +X(_techmap_special_) +X(techmap_wrap) +X(T_FALL_MAX) +X(T_FALL_MIN) +X(T_FALL_TYP) +X(T_LIMIT) +X(T_LIMIT2) +X(T_LIMIT2_MAX) +X(T_LIMIT2_MIN) +X(T_LIMIT2_TYP) +X(T_LIMIT_MAX) +X(T_LIMIT_MIN) +X(T_LIMIT_TYP) +X(to_delete) +X(top) +X(TRANS_NUM) +X(TRANSPARENT) +X(TRANS_TABLE) +X(T_RISE_MAX) +X(T_RISE_MIN) +X(T_RISE_TYP) +X(TYPE) +X(U) +X(unique) +X(unused_bits) +X(V) +X(wand) +X(whitebox) +X(WIDTH) +X(wildcard_port_conns) +X(wor) +X(WORDS) +X(WR_ADDR) +X(WR_CLK) +X(WR_CLK_ENABLE) +X(WR_CLK_POLARITY) +X(WR_DATA) +X(WR_EN) +X(WR_PORTS) +X(X) +X(Y) +X(Y_WIDTH) diff --git a/kernel/macc.h b/kernel/macc.h index 371f6737d..e9f6f05e9 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -104,11 +104,11 @@ struct Macc ports.clear(); bit_ports = cell->getPort(ID::B); - std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits; + std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits; int config_cursor = 0; #ifndef NDEBUG - int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int(); + int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int(); log_assert(GetSize(config_bits) >= config_width); #endif @@ -193,10 +193,10 @@ struct Macc cell->setPort(ID::A, port_a); cell->setPort(ID::B, bit_ports); - cell->setParam(ID(CONFIG), config_bits); - cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); - cell->setParam(ID(A_WIDTH), GetSize(port_a)); - cell->setParam(ID(B_WIDTH), GetSize(bit_ports)); + cell->setParam(ID::CONFIG, config_bits); + cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits)); + cell->setParam(ID::A_WIDTH, GetSize(port_a)); + cell->setParam(ID::B_WIDTH, GetSize(bit_ports)); } bool eval(RTLIL::Const &result) const diff --git a/kernel/modtools.h b/kernel/modtools.h index 409562eb9..fbc5482ee 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor #endif } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE { log_assert(module == cell->module); @@ -380,22 +380,15 @@ struct ModWalker } } - ModWalker() : design(NULL), module(NULL) + ModWalker(RTLIL::Design *design) : design(design), module(NULL) { + ct.setup(design); } - ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) + void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL) { - setup(design, module, filter_ct); - } - - void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) - { - this->design = design; this->module = module; - ct.clear(); - ct.setup(design); sigmap.set(module); signal_drivers.clear(); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 06181b763..00c116115 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -21,6 +21,7 @@ #include "kernel/macc.h" #include "kernel/celltypes.h" #include "frontends/verilog/verilog_frontend.h" +#include "frontends/verilog/preproc.h" #include "backends/ilang/ilang_backend.h" #include <string.h> @@ -40,12 +41,10 @@ int RTLIL::IdString::last_created_idx_[8]; int RTLIL::IdString::last_created_idx_ptr_; #endif -IdString RTLIL::ID::A; -IdString RTLIL::ID::B; -IdString RTLIL::ID::Y; -IdString RTLIL::ID::keep; -IdString RTLIL::ID::whitebox; -IdString RTLIL::ID::blackbox; +#define X(_id) IdString RTLIL::ID::_id; +#include "constids.inc" +#undef X + dict<std::string, std::string> RTLIL::constpad; RTLIL::Const::Const() @@ -84,14 +83,14 @@ RTLIL::Const::Const(RTLIL::State bit, int width) RTLIL::Const::Const(const std::vector<bool> &bits) { flags = RTLIL::CONST_FLAG_NONE; - for (auto b : bits) - this->bits.push_back(b ? State::S1 : State::S0); + for (const auto &b : bits) + this->bits.emplace_back(b ? State::S1 : State::S0); } RTLIL::Const::Const(const RTLIL::Const &c) { flags = c.flags; - for (auto b : c.bits) + for (const auto &b : c.bits) this->bits.push_back(b); } @@ -138,6 +137,7 @@ int RTLIL::Const::as_int(bool is_signed) const std::string RTLIL::Const::as_string() const { std::string ret; + ret.reserve(bits.size()); for (size_t i = bits.size(); i > 0; i--) switch (bits[i-1]) { case S0: ret += "0"; break; @@ -150,9 +150,10 @@ std::string RTLIL::Const::as_string() const return ret; } -RTLIL::Const RTLIL::Const::from_string(std::string str) +RTLIL::Const RTLIL::Const::from_string(const std::string &str) { Const c; + c.bits.reserve(str.size()); for (auto it = str.rbegin(); it != str.rend(); it++) switch (*it) { case '0': c.bits.push_back(State::S0); break; @@ -168,17 +169,16 @@ RTLIL::Const RTLIL::Const::from_string(std::string str) std::string RTLIL::Const::decode_string() const { std::string string; - std::vector<char> string_chars; - for (int i = 0; i < int (bits.size()); i += 8) { + string.reserve(GetSize(bits)/8); + for (int i = 0; i < GetSize(bits); i += 8) { char ch = 0; for (int j = 0; j < 8 && i + j < int (bits.size()); j++) if (bits[i + j] == RTLIL::State::S1) ch |= 1 << j; if (ch != 0) - string_chars.push_back(ch); + string.append({ch}); } - for (int i = int (string_chars.size()) - 1; i >= 0; i--) - string += string_chars[i]; + std::reverse(string.begin(), string.end()); return string; } @@ -186,7 +186,7 @@ bool RTLIL::Const::is_fully_zero() const { cover("kernel.rtlil.const.is_fully_zero"); - for (auto bit : bits) + for (const auto &bit : bits) if (bit != RTLIL::State::S0) return false; @@ -197,7 +197,7 @@ bool RTLIL::Const::is_fully_ones() const { cover("kernel.rtlil.const.is_fully_ones"); - for (auto bit : bits) + for (const auto &bit : bits) if (bit != RTLIL::State::S1) return false; @@ -208,7 +208,7 @@ bool RTLIL::Const::is_fully_def() const { cover("kernel.rtlil.const.is_fully_def"); - for (auto bit : bits) + for (const auto &bit : bits) if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1) return false; @@ -219,7 +219,7 @@ bool RTLIL::Const::is_fully_undef() const { cover("kernel.rtlil.const.is_fully_undef"); - for (auto bit : bits) + for (const auto &bit : bits) if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz) return false; @@ -230,11 +230,8 @@ void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value) { if (value) attributes[id] = RTLIL::Const(1); - else { - const auto it = attributes.find(id); - if (it != attributes.end()) - attributes.erase(it); - } + else + attributes.erase(id); } bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const @@ -248,7 +245,7 @@ bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data) { string attrval; - for (auto &s : data) { + for (const auto &s : data) { if (!attrval.empty()) attrval += "|"; attrval += s; @@ -276,16 +273,17 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const void RTLIL::AttrObject::set_src_attribute(const std::string &src) { if (src.empty()) - attributes.erase(ID(src)); + attributes.erase(ID::src); else - attributes[ID(src)] = src; + attributes[ID::src] = src; } std::string RTLIL::AttrObject::get_src_attribute() const { std::string src; - if (attributes.count(ID(src))) - src = attributes.at(ID(src)).decode_string(); + const auto it = attributes.find(ID::src); + if (it != attributes.end()) + src = it->second.decode_string(); return src; } @@ -379,6 +377,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) } RTLIL::Design::Design() + : verilog_defines (new define_map_t) { static unsigned int hashidx_count = 123456789; hashidx_count = mkhash_xorshift(hashidx_count); @@ -429,7 +428,7 @@ RTLIL::Module *RTLIL::Design::top_module() int module_count = 0; for (auto mod : selected_modules()) { - if (mod->get_bool_attribute(ID(top))) + if (mod->get_bool_attribute(ID::top)) return mod; module_count++; module = mod; @@ -475,32 +474,33 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) return module; } -void RTLIL::Design::scratchpad_unset(std::string varname) +void RTLIL::Design::scratchpad_unset(const std::string &varname) { scratchpad.erase(varname); } -void RTLIL::Design::scratchpad_set_int(std::string varname, int value) +void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value) { scratchpad[varname] = stringf("%d", value); } -void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value) +void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value) { scratchpad[varname] = value ? "true" : "false"; } -void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value) +void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value) { - scratchpad[varname] = value; + scratchpad[varname] = std::move(value); } -int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const +int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const { - if (scratchpad.count(varname) == 0) + auto it = scratchpad.find(varname); + if (it == scratchpad.end()) return default_value; - std::string str = scratchpad.at(varname); + const std::string &str = it->second; if (str == "0" || str == "false") return 0; @@ -513,12 +513,13 @@ int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) co return *endptr ? default_value : parsed_value; } -bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const +bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const { - if (scratchpad.count(varname) == 0) + auto it = scratchpad.find(varname); + if (it == scratchpad.end()) return default_value; - std::string str = scratchpad.at(varname); + const std::string &str = it->second; if (str == "0" || str == "false") return false; @@ -529,11 +530,13 @@ bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) return default_value; } -std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const +std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const { - if (scratchpad.count(varname) == 0) + auto it = scratchpad.find(varname); + if (it == scratchpad.end()) return default_value; - return scratchpad.at(varname); + + return it->second; } void RTLIL::Design::remove(RTLIL::Module *module) @@ -721,12 +724,12 @@ void RTLIL::Module::makeblackbox() set_bool_attribute(ID::blackbox); } -void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>) +void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &) { log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); } -RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail) { if (mayfail) return RTLIL::IdString(); @@ -734,7 +737,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLI } -RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail) { if (mayfail) return RTLIL::IdString(); @@ -768,16 +771,17 @@ namespace { int param(RTLIL::IdString name) { - if (cell->parameters.count(name) == 0) + auto it = cell->parameters.find(name); + if (it == cell->parameters.end()) error(__LINE__); expected_params.insert(name); - return cell->parameters.at(name).as_int(); + return it->second.as_int(); } int param_bool(RTLIL::IdString name) { int v = param(name); - if (cell->parameters.at(name).bits.size() > 32) + if (GetSize(cell->parameters.at(name)) > 32) error(__LINE__); if (v != 0 && v != 1) error(__LINE__); @@ -795,20 +799,21 @@ namespace { void param_bits(RTLIL::IdString name, int width) { param(name); - if (int(cell->parameters.at(name).bits.size()) != width) + if (GetSize(cell->parameters.at(name).bits) != width) error(__LINE__); } void port(RTLIL::IdString name, int width) { - if (!cell->hasPort(name)) + auto it = cell->connections_.find(name); + if (it == cell->connections_.end()) error(__LINE__); - if (cell->getPort(name).size() != width) + if (GetSize(it->second) != width) error(__LINE__); expected_ports.insert(name); } - void check_expected(bool check_matched_sign = true) + void check_expected(bool check_matched_sign = false) { for (auto ¶ : cell->parameters) if (expected_params.count(para.first) == 0) @@ -817,35 +822,15 @@ namespace { if (expected_ports.count(conn.first) == 0) error(__LINE__); - if (expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) && check_matched_sign) { - bool a_is_signed = param(ID(A_SIGNED)) != 0; - bool b_is_signed = param(ID(B_SIGNED)) != 0; + if (check_matched_sign) { + log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0); + bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); + bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool(); if (a_is_signed != b_is_signed) error(__LINE__); } } - void check_gate(const char *ports) - { - if (cell->parameters.size() != 0) - error(__LINE__); - - for (const char *p = ports; *p; p++) { - char portname[3] = { '\\', *p, 0 }; - if (!cell->hasPort(portname)) - error(__LINE__); - if (cell->getPort(portname).size() != 1) - error(__LINE__); - } - - for (auto &conn : cell->connections()) { - if (conn.first.size() != 2 || conn.first[0] != '\\') - error(__LINE__); - if (strchr(ports, conn.first[1]) == NULL) - error(__LINE__); - } - } - void check() { if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") || @@ -853,357 +838,357 @@ namespace { return; if (cell->type.in(ID($not), ID($pos), ID($neg))) { - param_bool(ID(A_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); return; } if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); - check_expected(); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); + check_expected(true); return; } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { - param_bool(ID(A_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); return; } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED), /*expected=*/false); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED, /*expected=*/false); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } if (cell->type.in(ID($shift), ID($shiftx))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); - check_expected(); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); + check_expected(true); return; } if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(cell->type != ID($pow)); return; } if (cell->type == ID($fa)) { - port(ID::A, param(ID(WIDTH))); - port(ID::B, param(ID(WIDTH))); - port(ID(C), param(ID(WIDTH))); - port(ID(X), param(ID(WIDTH))); - port(ID::Y, param(ID(WIDTH))); + port(ID::A, param(ID::WIDTH)); + port(ID::B, param(ID::WIDTH)); + port(ID::C, param(ID::WIDTH)); + port(ID::X, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($lcu)) { - port(ID(P), param(ID(WIDTH))); - port(ID(G), param(ID(WIDTH))); - port(ID(CI), 1); - port(ID(CO), param(ID(WIDTH))); + port(ID::P, param(ID::WIDTH)); + port(ID::G, param(ID::WIDTH)); + port(ID::CI, 1); + port(ID::CO, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($alu)) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID(CI), 1); - port(ID(BI), 1); - port(ID(X), param(ID(Y_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); - port(ID(CO), param(ID(Y_WIDTH))); - check_expected(); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::CI, 1); + port(ID::BI, 1); + port(ID::X, param(ID::Y_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); + port(ID::CO, param(ID::Y_WIDTH)); + check_expected(true); return; } if (cell->type == ID($macc)) { - param(ID(CONFIG)); - param(ID(CONFIG_WIDTH)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param(ID::CONFIG); + param(ID::CONFIG_WIDTH); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); Macc().from_cell(cell); return; } if (cell->type == ID($logic_not)) { - param_bool(ID(A_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); return; } if (cell->type.in(ID($logic_and), ID($logic_or))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } if (cell->type == ID($slice)) { - param(ID(OFFSET)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); - if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH))) + param(ID::OFFSET); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); + if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH)) error(__LINE__); check_expected(); return; } if (cell->type == ID($concat)) { - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH))); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH)); check_expected(); return; } if (cell->type == ID($mux)) { - port(ID::A, param(ID(WIDTH))); - port(ID::B, param(ID(WIDTH))); - port(ID(S), 1); - port(ID::Y, param(ID(WIDTH))); + port(ID::A, param(ID::WIDTH)); + port(ID::B, param(ID::WIDTH)); + port(ID::S, 1); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($pmux)) { - port(ID::A, param(ID(WIDTH))); - port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH))); - port(ID(S), param(ID(S_WIDTH))); - port(ID::Y, param(ID(WIDTH))); + port(ID::A, param(ID::WIDTH)); + port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH)); + port(ID::S, param(ID::S_WIDTH)); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($lut)) { - param(ID(LUT)); - port(ID::A, param(ID(WIDTH))); + param(ID::LUT); + port(ID::A, param(ID::WIDTH)); port(ID::Y, 1); check_expected(); return; } if (cell->type == ID($sop)) { - param(ID(DEPTH)); - param(ID(TABLE)); - port(ID::A, param(ID(WIDTH))); + param(ID::DEPTH); + param(ID::TABLE); + port(ID::A, param(ID::WIDTH)); port(ID::Y, 1); check_expected(); return; } if (cell->type == ID($sr)) { - param_bool(ID(SET_POLARITY)); - param_bool(ID(CLR_POLARITY)); - port(ID(SET), param(ID(WIDTH))); - port(ID(CLR), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::SET_POLARITY); + param_bool(ID::CLR_POLARITY); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($ff)) { - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dff)) { - param_bool(ID(CLK_POLARITY)); - port(ID(CLK), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + port(ID::CLK, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dffe)) { - param_bool(ID(CLK_POLARITY)); - param_bool(ID(EN_POLARITY)); - port(ID(CLK), 1); - port(ID(EN), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + param_bool(ID::EN_POLARITY); + port(ID::CLK, 1); + port(ID::EN, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dffsr)) { - param_bool(ID(CLK_POLARITY)); - param_bool(ID(SET_POLARITY)); - param_bool(ID(CLR_POLARITY)); - port(ID(CLK), 1); - port(ID(SET), param(ID(WIDTH))); - port(ID(CLR), param(ID(WIDTH))); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + param_bool(ID::SET_POLARITY); + param_bool(ID::CLR_POLARITY); + port(ID::CLK, 1); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($adff)) { - param_bool(ID(CLK_POLARITY)); - param_bool(ID(ARST_POLARITY)); - param_bits(ID(ARST_VALUE), param(ID(WIDTH))); - port(ID(CLK), 1); - port(ID(ARST), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + param_bool(ID::ARST_POLARITY); + param_bits(ID::ARST_VALUE, param(ID::WIDTH)); + port(ID::CLK, 1); + port(ID::ARST, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dlatch)) { - param_bool(ID(EN_POLARITY)); - port(ID(EN), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::EN_POLARITY); + port(ID::EN, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dlatchsr)) { - param_bool(ID(EN_POLARITY)); - param_bool(ID(SET_POLARITY)); - param_bool(ID(CLR_POLARITY)); - port(ID(EN), 1); - port(ID(SET), param(ID(WIDTH))); - port(ID(CLR), param(ID(WIDTH))); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::EN_POLARITY); + param_bool(ID::SET_POLARITY); + param_bool(ID::CLR_POLARITY); + port(ID::EN, 1); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($fsm)) { - param(ID(NAME)); - param_bool(ID(CLK_POLARITY)); - param_bool(ID(ARST_POLARITY)); - param(ID(STATE_BITS)); - param(ID(STATE_NUM)); - param(ID(STATE_NUM_LOG2)); - param(ID(STATE_RST)); - param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM))); - param(ID(TRANS_NUM)); - param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH)))); - port(ID(CLK), 1); - port(ID(ARST), 1); - port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH))); - port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH))); + param(ID::NAME); + param_bool(ID::CLK_POLARITY); + param_bool(ID::ARST_POLARITY); + param(ID::STATE_BITS); + param(ID::STATE_NUM); + param(ID::STATE_NUM_LOG2); + param(ID::STATE_RST); + param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM)); + param(ID::TRANS_NUM); + param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH))); + port(ID::CLK, 1); + port(ID::ARST, 1); + port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH)); + port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH)); check_expected(); return; } if (cell->type == ID($memrd)) { - param(ID(MEMID)); - param_bool(ID(CLK_ENABLE)); - param_bool(ID(CLK_POLARITY)); - param_bool(ID(TRANSPARENT)); - port(ID(CLK), 1); - port(ID(EN), 1); - port(ID(ADDR), param(ID(ABITS))); - port(ID(DATA), param(ID(WIDTH))); + param(ID::MEMID); + param_bool(ID::CLK_ENABLE); + param_bool(ID::CLK_POLARITY); + param_bool(ID::TRANSPARENT); + port(ID::CLK, 1); + port(ID::EN, 1); + port(ID::ADDR, param(ID::ABITS)); + port(ID::DATA, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($memwr)) { - param(ID(MEMID)); - param_bool(ID(CLK_ENABLE)); - param_bool(ID(CLK_POLARITY)); - param(ID(PRIORITY)); - port(ID(CLK), 1); - port(ID(EN), param(ID(WIDTH))); - port(ID(ADDR), param(ID(ABITS))); - port(ID(DATA), param(ID(WIDTH))); + param(ID::MEMID); + param_bool(ID::CLK_ENABLE); + param_bool(ID::CLK_POLARITY); + param(ID::PRIORITY); + port(ID::CLK, 1); + port(ID::EN, param(ID::WIDTH)); + port(ID::ADDR, param(ID::ABITS)); + port(ID::DATA, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($meminit)) { - param(ID(MEMID)); - param(ID(PRIORITY)); - port(ID(ADDR), param(ID(ABITS))); - port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS))); + param(ID::MEMID); + param(ID::PRIORITY); + port(ID::ADDR, param(ID::ABITS)); + port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS)); check_expected(); return; } if (cell->type == ID($mem)) { - param(ID(MEMID)); - param(ID(SIZE)); - param(ID(OFFSET)); - param(ID(INIT)); - param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS)))); - param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS)))); - param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS)))); - param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS)))); - param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS)))); - port(ID(RD_CLK), param(ID(RD_PORTS))); - port(ID(RD_EN), param(ID(RD_PORTS))); - port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS))); - port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH))); - port(ID(WR_CLK), param(ID(WR_PORTS))); - port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH))); - port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS))); - port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH))); + param(ID::MEMID); + param(ID::SIZE); + param(ID::OFFSET); + param(ID::INIT); + param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS))); + param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS))); + param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS))); + param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS))); + param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS))); + port(ID::RD_CLK, param(ID::RD_PORTS)); + port(ID::RD_EN, param(ID::RD_PORTS)); + port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS)); + port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH)); + port(ID::WR_CLK, param(ID::WR_PORTS)); + port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH)); + port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS)); + port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($tribuf)) { - port(ID::A, param(ID(WIDTH))); - port(ID::Y, param(ID(WIDTH))); - port(ID(EN), 1); + port(ID::A, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); + port(ID::EN, 1); check_expected(); return; } if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) { port(ID::A, 1); - port(ID(EN), 1); + port(ID::EN, 1); check_expected(); return; } @@ -1215,7 +1200,7 @@ namespace { } if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) { - port(ID::Y, param(ID(WIDTH))); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } @@ -1229,115 +1214,115 @@ namespace { } if (cell->type.in(ID($specify2), ID($specify3))) { - param_bool(ID(FULL)); - param_bool(ID(SRC_DST_PEN)); - param_bool(ID(SRC_DST_POL)); - param(ID(T_RISE_MIN)); - param(ID(T_RISE_TYP)); - param(ID(T_RISE_MAX)); - param(ID(T_FALL_MIN)); - param(ID(T_FALL_TYP)); - param(ID(T_FALL_MAX)); - port(ID(EN), 1); - port(ID(SRC), param(ID(SRC_WIDTH))); - port(ID(DST), param(ID(DST_WIDTH))); + param_bool(ID::FULL); + param_bool(ID::SRC_DST_PEN); + param_bool(ID::SRC_DST_POL); + param(ID::T_RISE_MIN); + param(ID::T_RISE_TYP); + param(ID::T_RISE_MAX); + param(ID::T_FALL_MIN); + param(ID::T_FALL_TYP); + param(ID::T_FALL_MAX); + port(ID::EN, 1); + port(ID::SRC, param(ID::SRC_WIDTH)); + port(ID::DST, param(ID::DST_WIDTH)); if (cell->type == ID($specify3)) { - param_bool(ID(EDGE_EN)); - param_bool(ID(EDGE_POL)); - param_bool(ID(DAT_DST_PEN)); - param_bool(ID(DAT_DST_POL)); - port(ID(DAT), param(ID(DST_WIDTH))); + param_bool(ID::EDGE_EN); + param_bool(ID::EDGE_POL); + param_bool(ID::DAT_DST_PEN); + param_bool(ID::DAT_DST_POL); + port(ID::DAT, param(ID::DST_WIDTH)); } check_expected(); return; } if (cell->type == ID($specrule)) { - param(ID(TYPE)); - param_bool(ID(SRC_PEN)); - param_bool(ID(SRC_POL)); - param_bool(ID(DST_PEN)); - param_bool(ID(DST_POL)); - param(ID(T_LIMIT_MIN)); - param(ID(T_LIMIT_TYP)); - param(ID(T_LIMIT_MAX)); - param(ID(T_LIMIT2_MIN)); - param(ID(T_LIMIT2_TYP)); - param(ID(T_LIMIT2_MAX)); - port(ID(SRC_EN), 1); - port(ID(DST_EN), 1); - port(ID(SRC), param(ID(SRC_WIDTH))); - port(ID(DST), param(ID(DST_WIDTH))); + param(ID::TYPE); + param_bool(ID::SRC_PEN); + param_bool(ID::SRC_POL); + param_bool(ID::DST_PEN); + param_bool(ID::DST_POL); + param(ID::T_LIMIT_MIN); + param(ID::T_LIMIT_TYP); + param(ID::T_LIMIT_MAX); + param(ID::T_LIMIT2_MIN); + param(ID::T_LIMIT2_TYP); + param(ID::T_LIMIT2_MAX); + port(ID::SRC_EN, 1); + port(ID::DST_EN, 1); + port(ID::SRC, param(ID::SRC_WIDTH)); + port(ID::DST, param(ID::DST_WIDTH)); check_expected(); return; } - if (cell->type == ID($_BUF_)) { check_gate("AY"); return; } - if (cell->type == ID($_NOT_)) { check_gate("AY"); return; } - if (cell->type == ID($_AND_)) { check_gate("ABY"); return; } - if (cell->type == ID($_NAND_)) { check_gate("ABY"); return; } - if (cell->type == ID($_OR_)) { check_gate("ABY"); return; } - if (cell->type == ID($_NOR_)) { check_gate("ABY"); return; } - if (cell->type == ID($_XOR_)) { check_gate("ABY"); return; } - if (cell->type == ID($_XNOR_)) { check_gate("ABY"); return; } - if (cell->type == ID($_ANDNOT_)) { check_gate("ABY"); return; } - if (cell->type == ID($_ORNOT_)) { check_gate("ABY"); return; } - if (cell->type == ID($_MUX_)) { check_gate("ABSY"); return; } - if (cell->type == ID($_NMUX_)) { check_gate("ABSY"); return; } - if (cell->type == ID($_AOI3_)) { check_gate("ABCY"); return; } - if (cell->type == ID($_OAI3_)) { check_gate("ABCY"); return; } - if (cell->type == ID($_AOI4_)) { check_gate("ABCDY"); return; } - if (cell->type == ID($_OAI4_)) { check_gate("ABCDY"); return; } - - if (cell->type == ID($_TBUF_)) { check_gate("AYE"); return; } - - if (cell->type == ID($_MUX4_)) { check_gate("ABCDSTY"); return; } - if (cell->type == ID($_MUX8_)) { check_gate("ABCDEFGHSTUY"); return; } - if (cell->type == ID($_MUX16_)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; } - - if (cell->type == ID($_SR_NN_)) { check_gate("SRQ"); return; } - if (cell->type == ID($_SR_NP_)) { check_gate("SRQ"); return; } - if (cell->type == ID($_SR_PN_)) { check_gate("SRQ"); return; } - if (cell->type == ID($_SR_PP_)) { check_gate("SRQ"); return; } - - if (cell->type == ID($_FF_)) { check_gate("DQ"); return; } - if (cell->type == ID($_DFF_N_)) { check_gate("DQC"); return; } - if (cell->type == ID($_DFF_P_)) { check_gate("DQC"); return; } - - if (cell->type == ID($_DFFE_NN_)) { check_gate("DQCE"); return; } - if (cell->type == ID($_DFFE_NP_)) { check_gate("DQCE"); return; } - if (cell->type == ID($_DFFE_PN_)) { check_gate("DQCE"); return; } - if (cell->type == ID($_DFFE_PP_)) { check_gate("DQCE"); return; } - - if (cell->type == ID($_DFF_NN0_)) { check_gate("DQCR"); return; } - if (cell->type == ID($_DFF_NN1_)) { check_gate("DQCR"); return; } - if (cell->type == ID($_DFF_NP0_)) { check_gate("DQCR"); return; } - if (cell->type == ID($_DFF_NP1_)) { check_gate("DQCR"); return; } - if (cell->type == ID($_DFF_PN0_)) { check_gate("DQCR"); return; } - if (cell->type == ID($_DFF_PN1_)) { check_gate("DQCR"); return; } - if (cell->type == ID($_DFF_PP0_)) { check_gate("DQCR"); return; } - if (cell->type == ID($_DFF_PP1_)) { check_gate("DQCR"); return; } - - if (cell->type == ID($_DFFSR_NNN_)) { check_gate("CSRDQ"); return; } - if (cell->type == ID($_DFFSR_NNP_)) { check_gate("CSRDQ"); return; } - if (cell->type == ID($_DFFSR_NPN_)) { check_gate("CSRDQ"); return; } - if (cell->type == ID($_DFFSR_NPP_)) { check_gate("CSRDQ"); return; } - if (cell->type == ID($_DFFSR_PNN_)) { check_gate("CSRDQ"); return; } - if (cell->type == ID($_DFFSR_PNP_)) { check_gate("CSRDQ"); return; } - if (cell->type == ID($_DFFSR_PPN_)) { check_gate("CSRDQ"); return; } - if (cell->type == ID($_DFFSR_PPP_)) { check_gate("CSRDQ"); return; } - - if (cell->type == ID($_DLATCH_N_)) { check_gate("EDQ"); return; } - if (cell->type == ID($_DLATCH_P_)) { check_gate("EDQ"); return; } - - if (cell->type == ID($_DLATCHSR_NNN_)) { check_gate("ESRDQ"); return; } - if (cell->type == ID($_DLATCHSR_NNP_)) { check_gate("ESRDQ"); return; } - if (cell->type == ID($_DLATCHSR_NPN_)) { check_gate("ESRDQ"); return; } - if (cell->type == ID($_DLATCHSR_NPP_)) { check_gate("ESRDQ"); return; } - if (cell->type == ID($_DLATCHSR_PNN_)) { check_gate("ESRDQ"); return; } - if (cell->type == ID($_DLATCHSR_PNP_)) { check_gate("ESRDQ"); return; } - if (cell->type == ID($_DLATCHSR_PPN_)) { check_gate("ESRDQ"); return; } - if (cell->type == ID($_DLATCHSR_PPP_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; } + + if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; } + + if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; } + + if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + + if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; } + if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; } + + if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + + if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + + if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + + if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + + if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } error(__LINE__); } @@ -1492,11 +1477,10 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const RTLIL::Module *mod; void operator()(RTLIL::SigSpec &sig) { - std::vector<RTLIL::SigChunk> chunks = sig.chunks(); - for (auto &c : chunks) + sig.pack(); + for (auto &c : sig.chunks_) if (c.wire != NULL) c.wire = mod->wires_.at(c.wire->name); - sig = chunks; } }; @@ -1586,30 +1570,26 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires) const pool<RTLIL::Wire*> *wires_p; void operator()(RTLIL::SigSpec &sig) { - std::vector<RTLIL::SigChunk> chunks = sig; - for (auto &c : chunks) + sig.pack(); + for (auto &c : sig.chunks_) if (c.wire != NULL && wires_p->count(c.wire)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; } - sig = chunks; } void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) { log_assert(GetSize(lhs) == GetSize(rhs)); - RTLIL::SigSpec new_lhs, new_rhs; + lhs.unpack(); + rhs.unpack(); for (int i = 0; i < GetSize(lhs); i++) { - RTLIL::SigBit lhs_bit = lhs[i]; - if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) - continue; - RTLIL::SigBit rhs_bit = rhs[i]; - if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire)) - continue; - new_lhs.append(lhs_bit); - new_rhs.append(rhs_bit); + RTLIL::SigBit &lhs_bit = lhs.bits_[i]; + RTLIL::SigBit &rhs_bit = rhs.bits_[i]; + if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) { + lhs_bit = State::Sx; + rhs_bit = State::Sx; + } } - lhs = new_lhs; - rhs = new_rhs; } }; @@ -1849,17 +1829,17 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth } #define DEF_METHOD(_func, _y_size, _type) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(A_SIGNED)] = is_signed; \ - cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->parameters[ID::A_SIGNED] = is_signed; \ + cell->parameters[ID::A_WIDTH] = sig_a.size(); \ + cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ @@ -1876,20 +1856,20 @@ DEF_METHOD(LogicNot, 1, ID($logic_not)) #undef DEF_METHOD #define DEF_METHOD(_func, _y_size, _type) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(A_SIGNED)] = is_signed; \ - cell->parameters[ID(B_SIGNED)] = is_signed; \ - cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ - cell->parameters[ID(B_WIDTH)] = sig_b.size(); \ - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->parameters[ID::A_SIGNED] = is_signed; \ + cell->parameters[ID::B_SIGNED] = is_signed; \ + cell->parameters[ID::A_WIDTH] = sig_a.size(); \ + cell->parameters[ID::B_WIDTH] = sig_b.size(); \ + cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::B, sig_b); \ cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ @@ -1918,20 +1898,20 @@ DEF_METHOD(LogicOr, 1, ID($logic_or)) #undef DEF_METHOD #define DEF_METHOD(_func, _y_size, _type) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(A_SIGNED)] = is_signed; \ - cell->parameters[ID(B_SIGNED)] = false; \ - cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ - cell->parameters[ID(B_WIDTH)] = sig_b.size(); \ - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->parameters[ID::A_SIGNED] = is_signed; \ + cell->parameters[ID::B_SIGNED] = false; \ + cell->parameters[ID::A_WIDTH] = sig_a.size(); \ + cell->parameters[ID::B_WIDTH] = sig_b.size(); \ + cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::B, sig_b); \ cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ @@ -1943,18 +1923,18 @@ DEF_METHOD(Sshr, sig_a.size(), ID($sshr)) #undef DEF_METHOD #define DEF_METHOD(_func, _type, _pmux) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(WIDTH)] = sig_a.size(); \ - if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \ + cell->parameters[ID::WIDTH] = sig_a.size(); \ + if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::B, sig_b); \ - cell->setPort(ID(S), sig_s); \ + cell->setPort(ID::S, sig_s); \ cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \ add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \ return sig_y; \ @@ -1964,20 +1944,20 @@ DEF_METHOD(Pmux, ID($pmux), 1) #undef DEF_METHOD #define DEF_METHOD_2(_func, _type, _P1, _P2) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->setPort("\\" #_P1, sig1); \ cell->setPort("\\" #_P2, sig2); \ cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \ RTLIL::SigBit sig2 = addWire(NEW_ID); \ add ## _func(name, sig1, sig2, src); \ return sig2; \ } #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->setPort("\\" #_P1, sig1); \ cell->setPort("\\" #_P2, sig2); \ @@ -1985,13 +1965,13 @@ DEF_METHOD(Pmux, ID($pmux), 1) cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \ RTLIL::SigBit sig3 = addWire(NEW_ID); \ add ## _func(name, sig1, sig2, sig3, src); \ return sig3; \ } #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->setPort("\\" #_P1, sig1); \ cell->setPort("\\" #_P2, sig2); \ @@ -2000,13 +1980,13 @@ DEF_METHOD(Pmux, ID($pmux), 1) cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \ RTLIL::SigBit sig4 = addWire(NEW_ID); \ add ## _func(name, sig1, sig2, sig3, sig4, src); \ return sig4; \ } #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->setPort("\\" #_P1, sig1); \ cell->setPort("\\" #_P2, sig2); \ @@ -2016,7 +1996,7 @@ DEF_METHOD(Pmux, ID($pmux), 1) cell->set_src_attribute(src); \ return cell; \ } \ - RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \ RTLIL::SigBit sig5 = addWire(NEW_ID); \ add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \ return sig5; \ @@ -2042,14 +2022,14 @@ DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y) #undef DEF_METHOD_4 #undef DEF_METHOD_5 -RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src) +RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($pow)); - cell->parameters[ID(A_SIGNED)] = a_signed; - cell->parameters[ID(B_SIGNED)] = b_signed; - cell->parameters[ID(A_WIDTH)] = sig_a.size(); - cell->parameters[ID(B_WIDTH)] = sig_b.size(); - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); + cell->parameters[ID::A_SIGNED] = a_signed; + cell->parameters[ID::B_SIGNED] = b_signed; + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::B_WIDTH] = sig_b.size(); + cell->parameters[ID::Y_WIDTH] = sig_y.size(); cell->setPort(ID::A, sig_a); cell->setPort(ID::B, sig_b); cell->setPort(ID::Y, sig_y); @@ -2057,23 +2037,23 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R return cell; } -RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src) +RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($slice)); - cell->parameters[ID(A_WIDTH)] = sig_a.size(); - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); - cell->parameters[ID(OFFSET)] = offset; + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::Y_WIDTH] = sig_y.size(); + cell->parameters[ID::OFFSET] = offset; cell->setPort(ID::A, sig_a); cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src) +RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($concat)); - cell->parameters[ID(A_WIDTH)] = sig_a.size(); - cell->parameters[ID(B_WIDTH)] = sig_b.size(); + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::B_WIDTH] = sig_b.size(); cell->setPort(ID::A, sig_a); cell->setPort(ID::B, sig_b); cell->setPort(ID::Y, sig_y); @@ -2081,74 +2061,74 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a return cell; } -RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src) +RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($lut)); - cell->parameters[ID(LUT)] = lut; - cell->parameters[ID(WIDTH)] = sig_a.size(); + cell->parameters[ID::LUT] = lut; + cell->parameters[ID::WIDTH] = sig_a.size(); cell->setPort(ID::A, sig_a); cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src) +RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($tribuf)); - cell->parameters[ID(WIDTH)] = sig_a.size(); + cell->parameters[ID::WIDTH] = sig_a.size(); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) +RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($assert)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) +RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($assume)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) +RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($live)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) +RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($fair)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) +RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($cover)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src) +RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($equiv)); cell->setPort(ID::A, sig_a); @@ -2158,191 +2138,191 @@ RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, return cell; } -RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($sr)); - cell->parameters[ID(SET_POLARITY)] = set_polarity; - cell->parameters[ID(CLR_POLARITY)] = clr_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(SET), sig_set); - cell->setPort(ID(CLR), sig_clr); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::SET_POLARITY] = set_polarity; + cell->parameters[ID::CLR_POLARITY] = clr_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::SET, sig_set); + cell->setPort(ID::CLR, sig_clr); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src) +RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($ff)); - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dff)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dffe)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(EN_POLARITY)] = en_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(EN), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::EN_POLARITY] = en_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::EN, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dffsr)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(SET_POLARITY)] = set_polarity; - cell->parameters[ID(CLR_POLARITY)] = clr_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(SET), sig_set); - cell->setPort(ID(CLR), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::SET_POLARITY] = set_polarity; + cell->parameters[ID::CLR_POLARITY] = clr_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::SET, sig_set); + cell->setPort(ID::CLR, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, +RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($adff)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(ARST_POLARITY)] = arst_polarity; - cell->parameters[ID(ARST_VALUE)] = arst_value; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(ARST), sig_arst); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::ARST_POLARITY] = arst_polarity; + cell->parameters[ID::ARST_VALUE] = arst_value; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::ARST, sig_arst); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dlatch)); - cell->parameters[ID(EN_POLARITY)] = en_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(EN), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::EN_POLARITY] = en_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::EN, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dlatchsr)); - cell->parameters[ID(EN_POLARITY)] = en_polarity; - cell->parameters[ID(SET_POLARITY)] = set_polarity; - cell->parameters[ID(CLR_POLARITY)] = clr_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(EN), sig_en); - cell->setPort(ID(SET), sig_set); - cell->setPort(ID(CLR), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::EN_POLARITY] = en_polarity; + cell->parameters[ID::SET_POLARITY] = set_polarity; + cell->parameters[ID::CLR_POLARITY] = clr_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::EN, sig_en); + cell->setPort(ID::SET, sig_set); + cell->setPort(ID::CLR, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src) +RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($_FF_)); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(E), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::E, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(S), sig_set); - cell->setPort(ID(R), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::S, sig_set); + cell->setPort(ID::R, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, +RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(R), sig_arst); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::R, sig_arst); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')); - cell->setPort(ID(E), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::E, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } -RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) +RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort(ID(E), sig_en); - cell->setPort(ID(S), sig_set); - cell->setPort(ID(R), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::E, sig_en); + cell->setPort(ID::S, sig_set); + cell->setPort(ID::R, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2351,7 +2331,7 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const st { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($anyconst)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2361,7 +2341,7 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std: { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($anyseq)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2371,7 +2351,7 @@ RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const st { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($allconst)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2381,7 +2361,7 @@ RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std: { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($allseq)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2503,14 +2483,9 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname) void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) { - auto conn_it = connections_.find(portname); - - if (conn_it == connections_.end()) { - connections_[portname] = RTLIL::SigSpec(); - conn_it = connections_.find(portname); - log_assert(conn_it != connections_.end()); - } else - if (conn_it->second == signal) + auto r = connections_.insert(portname); + auto conn_it = r.first; + if (!r.second && conn_it->second == signal) return; for (auto mon : module->monitors) @@ -2525,7 +2500,7 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) log_backtrace("-X- ", yosys_xtrace-1); } - conn_it->second = signal; + conn_it->second = std::move(signal); } const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const @@ -2583,7 +2558,7 @@ void RTLIL::Cell::unsetParam(RTLIL::IdString paramname) void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value) { - parameters[paramname] = value; + parameters[paramname] = std::move(value); } const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const @@ -2613,25 +2588,25 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; if (type == ID($mux) || type == ID($pmux)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]); + parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); if (type == ID($pmux)) - parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]); + parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]); check(); return; } if (type == ID($lut) || type == ID($sop)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID::A]); + parameters[ID::WIDTH] = GetSize(connections_[ID::A]); return; } if (type == ID($fa)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]); + parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); return; } if (type == ID($lcu)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]); + parameters[ID::WIDTH] = GetSize(connections_[ID::CO]); return; } @@ -2640,28 +2615,28 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) if (connections_.count(ID::A)) { if (signedness_ab) { if (set_a_signed) - parameters[ID(A_SIGNED)] = true; - else if (parameters.count(ID(A_SIGNED)) == 0) - parameters[ID(A_SIGNED)] = false; + parameters[ID::A_SIGNED] = true; + else if (parameters.count(ID::A_SIGNED) == 0) + parameters[ID::A_SIGNED] = false; } - parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]); + parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]); } if (connections_.count(ID::B)) { if (signedness_ab) { if (set_b_signed) - parameters[ID(B_SIGNED)] = true; - else if (parameters.count(ID(B_SIGNED)) == 0) - parameters[ID(B_SIGNED)] = false; + parameters[ID::B_SIGNED] = true; + else if (parameters.count(ID::B_SIGNED) == 0) + parameters[ID::B_SIGNED] = false; } - parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]); + parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]); } if (connections_.count(ID::Y)) - parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]); + parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]); - if (connections_.count(ID(Q))) - parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]); + if (connections_.count(ID::Q)) + parameters[ID::WIDTH] = GetSize(connections_[ID::Q]); check(); } @@ -2721,7 +2696,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width) offset = 0; } -RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit) +RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit) { wire = bit.wire; offset = 0; @@ -2732,12 +2707,9 @@ RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit) width = 1; } -RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data) +RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) { - wire = sigchunk.wire; - data = sigchunk.data; - width = sigchunk.width; - offset = sigchunk.offset; + *this = sigchunk; } RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const @@ -2803,45 +2775,21 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts) width_ = 0; hash_ = 0; - std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end()); - for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++) - append(*it); + log_assert(parts.size() > 0); + auto ie = parts.begin(); + auto it = ie + parts.size() - 1; + while (it >= ie) + append(*it--); } -const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other) +RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other) { cover("kernel.rtlil.sigspec.assign"); width_ = other.width_; hash_ = other.hash_; chunks_ = other.chunks_; - bits_.clear(); - - if (!other.bits_.empty()) - { - RTLIL::SigChunk *last = NULL; - int last_end_offset = 0; - - for (auto &bit : other.bits_) { - if (last && bit.wire == last->wire) { - if (bit.wire == NULL) { - last->data.push_back(bit.data); - last->width++; - continue; - } else if (last_end_offset == bit.offset) { - last_end_offset++; - last->width++; - continue; - } - } - chunks_.push_back(bit); - last = &chunks_.back(); - last_end_offset = bit.offset + 1; - } - - check(); - } - + bits_ = other.bits_; return *this; } @@ -2849,7 +2797,7 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) { cover("kernel.rtlil.sigspec.init.const"); - chunks_.push_back(RTLIL::SigChunk(value)); + chunks_.emplace_back(value); width_ = chunks_.back().width; hash_ = 0; check(); @@ -2859,7 +2807,7 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) { cover("kernel.rtlil.sigspec.init.chunk"); - chunks_.push_back(chunk); + chunks_.emplace_back(chunk); width_ = chunks_.back().width; hash_ = 0; check(); @@ -2869,7 +2817,7 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) { cover("kernel.rtlil.sigspec.init.wire"); - chunks_.push_back(RTLIL::SigChunk(wire)); + chunks_.emplace_back(wire); width_ = chunks_.back().width; hash_ = 0; check(); @@ -2879,7 +2827,7 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) { cover("kernel.rtlil.sigspec.init.wire_part"); - chunks_.push_back(RTLIL::SigChunk(wire, offset, width)); + chunks_.emplace_back(wire, offset, width); width_ = chunks_.back().width; hash_ = 0; check(); @@ -2889,7 +2837,7 @@ RTLIL::SigSpec::SigSpec(const std::string &str) { cover("kernel.rtlil.sigspec.init.str"); - chunks_.push_back(RTLIL::SigChunk(str)); + chunks_.emplace_back(str); width_ = chunks_.back().width; hash_ = 0; check(); @@ -2899,7 +2847,7 @@ RTLIL::SigSpec::SigSpec(int val, int width) { cover("kernel.rtlil.sigspec.init.int"); - chunks_.push_back(RTLIL::SigChunk(val, width)); + chunks_.emplace_back(val, width); width_ = width; hash_ = 0; check(); @@ -2909,18 +2857,18 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) { cover("kernel.rtlil.sigspec.init.state"); - chunks_.push_back(RTLIL::SigChunk(bit, width)); + chunks_.emplace_back(bit, width); width_ = width; hash_ = 0; check(); } -RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) +RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width) { cover("kernel.rtlil.sigspec.init.bit"); if (bit.wire == NULL) - chunks_.push_back(RTLIL::SigChunk(bit.data, width)); + chunks_.emplace_back(bit.data, width); else for (int i = 0; i < width; i++) chunks_.push_back(bit); @@ -2929,47 +2877,47 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) check(); } -RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks) +RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks) { cover("kernel.rtlil.sigspec.init.stdvec_chunks"); width_ = 0; hash_ = 0; - for (auto &c : chunks) + for (const auto &c : chunks) append(c); check(); } -RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits) +RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits) { cover("kernel.rtlil.sigspec.init.stdvec_bits"); width_ = 0; hash_ = 0; - for (auto &bit : bits) - append_bit(bit); + for (const auto &bit : bits) + append(bit); check(); } -RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits) +RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits) { cover("kernel.rtlil.sigspec.init.pool_bits"); width_ = 0; hash_ = 0; - for (auto &bit : bits) - append_bit(bit); + for (const auto &bit : bits) + append(bit); check(); } -RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits) +RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits) { cover("kernel.rtlil.sigspec.init.stdset_bits"); width_ = 0; hash_ = 0; - for (auto &bit : bits) - append_bit(bit); + for (const auto &bit : bits) + append(bit); check(); } @@ -2979,7 +2927,7 @@ RTLIL::SigSpec::SigSpec(bool bit) width_ = 0; hash_ = 0; - append_bit(bit); + append(SigBit(bit)); check(); } @@ -3032,7 +2980,7 @@ void RTLIL::SigSpec::unpack() const that->bits_.reserve(that->width_); for (auto &c : that->chunks_) for (int i = 0; i < c.width; i++) - that->bits_.push_back(RTLIL::SigBit(c, i)); + that->bits_.emplace_back(c, i); that->chunks_.clear(); that->hash_ = 0; @@ -3297,14 +3245,14 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLI bits_match[i].wire == pattern_chunk.wire && bits_match[i].offset >= pattern_chunk.offset && bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width) - ret.append_bit(bits_other[i]); + ret.append(bits_other[i]); } else { for (int i = 0; i < width_; i++) if (bits_match[i].wire && bits_match[i].wire == pattern_chunk.wire && bits_match[i].offset >= pattern_chunk.offset && bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width) - ret.append_bit(bits_match[i]); + ret.append(bits_match[i]); } } @@ -3328,11 +3276,11 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector(); for (int i = 0; i < width_; i++) if (bits_match[i].wire && pattern.count(bits_match[i])) - ret.append_bit(bits_other[i]); + ret.append(bits_other[i]); } else { for (int i = 0; i < width_; i++) if (bits_match[i].wire && pattern.count(bits_match[i])) - ret.append_bit(bits_match[i]); + ret.append(bits_match[i]); } ret.check(); @@ -3454,7 +3402,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) check(); } -void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) +void RTLIL::SigSpec::append(const RTLIL::SigBit &bit) { if (packed()) { @@ -3527,7 +3475,7 @@ void RTLIL::SigSpec::check() const int w = 0; for (size_t i = 0; i < chunks_.size(); i++) { - const RTLIL::SigChunk chunk = chunks_[i]; + const RTLIL::SigChunk &chunk = chunks_[i]; if (chunk.wire == NULL) { if (i > 0) log_assert(chunks_[i-1].wire != NULL); @@ -3766,11 +3714,11 @@ std::string RTLIL::SigSpec::as_string() const pack(); std::string str; + str.reserve(size()); for (size_t i = chunks_.size(); i > 0; i--) { const RTLIL::SigChunk &chunk = chunks_[i-1]; if (chunk.wire != NULL) - for (int j = 0; j < chunk.width; j++) - str += "?"; + str.append(chunk.width, '?'); else str += RTLIL::Const(chunk.data).as_string(); } @@ -3817,24 +3765,30 @@ RTLIL::SigBit RTLIL::SigSpec::as_bit() const return bits_[0]; } -bool RTLIL::SigSpec::match(std::string pattern) const +bool RTLIL::SigSpec::match(const char* pattern) const { cover("kernel.rtlil.sigspec.match"); - pack(); - std::string str = as_string(); - log_assert(pattern.size() == str.size()); + unpack(); + log_assert(int(strlen(pattern)) == GetSize(bits_)); - for (size_t i = 0; i < pattern.size(); i++) { - if (pattern[i] == ' ') + for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) { + if (*pattern == ' ') continue; - if (pattern[i] == '*') { - if (str[i] != 'z' && str[i] != 'x') + if (*pattern == '*') { + if (*it != State::Sz && *it != State::Sx) return false; continue; } - if (pattern[i] != str[i]) - return false; + if (*pattern == '0') { + if (*it != State::S0) + return false; + } else + if (*pattern == '1') { + if (*it != State::S1) + return false; + } else + log_abort(); } return true; @@ -3858,6 +3812,7 @@ pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const pack(); pool<RTLIL::SigBit> sigbits; + sigbits.reserve(size()); for (auto &c : chunks_) for (int i = 0; i < c.width; i++) sigbits.insert(RTLIL::SigBit(c, i)); @@ -3898,6 +3853,7 @@ dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::S log_assert(width_ == other.width_); dict<RTLIL::SigBit, RTLIL::SigBit> new_map; + new_map.reserve(size()); for (int i = 0; i < width_; i++) new_map[bits_[i]] = other.bits_[i]; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 58c5d9674..7279835ea 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -235,7 +235,10 @@ namespace RTLIL return; log_assert(refcount == 0); - + free_reference(idx); + } + static inline void free_reference(int idx) + { if (yosys_xtrace) { log("#X# Removed IdString '%s' with index %d.\n", global_id_storage_.at(idx), idx); log_backtrace("-X- ", yosys_xtrace-1); @@ -358,34 +361,35 @@ namespace RTLIL // often one needs to check if a given IdString is part of a list (for example a list // of cell types). the following functions helps with that. - template<typename T, typename... Args> - bool in(T first, Args... rest) const { - return in(first) || in(rest...); + template<typename... Args> + bool in(Args... args) const { + // Credit: https://articles.emptycrate.com/2016/05/14/folds_in_cpp11_ish.html + bool result = false; + (void) std::initializer_list<int>{ (result = result || in(args), 0)... }; + return result; } - bool in(IdString rhs) const { return *this == rhs; } + bool in(const IdString &rhs) const { return *this == rhs; } bool in(const char *rhs) const { return *this == rhs; } bool in(const std::string &rhs) const { return *this == rhs; } bool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; } }; namespace ID { - // defined in rtlil.cc, initialized in yosys.cc - extern IdString A, B, Y; - extern IdString keep; - extern IdString whitebox; - extern IdString blackbox; +#define X(_id) extern IdString _id; +#include "constids.inc" +#undef X }; extern dict<std::string, std::string> constpad; - static inline std::string escape_id(std::string str) { + static inline std::string escape_id(const std::string &str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; return str; } - static inline std::string unescape_id(std::string str) { + static inline std::string unescape_id(const std::string &str) { if (str.size() < 2) return str; if (str[0] != '\\') @@ -401,7 +405,7 @@ namespace RTLIL return unescape_id(str.str()); } - static inline const char *id2cstr(const RTLIL::IdString &str) { + static inline const char *id2cstr(RTLIL::IdString str) { return log_id(str); } @@ -606,7 +610,7 @@ struct RTLIL::Const bool as_bool() const; int as_int(bool is_signed = false) const; std::string as_string() const; - static Const from_string(std::string str); + static Const from_string(const std::string &str); std::string decode_string() const; @@ -678,7 +682,7 @@ struct RTLIL::SigChunk SigChunk(const std::string &str); SigChunk(int val, int width = 32); SigChunk(RTLIL::State bit, int width = 1); - SigChunk(RTLIL::SigBit bit); + SigChunk(const RTLIL::SigBit &bit); SigChunk(const RTLIL::SigChunk &sigchunk); RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default; @@ -758,11 +762,15 @@ private: unpack(); } + // Only used by Module::remove(const pool<Wire*> &wires) + // but cannot be more specific as it isn't yet declared + friend struct RTLIL::Module; + public: SigSpec(); SigSpec(const RTLIL::SigSpec &other); SigSpec(std::initializer_list<RTLIL::SigSpec> parts); - const RTLIL::SigSpec &operator=(const RTLIL::SigSpec &other); + RTLIL::SigSpec &operator=(const RTLIL::SigSpec &other); SigSpec(const RTLIL::Const &value); SigSpec(const RTLIL::SigChunk &chunk); @@ -771,11 +779,11 @@ public: SigSpec(const std::string &str); SigSpec(int val, int width = 32); SigSpec(RTLIL::State bit, int width = 1); - SigSpec(RTLIL::SigBit bit, int width = 1); - SigSpec(std::vector<RTLIL::SigChunk> chunks); - SigSpec(std::vector<RTLIL::SigBit> bits); - SigSpec(pool<RTLIL::SigBit> bits); - SigSpec(std::set<RTLIL::SigBit> bits); + SigSpec(const RTLIL::SigBit &bit, int width = 1); + SigSpec(const std::vector<RTLIL::SigChunk> &chunks); + SigSpec(const std::vector<RTLIL::SigBit> &bits); + SigSpec(const pool<RTLIL::SigBit> &bits); + SigSpec(const std::set<RTLIL::SigBit> &bits); SigSpec(bool bit); SigSpec(RTLIL::SigSpec &&other) { @@ -845,7 +853,13 @@ public: RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } void append(const RTLIL::SigSpec &signal); - void append_bit(const RTLIL::SigBit &bit); + inline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); } + inline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); } + inline void append(const RTLIL::Const &const_) { append(RTLIL::SigSpec(const_)); } + + void append(const RTLIL::SigBit &bit); + inline void append(RTLIL::State state) { append(RTLIL::SigBit(state)); } + inline void append(bool bool_) { append(RTLIL::SigBit(bool_)); } void extend_u0(int width, bool is_signed = false); @@ -877,7 +891,7 @@ public: RTLIL::SigChunk as_chunk() const; RTLIL::SigBit as_bit() const; - bool match(std::string pattern) const; + bool match(const char* pattern) const; std::set<RTLIL::SigBit> to_sigbit_set() const; pool<RTLIL::SigBit> to_sigbit_pool() const; @@ -891,7 +905,7 @@ public: operator std::vector<RTLIL::SigChunk>() const { return chunks(); } operator std::vector<RTLIL::SigBit>() const { return bits(); } - RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; } + const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; } unsigned int hash() const { if (!hash_) updhash(); return hash_; }; @@ -946,12 +960,15 @@ struct RTLIL::Monitor virtual ~Monitor() { } virtual void notify_module_add(RTLIL::Module*) { } virtual void notify_module_del(RTLIL::Module*) { } - virtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, RTLIL::SigSpec&) { } + virtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { } virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { } virtual void notify_blackout(RTLIL::Module*) { } }; +// Forward declaration; defined in preproc.h. +struct define_map_t; + struct RTLIL::Design { unsigned int hashidx_; @@ -963,7 +980,7 @@ struct RTLIL::Design int refcount_modules_; dict<RTLIL::IdString, RTLIL::Module*> modules_; std::vector<AST::AstNode*> verilog_packages, verilog_globals; - dict<std::string, std::pair<std::string, bool>> verilog_defines; + std::unique_ptr<define_map_t> verilog_defines; std::vector<RTLIL::Selection> selection_stack; dict<RTLIL::IdString, RTLIL::Selection> selection_vars; @@ -985,15 +1002,15 @@ struct RTLIL::Design void remove(RTLIL::Module *module); void rename(RTLIL::Module *module, RTLIL::IdString new_name); - void scratchpad_unset(std::string varname); + void scratchpad_unset(const std::string &varname); - void scratchpad_set_int(std::string varname, int value); - void scratchpad_set_bool(std::string varname, bool value); - void scratchpad_set_string(std::string varname, std::string value); + void scratchpad_set_int(const std::string &varname, int value); + void scratchpad_set_bool(const std::string &varname, bool value); + void scratchpad_set_string(const std::string &varname, std::string value); - int scratchpad_get_int(std::string varname, int default_value = 0) const; - bool scratchpad_get_bool(std::string varname, bool default_value = false) const; - std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + int scratchpad_get_int(const std::string &varname, int default_value = 0) const; + bool scratchpad_get_bool(const std::string &varname, bool default_value = false) const; + std::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const; void sort(); void check(); @@ -1069,10 +1086,10 @@ public: Module(); virtual ~Module(); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); - virtual void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces); + virtual void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces); virtual void sort(); virtual void check(); @@ -1133,166 +1150,166 @@ public: // The add* methods create a cell and return the created cell. All signals must exist in advance. - RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - - RTLIL::Cell* addAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - - RTLIL::Cell* addReduceAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addReduceOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addReduceXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - - RTLIL::Cell* addShl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addShr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addSshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addSshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addShift (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addShiftx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - - RTLIL::Cell* addLt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addLe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addEq (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addNe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addEqx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addNex (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addGe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addGt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - - RTLIL::Cell* addAdd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addSub (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addMul (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addDiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addMod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addPow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); - - RTLIL::Cell* addLogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addLogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - RTLIL::Cell* addLogicOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - - RTLIL::Cell* addMux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); - RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); - - RTLIL::Cell* addSlice (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); - RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); - RTLIL::Cell* addLut (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); - RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); - RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - RTLIL::Cell* addAssume (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - RTLIL::Cell* addLive (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - RTLIL::Cell* addFair (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - RTLIL::Cell* addCover (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - RTLIL::Cell* addEquiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); - - RTLIL::Cell* addSr (RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - RTLIL::Cell* addFf (RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); - RTLIL::Cell* addDff (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDffe (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDffsr (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - RTLIL::Cell* addAdff (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, + RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + + RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + + RTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + + RTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + + RTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + + RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + + RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + + RTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + RTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + + RTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src = ""); + RTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + RTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src = ""); + RTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + RTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = ""); + RTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = ""); + RTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = ""); + RTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = ""); + RTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src = ""); + RTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + + RTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + RTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = ""); + RTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = ""); + RTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDlatch (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDlatchsr (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - - RTLIL::Cell* addBufGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addNotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addAndGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addNandGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addOrGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addNorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addXorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addXnorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addAndnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addOrnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addMuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addNmuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addOai3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); - RTLIL::Cell* addOai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); - - RTLIL::Cell* addFfGate (RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); - RTLIL::Cell* addDffGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDffeGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDffsrGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - RTLIL::Cell* addAdffGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, + RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = ""); + RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + + RTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = ""); + RTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = ""); + + RTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = ""); + RTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = ""); + RTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + RTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + RTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDlatchGate (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); - RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, - RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = ""); + RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, + RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); // The methods without the add* prefix create a cell and an output signal. They return the newly created output signal. - RTLIL::SigSpec Not (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Pos (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Bu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Neg (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - - RTLIL::SigSpec And (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Or (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Xor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Xnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - - RTLIL::SigSpec ReduceAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec ReduceOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec ReduceXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec ReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - - RTLIL::SigSpec Shl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Shr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Sshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Sshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Shift (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Shiftx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - - RTLIL::SigSpec Lt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Le (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Eq (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Ne (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Eqx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Nex (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Ge (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Gt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - - RTLIL::SigSpec Add (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Sub (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Mul (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Div (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Mod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec Pow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = ""); - - RTLIL::SigSpec LogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec LogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - RTLIL::SigSpec LogicOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - - RTLIL::SigSpec Mux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); - RTLIL::SigSpec Pmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); - - RTLIL::SigBit BufGate (RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); - RTLIL::SigBit NotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); - RTLIL::SigBit AndGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit NandGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit OrGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit NorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit XorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit XnorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit AndnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit OrnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - RTLIL::SigBit MuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); - RTLIL::SigBit NmuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); - RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); - RTLIL::SigBit Oai3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); - RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); - RTLIL::SigBit Oai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Bu0 (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + + RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + + RTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + + RTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + + RTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + + RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + + RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); + + RTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = ""); + RTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src = ""); + + RTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = ""); + RTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const std::string &src = ""); + RTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const std::string &src = ""); + RTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = ""); + RTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const std::string &src = ""); + RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = ""); + RTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const std::string &src = ""); + RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = ""); + RTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const std::string &src = ""); RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); @@ -1465,7 +1482,7 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } -inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){if(wire) offset = sigbit.offset;} +inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){ if (wire) offset = sigbit.offset; } inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const { if (wire == other.wire) diff --git a/kernel/satgen.h b/kernel/satgen.h index 133389eee..88b84b7e6 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -224,8 +224,8 @@ struct SatGen void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false) { bool is_signed = forced_signed; - if (!forced_signed && cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters.count(ID(B_SIGNED)) > 0) - is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); + if (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0) + is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool(); while (vec_a.size() < vec_b.size() || vec_a.size() < y_width) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_b.size() < vec_a.size() || vec_b.size() < y_width) @@ -241,7 +241,7 @@ struct SatGen void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false) { - bool is_signed = forced_signed || (cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool()); + bool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool()); while (vec_a.size() < vec_y.size()) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_y.size() < vec_a.size()) @@ -397,8 +397,8 @@ struct SatGen int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0); int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0); - int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0); - int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0); + int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0); + int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0); int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); int yy = model_undef ? ez->literal() : y; @@ -411,8 +411,8 @@ struct SatGen { int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0); int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0); - int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0); - int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0); + int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0); + int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0); int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0); if (aoi_mode) @@ -479,7 +479,7 @@ struct SatGen { std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; @@ -492,7 +492,7 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b)); @@ -508,7 +508,7 @@ struct SatGen { std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; @@ -524,7 +524,7 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); int maybe_a = ez->CONST_TRUE; @@ -684,7 +684,7 @@ struct SatGen if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { - bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); + bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool(); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); @@ -774,7 +774,7 @@ struct SatGen int extend_bit = ez->CONST_FALSE; - if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) + if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool()) extend_bit = a.back(); while (y.size() < a.size()) @@ -792,10 +792,10 @@ struct SatGen shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($sshr)) - shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); + shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type.in(ID($shift), ID($shiftx))) - shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); + shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); ez->assume(ez->vec_eq(shifted_a, yy)); @@ -807,7 +807,7 @@ struct SatGen std::vector<int> undef_a_shifted; extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE; - if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) + if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool()) extend_bit = undef_a.back(); while (undef_y.size() < undef_a.size()) @@ -822,13 +822,13 @@ struct SatGen undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($sshr)) - undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE); + undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($shift)) - undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($shiftx)) - undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE); + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b); @@ -945,7 +945,7 @@ struct SatGen std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> a_u, b_u; - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) { a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a); b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b); } else { @@ -971,12 +971,12 @@ struct SatGen std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size()); if (cell->type == ID($div)) { - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u))); else ez->assume(ez->vec_eq(y_tmp, y_u)); } else { - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf))); else ez->assume(ez->vec_eq(y_tmp, chain_buf)); @@ -987,7 +987,7 @@ struct SatGen } else { std::vector<int> div_zero_result; if (cell->type == ID($div)) { - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) { std::vector<int> all_ones(y.size(), ez->CONST_TRUE); std::vector<int> only_first_one(y.size(), ez->CONST_FALSE); only_first_one.at(0) = ez->CONST_TRUE; @@ -999,7 +999,7 @@ struct SatGen } else { int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); else div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE); @@ -1021,7 +1021,7 @@ struct SatGen std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> lut; - for (auto bit : cell->getParam(ID(LUT)).bits) + for (auto bit : cell->getParam(ID::LUT).bits) lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); while (GetSize(lut) < (1 << GetSize(a))) lut.push_back(ez->CONST_FALSE); @@ -1070,10 +1070,10 @@ struct SatGen std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); - int width = cell->getParam(ID(WIDTH)).as_int(); - int depth = cell->getParam(ID(DEPTH)).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int depth = cell->getParam(ID::DEPTH).as_int(); - vector<State> table_raw = cell->getParam(ID(TABLE)).bits; + vector<State> table_raw = cell->getParam(ID::TABLE).bits; while (GetSize(table_raw) < 2*width*depth) table_raw.push_back(State::S0); @@ -1151,9 +1151,9 @@ struct SatGen { std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> c = importDefSigSpec(cell->getPort(ID(C)), timestep); + std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep); + std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep); std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x; @@ -1169,10 +1169,10 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep); + std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); + std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); ez->assume(ez->vec_eq(undef_x, undef_y)); @@ -1185,10 +1185,10 @@ struct SatGen if (cell->type == ID($lcu)) { - std::vector<int> p = importDefSigSpec(cell->getPort(ID(P)), timestep); - std::vector<int> g = importDefSigSpec(cell->getPort(ID(G)), timestep); - std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep); + std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep); + std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep); std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co; @@ -1197,10 +1197,10 @@ struct SatGen if (model_undef) { - std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID(P)), timestep); - std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID(G)), timestep); - std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep); + std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep); + std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep); int undef_any_p = ez->expression(ezSAT::OpOr, undef_p); int undef_any_g = ez->expression(ezSAT::OpOr, undef_g); @@ -1220,10 +1220,10 @@ struct SatGen std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep); - std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> bi = importDefSigSpec(cell->getPort(ID(BI)), timestep); - std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep); + std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep); + std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep); extendSignalWidth(a, b, y, cell); extendSignalWidth(a, b, x, cell); @@ -1250,12 +1250,12 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep); + std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); - std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep); + std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell); extendSignalWidth(undef_a, undef_b, undef_x, cell); @@ -1285,7 +1285,7 @@ struct SatGen { RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec y = cell->getPort(ID::Y); - ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep)); + ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep)); return true; } @@ -1306,20 +1306,20 @@ struct SatGen { if (timestep == 1) { - initial_state.add((*sigmap)(cell->getPort(ID(Q)))); + initial_state.add((*sigmap)(cell->getPort(ID::Q))); } else { - std::vector<int> d = importDefSigSpec(cell->getPort(ID(D)), timestep-1); - std::vector<int> q = importDefSigSpec(cell->getPort(ID(Q)), timestep); + std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1); + std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep); std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(D)), timestep-1); - std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Q)), timestep); + std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1); + std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -1397,7 +1397,7 @@ struct SatGen { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); asserts_a[pf].append((*sigmap)(cell->getPort(ID::A))); - asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); + asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN))); return true; } @@ -1405,7 +1405,7 @@ struct SatGen { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); assumes_a[pf].append((*sigmap)(cell->getPort(ID::A))); - assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); + assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN))); return true; } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 2517d6de3..c631fa481 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -39,7 +39,7 @@ struct SigPool bits.clear(); } - void add(RTLIL::SigSpec sig) + void add(const RTLIL::SigSpec &sig) { for (auto &bit : sig) if (bit.wire != NULL) @@ -52,7 +52,7 @@ struct SigPool bits.insert(bit); } - void del(RTLIL::SigSpec sig) + void del(const RTLIL::SigSpec &sig) { for (auto &bit : sig) if (bit.wire != NULL) @@ -65,7 +65,7 @@ struct SigPool bits.erase(bit); } - void expand(RTLIL::SigSpec from, RTLIL::SigSpec to) + void expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to) { log_assert(GetSize(from) == GetSize(to)); for (int i = 0; i < GetSize(from); i++) { @@ -75,16 +75,16 @@ struct SigPool } } - RTLIL::SigSpec extract(RTLIL::SigSpec sig) + RTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const { RTLIL::SigSpec result; for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit)) - result.append_bit(bit); + result.append(bit); return result; } - RTLIL::SigSpec remove(RTLIL::SigSpec sig) + RTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const { RTLIL::SigSpec result; for (auto &bit : sig) @@ -93,12 +93,12 @@ struct SigPool return result; } - bool check(RTLIL::SigBit bit) + bool check(const RTLIL::SigBit &bit) const { return bit.wire != NULL && bits.count(bit); } - bool check_any(RTLIL::SigSpec sig) + bool check_any(const RTLIL::SigSpec &sig) const { for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit)) @@ -106,7 +106,7 @@ struct SigPool return false; } - bool check_all(RTLIL::SigSpec sig) + bool check_all(const RTLIL::SigSpec &sig) const { for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit) == 0) @@ -114,14 +114,14 @@ struct SigPool return true; } - RTLIL::SigSpec export_one() + RTLIL::SigSpec export_one() const { for (auto &bit : bits) return RTLIL::SigSpec(bit.first, bit.second); return RTLIL::SigSpec(); } - RTLIL::SigSpec export_all() + RTLIL::SigSpec export_all() const { pool<RTLIL::SigBit> sig; for (auto &bit : bits) @@ -153,67 +153,67 @@ struct SigSet bits.clear(); } - void insert(RTLIL::SigSpec sig, T data) + void insert(const RTLIL::SigSpec &sig, T data) { - for (auto &bit : sig) + for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].insert(data); } - void insert(RTLIL::SigSpec sig, const std::set<T> &data) + void insert(const RTLIL::SigSpec& sig, const std::set<T> &data) { - for (auto &bit : sig) + for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].insert(data.begin(), data.end()); } - void erase(RTLIL::SigSpec sig) + void erase(const RTLIL::SigSpec& sig) { - for (auto &bit : sig) + for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].clear(); } - void erase(RTLIL::SigSpec sig, T data) + void erase(const RTLIL::SigSpec &sig, T data) { - for (auto &bit : sig) + for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].erase(data); } - void erase(RTLIL::SigSpec sig, const std::set<T> &data) + void erase(const RTLIL::SigSpec &sig, const std::set<T> &data) { - for (auto &bit : sig) + for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].erase(data.begin(), data.end()); } - void find(RTLIL::SigSpec sig, std::set<T> &result) + void find(const RTLIL::SigSpec &sig, std::set<T> &result) { - for (auto &bit : sig) + for (const auto &bit : sig) if (bit.wire != NULL) { auto &data = bits[bit]; result.insert(data.begin(), data.end()); } } - void find(RTLIL::SigSpec sig, pool<T> &result) + void find(const RTLIL::SigSpec &sig, pool<T> &result) { - for (auto &bit : sig) + for (const auto &bit : sig) if (bit.wire != NULL) { auto &data = bits[bit]; result.insert(data.begin(), data.end()); } } - std::set<T> find(RTLIL::SigSpec sig) + std::set<T> find(const RTLIL::SigSpec &sig) { std::set<T> result; find(sig, result); return result; } - bool has(RTLIL::SigSpec sig) + bool has(const RTLIL::SigSpec &sig) { for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit)) @@ -262,7 +262,7 @@ struct SigMap add(it.first, it.second); } - void add(RTLIL::SigSpec from, RTLIL::SigSpec to) + void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to) { log_assert(GetSize(from) == GetSize(to)); @@ -287,15 +287,21 @@ struct SigMap } } - void add(RTLIL::SigSpec sig) + void add(const RTLIL::SigBit &bit) { - for (auto &bit : sig) { - RTLIL::SigBit b = database.find(bit); - if (b.wire != nullptr) - database.promote(bit); - } + const auto &b = database.find(bit); + if (b.wire != nullptr) + database.promote(bit); + } + + void add(const RTLIL::SigSpec &sig) + { + for (const auto &bit : sig) + add(bit); } + inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); } + void apply(RTLIL::SigBit &bit) const { bit = database.find(bit); @@ -329,7 +335,7 @@ struct SigMap RTLIL::SigSpec allbits() const { RTLIL::SigSpec sig; - for (auto &bit : database) + for (const auto &bit : database) if (bit.wire != nullptr) sig.append(bit); return sig; diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 4b77c02e8..fb4e0930d 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -82,20 +82,20 @@ struct TimingInfo for (auto cell : module->cells()) { if (cell->type == ID($specify2)) { - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); - int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); - int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); + int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); + int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max); if (max < 0) log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell)); - if (cell->getParam(ID(FULL)).as_bool()) { + if (cell->getParam(ID::FULL).as_bool()) { for (const auto &s : src) for (const auto &d : dst) { auto r = t.comb.insert(BitBit(s,d)); @@ -117,16 +117,16 @@ struct TimingInfo } } else if (cell->type == ID($specify3)) { - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); - int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); - int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); + int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); + int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max); if (max < 0) log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); @@ -140,18 +140,18 @@ struct TimingInfo } } else if (cell->type == ID($specrule)) { - auto type = cell->getParam(ID(TYPE)).decode_string(); + auto type = cell->getParam(ID::TYPE).decode_string(); if (type != "$setup" && type != "$setuphold") continue; - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst)); - int max = cell->getParam(ID(T_LIMIT_MAX)).as_int(); + int max = cell->getParam(ID::T_LIMIT_MAX).as_int(); if (max < 0) log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); if (max <= 0) { diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 4cb53f05d..380f7030b 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -515,12 +515,9 @@ void yosys_setup() return; already_setup = true; - RTLIL::ID::A = "\\A"; - RTLIL::ID::B = "\\B"; - RTLIL::ID::Y = "\\Y"; - RTLIL::ID::keep = "\\keep"; - RTLIL::ID::whitebox = "\\whitebox"; - RTLIL::ID::blackbox = "\\blackbox"; +#define X(_id) RTLIL::ID::_id = "\\" # _id; +#include "constids.inc" +#undef X #ifdef WITH_PYTHON PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); @@ -1098,30 +1095,29 @@ static char *readline_obj_generator(const char *text, int state) if (design->selected_active_module.empty()) { - for (auto &it : design->modules_) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + for (auto mod : design->modules()) + if (RTLIL::unescape_id(mod->name).compare(0, len, text) == 0) + obj_names.push_back(strdup(log_id(mod->name))); } - else - if (design->modules_.count(design->selected_active_module) > 0) + else if (design->module(design->selected_active_module) != nullptr) { - RTLIL::Module *module = design->modules_.at(design->selected_active_module); + RTLIL::Module *module = design->module(design->selected_active_module); - for (auto &it : module->wires_) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + for (auto w : module->wires()) + if (RTLIL::unescape_id(w->name).compare(0, len, text) == 0) + obj_names.push_back(strdup(log_id(w->name))); for (auto &it : module->memories) if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + obj_names.push_back(strdup(log_id(it.first))); - for (auto &it : module->cells_) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + for (auto cell : module->cells()) + if (RTLIL::unescape_id(cell->name).compare(0, len, text) == 0) + obj_names.push_back(strdup(log_id(cell->name))); for (auto &it : module->processes) if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + obj_names.push_back(strdup(log_id(it.first))); } std::sort(obj_names.begin(), obj_names.end()); diff --git a/kernel/yosys.h b/kernel/yosys.h index 179bfe07a..16e0aaf1c 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -306,9 +306,9 @@ RTLIL::IdString new_id(std::string file, int line, std::string func); #define NEW_ID \ YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__) -// Create a statically allocated IdString object, using for example ID(A) or ID($add). +// Create a statically allocated IdString object, using for example ID::A or ID($add). // -// Recipe for Converting old code that is using conversion of strings like "\\A" and +// Recipe for Converting old code that is using conversion of strings like ID::A and // "$add" for creating IdStrings: Run below SED command on the .cc file and then use for // example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary. // diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index 177bcd8a3..8c666ca1f 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -1371,24 +1371,39 @@ int ezSAT::onehot(const std::vector<int> &vec, bool max_only) if (max_only == false) formula.push_back(expression(OpOr, vec)); - // create binary vector - int num_bits = clog2(vec.size()); - std::vector<int> bits; - for (int k = 0; k < num_bits; k++) - bits.push_back(literal()); - - // add at-most-one clauses using binary encoding - for (size_t i = 0; i < vec.size(); i++) - for (int k = 0; k < num_bits; k++) { - std::vector<int> clause; - clause.push_back(NOT(vec[i])); - clause.push_back((i & (1 << k)) != 0 ? bits[k] : NOT(bits[k])); - formula.push_back(expression(OpOr, clause)); - } + if (vec.size() < 8) + { + // fall-back to simple O(n^2) solution for small cases + for (size_t i = 0; i < vec.size(); i++) + for (size_t j = i+1; j < vec.size(); j++) { + std::vector<int> clause; + clause.push_back(NOT(vec[i])); + clause.push_back(NOT(vec[j])); + formula.push_back(expression(OpOr, clause)); + } + } + else + { + // create binary vector + int num_bits = clog2(vec.size()); + std::vector<int> bits; + for (int k = 0; k < num_bits; k++) + bits.push_back(literal()); + + // add at-most-one clauses using binary encoding + for (size_t i = 0; i < vec.size(); i++) + for (int k = 0; k < num_bits; k++) { + std::vector<int> clause; + clause.push_back(NOT(vec[i])); + clause.push_back((i & (1 << k)) != 0 ? bits[k] : NOT(bits[k])); + formula.push_back(expression(OpOr, clause)); + } + } return expression(OpAnd, formula); } +#if 0 int ezSAT::manyhot(const std::vector<int> &vec, int min_hot, int max_hot) { // many-hot encoding using a simple sorting network @@ -1426,6 +1441,123 @@ int ezSAT::manyhot(const std::vector<int> &vec, int min_hot, int max_hot) return expression(OpAnd, formula); } +#else +static std::vector<int> lfsr_sym(ezSAT *that, const std::vector<int> &vec, int poly) +{ + std::vector<int> out; + + for (int i = 0; i < int(vec.size()); i++) + if ((poly & (1 << (i+1))) != 0) { + if (out.empty()) + out.push_back(vec.at(i)); + else + out.at(0) = that->XOR(out.at(0), vec.at(i)); + } + + for (int i = 0; i+1 < int(vec.size()); i++) + out.push_back(vec.at(i)); + + return out; +} + +static int lfsr_num(int vec, int poly, int cnt = 1) +{ + int mask = poly >> 1; + mask |= mask >> 1; + mask |= mask >> 2; + mask |= mask >> 4; + mask |= mask >> 8; + mask |= mask >> 16; + + while (cnt-- > 0) { + int bits = vec & (poly >> 1); + bits = ((bits & 0xAAAAAAAA) >> 1) ^ (bits & 0x55555555); + bits = ((bits & 0x44444444) >> 2) ^ (bits & 0x11111111); + bits = ((bits & 0x10101010) >> 4) ^ (bits & 0x01010101); + bits = ((bits & 0x01000100) >> 8) ^ (bits & 0x00010001); + bits = ((bits & 0x00010000) >> 16) ^ (bits & 0x00000001); + vec = ((vec << 1) | bits) & mask; + } + + return vec; +} + +int ezSAT::manyhot(const std::vector<int> &vec, int min_hot, int max_hot) +{ + // many-hot encoding using LFSR as counter + + int poly = 0; + int nbits = 0; + + if (vec.size() < 3) { + poly = (1 << 2) | (1 << 1) | 1; + nbits = 2; + } else + if (vec.size() < 7) { + poly = (1 << 3) | (1 << 2) | 1; + nbits = 3; + } else + if (vec.size() < 15) { + poly = (1 << 4) | (1 << 3) | 1; + nbits = 4; + } else + if (vec.size() < 31) { + poly = (1 << 5) | (1 << 3) | 1; + nbits = 5; + } else + if (vec.size() < 63) { + poly = (1 << 6) | (1 << 5) | 1; + nbits = 6; + } else + if (vec.size() < 127) { + poly = (1 << 7) | (1 << 6) | 1; + nbits = 7; + } else + // if (vec.size() < 255) { + // poly = (1 << 8) | (1 << 6) | (1 << 5) | (1 << 4) | 1; + // nbits = 8; + // } else + if (vec.size() < 511) { + poly = (1 << 9) | (1 << 5) | 1; + nbits = 9; + } else { + assert(0); + } + + std::vector<int> min_val; + std::vector<int> max_val; + + if (min_hot > 1) + min_val = vec_const_unsigned(lfsr_num(1, poly, min_hot), nbits); + + if (max_hot >= 0) + max_val = vec_const_unsigned(lfsr_num(1, poly, max_hot+1), nbits); + + std::vector<int> state = vec_const_unsigned(1, nbits); + + std::vector<int> match_min; + std::vector<int> match_max; + + if (min_hot == 1) + match_min = vec; + + for (int i = 0; i < int(vec.size()); i++) + { + state = vec_ite(vec[i], lfsr_sym(this, state, poly), state); + + if (!min_val.empty() && i+1 >= min_hot) + match_min.push_back(vec_eq(min_val, state)); + + if (!max_val.empty() && i >= max_hot) + match_max.push_back(vec_eq(max_val, state)); + } + + int min_matched = min_hot ? vec_reduce_or(match_min) : CONST_TRUE; + int max_matched = vec_reduce_or(match_max); + + return AND(min_matched, NOT(max_matched)); +} +#endif int ezSAT::ordered(const std::vector<int> &vec1, const std::vector<int> &vec2, bool allow_equal) { diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index bed6326e2..4925defe3 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -5350,7 +5350,7 @@ never transition from a non-zero value to a zero value. For this proof we create the following template (test.tpl). - ; we need QF_UFBV for this poof + ; we need QF_UFBV for this proof (set-logic QF_UFBV) ; insert the auto-generated code here diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 20b38bf8e..60f20fa6d 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -1,4 +1,5 @@ +OBJS += passes/cmds/exec.o OBJS += passes/cmds/add.o OBJS += passes/cmds/delete.o OBJS += passes/cmds/design.o diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 7b76f3d4a..91f8c2add 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -42,9 +42,9 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const } else { RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype); - formal_cell->setPort(ID(A), wire); + formal_cell->setPort(ID::A, wire); if(enable_name == "") { - formal_cell->setPort(ID(EN), State::S1); + formal_cell->setPort(ID::EN, State::S1); log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str()); } else { @@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const if(enable_wire == nullptr) log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str()); - formal_cell->setPort(ID(EN), enable_wire); + formal_cell->setPort(ID::EN, enable_wire); log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str()); } } @@ -206,19 +206,23 @@ struct AddPass : public Pass { extra_args(args, argidx, design); + bool selected_anything = false; for (auto module : design->modules()) { log_assert(module != nullptr); if (!design->selected_whole_module(module->name)) continue; - if (module->get_bool_attribute("\\blackbox")) + if (module->get_bool_attribute(ID::blackbox)) continue; + selected_anything = true; if (is_formal_celltype(command)) add_formal(module, command, arg_name, enable_name); else if (command == "wire") add_wire(design, module, arg_name, arg_width, arg_flag_input, arg_flag_output, arg_flag_global); } + if (!selected_anything) + log_warning("No modules selected, or only blackboxes. Nothing was added.\n"); } } AddPass; diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc index d09ed872e..5c0405f15 100644 --- a/passes/cmds/blackbox.cc +++ b/passes/cmds/blackbox.cc @@ -73,7 +73,7 @@ struct BlackboxPass : public Pass { module->remove(remove_wires); - module->set_bool_attribute("\\blackbox"); + module->set_bool_attribute(ID::blackbox); } } } BlackboxPass; diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 5a47988ec..ad6a07fa0 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -114,8 +114,8 @@ struct BugpointPass : public Pass { return design; RTLIL::Design *design_copy = new RTLIL::Design; - for (auto &it : design->modules_) - design_copy->add(it.second->clone()); + for (auto module : design->modules()) + design_copy->add(module->clone()); Pass::call(design_copy, "proc_clean -quiet"); Pass::call(design_copy, "clean -purge"); @@ -127,21 +127,21 @@ struct BugpointPass : public Pass { RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool assigns, bool updates) { RTLIL::Design *design_copy = new RTLIL::Design; - for (auto &it : design->modules_) - design_copy->add(it.second->clone()); + for (auto module : design->modules()) + design_copy->add(module->clone()); int index = 0; if (modules) { - for (auto &it : design_copy->modules_) + for (auto module : design_copy->modules()) { - if (it.second->get_blackbox_attribute()) + if (module->get_blackbox_attribute()) continue; if (index++ == seed) { - log("Trying to remove module %s.\n", it.first.c_str()); - design_copy->remove(it.second); + log("Trying to remove module %s.\n", module->name.c_str()); + design_copy->remove(module); return design_copy; } } @@ -155,7 +155,7 @@ struct BugpointPass : public Pass { for (auto wire : mod->wires()) { - if (!stage2 && wire->get_bool_attribute("$bugpoint")) + if (!stage2 && wire->get_bool_attribute(ID($bugpoint))) continue; if (wire->port_input || wire->port_output) @@ -178,12 +178,12 @@ struct BugpointPass : public Pass { if (mod->get_blackbox_attribute()) continue; - for (auto &it : mod->cells_) + for (auto cell : mod->cells()) { if (index++ == seed) { - log("Trying to remove cell %s.%s.\n", mod->name.c_str(), it.first.c_str()); - mod->remove(it.second); + log("Trying to remove cell %s.%s.\n", mod->name.c_str(), cell->name.c_str()); + mod->remove(cell); return design_copy; } } @@ -220,7 +220,7 @@ struct BugpointPass : public Pass { { log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str()); RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size()); - wire->set_bool_attribute("$bugpoint"); + wire->set_bool_attribute(ID($bugpoint)); wire->port_input = cell->input(it.first); wire->port_output = cell->output(it.first); cell->unsetPort(it.first); @@ -285,7 +285,7 @@ struct BugpointPass : public Pass { } } } - return NULL; + return nullptr; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -433,8 +433,8 @@ struct BugpointPass : public Pass { { Pass::call(design, "design -reset"); crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true); - for (auto &it : crashing_design->modules_) - design->add(it.second->clone()); + for (auto module : crashing_design->modules()) + design->add(module->clone()); delete crashing_design; } } diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 820ecac7b..63703b848 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -99,47 +99,47 @@ struct CheckPass : public Pass { log_header(design, "Executing CHECK pass (checking for obvious problems).\n"); pool<IdString> fftypes; - fftypes.insert("$sr"); - fftypes.insert("$ff"); - fftypes.insert("$dff"); - fftypes.insert("$dffe"); - fftypes.insert("$dffsr"); - fftypes.insert("$adff"); - fftypes.insert("$dlatch"); - fftypes.insert("$dlatchsr"); - fftypes.insert("$_DFFE_NN_"); - fftypes.insert("$_DFFE_NP_"); - fftypes.insert("$_DFFE_PN_"); - fftypes.insert("$_DFFE_PP_"); - fftypes.insert("$_DFFSR_NNN_"); - fftypes.insert("$_DFFSR_NNP_"); - fftypes.insert("$_DFFSR_NPN_"); - fftypes.insert("$_DFFSR_NPP_"); - fftypes.insert("$_DFFSR_PNN_"); - fftypes.insert("$_DFFSR_PNP_"); - fftypes.insert("$_DFFSR_PPN_"); - fftypes.insert("$_DFFSR_PPP_"); - fftypes.insert("$_DFF_NN0_"); - fftypes.insert("$_DFF_NN1_"); - fftypes.insert("$_DFF_NP0_"); - fftypes.insert("$_DFF_NP1_"); - fftypes.insert("$_DFF_N_"); - fftypes.insert("$_DFF_PN0_"); - fftypes.insert("$_DFF_PN1_"); - fftypes.insert("$_DFF_PP0_"); - fftypes.insert("$_DFF_PP1_"); - fftypes.insert("$_DFF_P_"); - fftypes.insert("$_DLATCHSR_NNN_"); - fftypes.insert("$_DLATCHSR_NNP_"); - fftypes.insert("$_DLATCHSR_NPN_"); - fftypes.insert("$_DLATCHSR_NPP_"); - fftypes.insert("$_DLATCHSR_PNN_"); - fftypes.insert("$_DLATCHSR_PNP_"); - fftypes.insert("$_DLATCHSR_PPN_"); - fftypes.insert("$_DLATCHSR_PPP_"); - fftypes.insert("$_DLATCH_N_"); - fftypes.insert("$_DLATCH_P_"); - fftypes.insert("$_FF_"); + fftypes.insert(ID($sr)); + fftypes.insert(ID($ff)); + fftypes.insert(ID($dff)); + fftypes.insert(ID($dffe)); + fftypes.insert(ID($dffsr)); + fftypes.insert(ID($adff)); + fftypes.insert(ID($dlatch)); + fftypes.insert(ID($dlatchsr)); + fftypes.insert(ID($_DFFE_NN_)); + fftypes.insert(ID($_DFFE_NP_)); + fftypes.insert(ID($_DFFE_PN_)); + fftypes.insert(ID($_DFFE_PP_)); + fftypes.insert(ID($_DFFSR_NNN_)); + fftypes.insert(ID($_DFFSR_NNP_)); + fftypes.insert(ID($_DFFSR_NPN_)); + fftypes.insert(ID($_DFFSR_NPP_)); + fftypes.insert(ID($_DFFSR_PNN_)); + fftypes.insert(ID($_DFFSR_PNP_)); + fftypes.insert(ID($_DFFSR_PPN_)); + fftypes.insert(ID($_DFFSR_PPP_)); + fftypes.insert(ID($_DFF_NN0_)); + fftypes.insert(ID($_DFF_NN1_)); + fftypes.insert(ID($_DFF_NP0_)); + fftypes.insert(ID($_DFF_NP1_)); + fftypes.insert(ID($_DFF_N_)); + fftypes.insert(ID($_DFF_PN0_)); + fftypes.insert(ID($_DFF_PN1_)); + fftypes.insert(ID($_DFF_PP0_)); + fftypes.insert(ID($_DFF_PP1_)); + fftypes.insert(ID($_DFF_P_)); + fftypes.insert(ID($_DLATCHSR_NNN_)); + fftypes.insert(ID($_DLATCHSR_NNP_)); + fftypes.insert(ID($_DLATCHSR_NPN_)); + fftypes.insert(ID($_DLATCHSR_NPP_)); + fftypes.insert(ID($_DLATCHSR_PNN_)); + fftypes.insert(ID($_DLATCHSR_PNP_)); + fftypes.insert(ID($_DLATCHSR_PPN_)); + fftypes.insert(ID($_DLATCHSR_PPP_)); + fftypes.insert(ID($_DLATCH_N_)); + fftypes.insert(ID($_DLATCH_P_)); + fftypes.insert(ID($_FF_)); for (auto module : design->selected_whole_modules_warn()) { @@ -202,8 +202,8 @@ struct CheckPass : public Pass { if (wire->port_input && !wire->port_output) for (auto bit : sigmap(wire)) if (bit.wire) wire_drivers_count[bit]++; - if (wire->attributes.count("\\init")) { - Const initval = wire->attributes.at("\\init"); + if (wire->attributes.count(ID::init)) { + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) if (initval[i] == State::S0 || initval[i] == State::S1) init_bits.insert(sigmap(SigBit(wire, i))); @@ -245,7 +245,7 @@ struct CheckPass : public Pass { if (fftypes.count(cell->type) == 0) continue; - for (auto bit : sigmap(cell->getPort("\\Q"))) + for (auto bit : sigmap(cell->getPort(ID::Q))) init_bits.erase(bit); } diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index 7e32da65f..d6e7f2ccf 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -77,23 +77,23 @@ struct ChformalPass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-assert") { - constr_types.insert("$assert"); + constr_types.insert(ID($assert)); continue; } if (args[argidx] == "-assume") { - constr_types.insert("$assume"); + constr_types.insert(ID($assume)); continue; } if (args[argidx] == "-live") { - constr_types.insert("$live"); + constr_types.insert(ID($live)); continue; } if (args[argidx] == "-fair") { - constr_types.insert("$fair"); + constr_types.insert(ID($fair)); continue; } if (args[argidx] == "-cover") { - constr_types.insert("$cover"); + constr_types.insert(ID($cover)); continue; } if (mode == 0 && args[argidx] == "-remove") { @@ -139,11 +139,11 @@ struct ChformalPass : public Pass { extra_args(args, argidx, design); if (constr_types.empty()) { - constr_types.insert("$assert"); - constr_types.insert("$assume"); - constr_types.insert("$live"); - constr_types.insert("$fair"); - constr_types.insert("$cover"); + constr_types.insert(ID($assert)); + constr_types.insert(ID($assume)); + constr_types.insert(ID($live)); + constr_types.insert(ID($fair)); + constr_types.insert(ID($cover)); } if (mode == 0) @@ -171,11 +171,11 @@ struct ChformalPass : public Pass { for (auto wire : module->wires()) { - if (wire->attributes.count("\\init") == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec initsig = sigmap(wire); - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) { if (initval[i] == State::S0) @@ -187,17 +187,17 @@ struct ChformalPass : public Pass { for (auto cell : module->selected_cells()) { - if (cell->type == "$ff") { - SigSpec D = sigmap(cell->getPort("\\D")); - SigSpec Q = sigmap(cell->getPort("\\Q")); + if (cell->type == ID($ff)) { + SigSpec D = sigmap(cell->getPort(ID::D)); + SigSpec Q = sigmap(cell->getPort(ID::Q)); for (int i = 0; i < GetSize(D); i++) ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false)); } - if (cell->type == "$dff") { - SigSpec D = sigmap(cell->getPort("\\D")); - SigSpec Q = sigmap(cell->getPort("\\Q")); - SigSpec C = sigmap(cell->getPort("\\CLK")); - bool clockpol = cell->getParam("\\CLK_POLARITY").as_bool(); + if (cell->type == ID($dff)) { + SigSpec D = sigmap(cell->getPort(ID::D)); + SigSpec Q = sigmap(cell->getPort(ID::Q)); + SigSpec C = sigmap(cell->getPort(ID::CLK)); + bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool(); for (int i = 0; i < GetSize(D); i++) ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol)); } @@ -206,15 +206,15 @@ struct ChformalPass : public Pass { for (auto cell : constr_cells) while (true) { - SigSpec A = sigmap(cell->getPort("\\A")); - SigSpec EN = sigmap(cell->getPort("\\EN")); + SigSpec A = sigmap(cell->getPort(ID::A)); + SigSpec EN = sigmap(cell->getPort(ID::EN)); if (ffmap.count(A) == 0 || ffmap.count(EN) == 0) break; if (!init_zero.count(EN)) { - if (cell->type == "$cover") break; - if (cell->type.in("$assert", "$assume") && !init_one.count(A)) break; + if (cell->type == ID($cover)) break; + if (cell->type.in(ID($assert), ID($assume)) && !init_one.count(A)) break; } const auto &A_map = ffmap.at(A); @@ -223,8 +223,8 @@ struct ChformalPass : public Pass { if (A_map.second != EN_map.second) break; - cell->setPort("\\A", A_map.first); - cell->setPort("\\EN", EN_map.first); + cell->setPort(ID::A, A_map.first); + cell->setPort(ID::EN, EN_map.first); } } else @@ -233,18 +233,18 @@ struct ChformalPass : public Pass { for (auto cell : constr_cells) for (int i = 0; i < mode_arg; i++) { - SigSpec orig_a = cell->getPort("\\A"); - SigSpec orig_en = cell->getPort("\\EN"); + SigSpec orig_a = cell->getPort(ID::A); + SigSpec orig_en = cell->getPort(ID::EN); Wire *new_a = module->addWire(NEW_ID); Wire *new_en = module->addWire(NEW_ID); - new_en->attributes["\\init"] = State::S0; + new_en->attributes[ID::init] = State::S0; module->addFf(NEW_ID, orig_a, new_a); module->addFf(NEW_ID, orig_en, new_en); - cell->setPort("\\A", new_a); - cell->setPort("\\EN", new_en); + cell->setPort(ID::A, new_a); + cell->setPort(ID::EN, new_en); } } else @@ -254,26 +254,26 @@ struct ChformalPass : public Pass { for (int i = 0; i < mode_arg; i++) { Wire *w = module->addWire(NEW_ID); - w->attributes["\\init"] = State::S0; + w->attributes[ID::init] = State::S0; module->addFf(NEW_ID, en, w); en = w; } for (auto cell : constr_cells) - cell->setPort("\\EN", module->LogicAnd(NEW_ID, en, cell->getPort("\\EN"))); + cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN))); } else if (mode == 'c') { for (auto cell : constr_cells) - if (assert2assume && cell->type == "$assert") - cell->type = "$assume"; - else if (assume2assert && cell->type == "$assume") - cell->type = "$assert"; - else if (live2fair && cell->type == "$live") - cell->type = "$fair"; - else if (fair2live && cell->type == "$fair") - cell->type = "$live"; + if (assert2assume && cell->type == ID($assert)) + cell->type = ID($assume); + else if (assume2assert && cell->type == ID($assume)) + cell->type = ID($assert); + else if (live2fair && cell->type == ID($live)) + cell->type = ID($fair); + else if (fair2live && cell->type == ID($fair)) + cell->type = ID($live); } } } diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 5a15cbbaf..6ae7c9304 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -65,15 +65,13 @@ struct ConnwrappersWorker decls[key] = decl; } - void work(RTLIL::Design *design, RTLIL::Module *module) + void work(RTLIL::Module *module) { std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map; SigMap sigmap(module); - for (auto &it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = it.second; - if (!decl_celltypes.count(cell->type)) continue; @@ -105,13 +103,8 @@ struct ConnwrappersWorker } } - for (auto &it : module->cells_) + for (auto cell : module->selected_cells()) { - RTLIL::Cell *cell = it.second; - - if (!design->selected(module, cell)) - continue; - for (auto &conn : cell->connections_) { std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector(); @@ -141,8 +134,8 @@ struct ConnwrappersWorker } if (old_sig.size()) - log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), - RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second)); + log("Connected extended bits of %s.%s:%s: %s -> %s\n", log_id(module->name), log_id(cell->name), + log_id(conn.first), log_signal(old_sig), log_signal(conn.second)); } } } @@ -200,9 +193,8 @@ struct ConnwrappersPass : public Pass { log_header(design, "Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n"); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - worker.work(design, mod_it.second); + for (auto module : design->selected_modules()) + worker.work(module); } } ConnwrappersPass; diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index acd2dba52..99f1f69cf 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -44,10 +44,10 @@ struct CopyPass : public Pass { std::string src_name = RTLIL::escape_id(args[1]); std::string trg_name = RTLIL::escape_id(args[2]); - if (design->modules_.count(src_name) == 0) + if (design->module(src_name) == nullptr) log_cmd_error("Can't find source module %s.\n", src_name.c_str()); - if (design->modules_.count(trg_name) != 0) + if (design->module(trg_name) != nullptr) log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); RTLIL::Module *new_mod = design->module(src_name)->clone(); diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 5822c09f8..b124e3b0f 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -65,27 +65,24 @@ struct DeletePass : public Pass { } extra_args(args, argidx, design); - std::vector<RTLIL::IdString> delete_mods; - - for (auto &mod_it : design->modules_) + std::vector<RTLIL::Module *> delete_mods; + for (auto module : design->modules()) { - if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) { - delete_mods.push_back(mod_it.first); + if (design->selected_whole_module(module->name) && !flag_input && !flag_output) { + delete_mods.push_back(module); continue; } - if (!design->selected_module(mod_it.first)) + if (!design->selected_module(module->name)) continue; - RTLIL::Module *module = mod_it.second; - if (flag_input || flag_output) { - for (auto &it : module->wires_) - if (design->selected(module, it.second)) { + for (auto wire : module->wires()) + if (design->selected(module, wire)) { if (flag_input) - it.second->port_input = false; + wire->port_input = false; if (flag_output) - it.second->port_output = false; + wire->port_output = false; } module->fixup_ports(); continue; @@ -96,20 +93,19 @@ struct DeletePass : public Pass { pool<RTLIL::IdString> delete_procs; pool<RTLIL::IdString> delete_mems; - for (auto &it : module->wires_) - if (design->selected(module, it.second)) - delete_wires.insert(it.second); + for (auto wire : module->selected_wires()) + delete_wires.insert(wire); for (auto &it : module->memories) if (design->selected(module, it.second)) delete_mems.insert(it.first); - for (auto &it : module->cells_) { - if (design->selected(module, it.second)) - delete_cells.insert(it.second); - if (it.second->type.in("$memrd", "$memwr") && - delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0) - delete_cells.insert(it.second); + for (auto cell : module->cells()) { + if (design->selected(module, cell)) + delete_cells.insert(cell); + if (cell->type.in(ID($memrd), ID($memwr)) && + delete_mems.count(cell->parameters.at(ID::MEMID).decode_string()) != 0) + delete_cells.insert(cell); } for (auto &it : module->processes) @@ -134,9 +130,8 @@ struct DeletePass : public Pass { module->fixup_ports(); } - for (auto &it : delete_mods) { - delete design->modules_.at(it); - design->modules_.erase(it); + for (auto mod : delete_mods) { + design->remove(mod); } } } DeletePass; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 172addcc1..4612760cc 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "frontends/verilog/preproc.h" #include "frontends/ast/ast.h" YOSYS_NAMESPACE_BEGIN @@ -59,6 +60,11 @@ struct DesignPass : public Pass { log("Push the current design to the stack and then clear the current design.\n"); log("\n"); log("\n"); + log(" design -push-copy\n"); + log("\n"); + log("Push the current design to the stack without clearing the current design.\n"); + log("\n"); + log("\n"); log(" design -pop\n"); log("\n"); log("Reset the current design and pop the last design from the stack.\n"); @@ -100,6 +106,7 @@ struct DesignPass : public Pass { bool reset_mode = false; bool reset_vlog_mode = false; bool push_mode = false; + bool push_copy_mode = false; bool pop_mode = false; bool import_mode = false; RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL; @@ -125,6 +132,11 @@ struct DesignPass : public Pass { push_mode = true; continue; } + if (!got_mode && args[argidx] == "-push-copy") { + got_mode = true; + push_copy_mode = true; + continue; + } if (!got_mode && args[argidx] == "-pop") { got_mode = true; pop_mode = true; @@ -194,19 +206,19 @@ struct DesignPass : public Pass { argidx = args.size(); } - for (auto &it : copy_from_design->modules_) { - if (sel.selected_whole_module(it.first)) { - copy_src_modules.push_back(it.second); + for (auto mod : copy_from_design->modules()) { + if (sel.selected_whole_module(mod->name)) { + copy_src_modules.push_back(mod); continue; } - if (sel.selected_module(it.first)) - log_cmd_error("Module %s is only partly selected.\n", RTLIL::id2cstr(it.first)); + if (sel.selected_module(mod->name)) + log_cmd_error("Module %s is only partly selected.\n", log_id(mod->name)); } if (import_mode) { for (auto module : copy_src_modules) { - if (module->get_bool_attribute("\\top")) { + if (module->get_bool_attribute(ID::top)) { copy_src_modules.clear(); copy_src_modules.push_back(module); break; @@ -230,8 +242,8 @@ struct DesignPass : public Pass { pool<Module*> queue; dict<IdString, IdString> done; - if (copy_to_design->modules_.count(prefix)) - delete copy_to_design->modules_.at(prefix); + if (copy_to_design->module(prefix) != nullptr) + copy_to_design->remove(copy_to_design->module(prefix)); if (GetSize(copy_src_modules) != 1) log_cmd_error("No top module found in source design.\n"); @@ -240,12 +252,13 @@ struct DesignPass : public Pass { { log("Importing %s as %s.\n", log_id(mod), log_id(prefix)); - copy_to_design->modules_[prefix] = mod->clone(); - copy_to_design->modules_[prefix]->name = prefix; - copy_to_design->modules_[prefix]->design = copy_to_design; - copy_to_design->modules_[prefix]->attributes.erase("\\top"); + RTLIL::Module *t = mod->clone(); + t->name = prefix; + t->design = copy_to_design; + t->attributes.erase(ID::top); + copy_to_design->add(t); - queue.insert(copy_to_design->modules_[prefix]); + queue.insert(t); done[mod->name] = prefix; } @@ -268,15 +281,16 @@ struct DesignPass : public Pass { log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name)); - if (copy_to_design->modules_.count(trg_name)) - delete copy_to_design->modules_.at(trg_name); + if (copy_to_design->module(trg_name) != nullptr) + copy_to_design->remove(copy_to_design->module(trg_name)); - copy_to_design->modules_[trg_name] = fmod->clone(); - copy_to_design->modules_[trg_name]->name = trg_name; - copy_to_design->modules_[trg_name]->design = copy_to_design; - copy_to_design->modules_[trg_name]->attributes.erase("\\top"); + RTLIL::Module *t = fmod->clone(); + t->name = trg_name; + t->design = copy_to_design; + t->attributes.erase(ID::top); + copy_to_design->add(t); - queue.insert(copy_to_design->modules_[trg_name]); + queue.insert(t); done[cell->type] = trg_name; } @@ -294,21 +308,22 @@ struct DesignPass : public Pass { { std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name); - if (copy_to_design->modules_.count(trg_name)) - delete copy_to_design->modules_.at(trg_name); + if (copy_to_design->module(trg_name) != nullptr) + copy_to_design->remove(copy_to_design->module(trg_name)); - copy_to_design->modules_[trg_name] = mod->clone(); - copy_to_design->modules_[trg_name]->name = trg_name; - copy_to_design->modules_[trg_name]->design = copy_to_design; + RTLIL::Module *t = mod->clone(); + t->name = trg_name; + t->design = copy_to_design; + copy_to_design->add(t); } } - if (!save_name.empty() || push_mode) + if (!save_name.empty() || push_mode || push_copy_mode) { RTLIL::Design *design_copy = new RTLIL::Design; - for (auto &it : design->modules_) - design_copy->add(it.second->clone()); + for (auto mod : design->modules()) + design_copy->add(mod->clone()); design_copy->selection_stack = design->selection_stack; design_copy->selection_vars = design->selection_vars; @@ -317,7 +332,7 @@ struct DesignPass : public Pass { if (saved_designs.count(save_name)) delete saved_designs.at(save_name); - if (push_mode) + if (push_mode || push_copy_mode) pushed_designs.push_back(design_copy); else saved_designs[save_name] = design_copy; @@ -325,9 +340,8 @@ struct DesignPass : public Pass { if (reset_mode || !load_name.empty() || push_mode || pop_mode) { - for (auto &it : design->modules_) - delete it.second; - design->modules_.clear(); + for (auto mod : design->modules()) + design->remove(mod); design->selection_stack.clear(); design->selection_vars.clear(); @@ -346,15 +360,15 @@ struct DesignPass : public Pass { delete node; design->verilog_globals.clear(); - design->verilog_defines.clear(); + design->verilog_defines->clear(); } if (!load_name.empty() || pop_mode) { RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name); - for (auto &it : saved_design->modules_) - design->add(it.second->clone()); + for (auto mod : saved_design->modules()) + design->add(mod->clone()); design->selection_stack = saved_design->selection_stack; design->selection_vars = saved_design->selection_vars; diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc new file mode 100644 index 000000000..7eeefe705 --- /dev/null +++ b/passes/cmds/exec.cc @@ -0,0 +1,205 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/log.h" +#include <cstdio> + +#if defined(_WIN32) +# include <csignal> +# define WIFEXITED(x) 1 +# define WIFSIGNALED(x) 0 +# define WIFSTOPPED(x) 0 +# define WEXITSTATUS(x) ((x) & 0xff) +# define WTERMSIG(x) SIGTERM +# define WSTOPSIG(x) 0 +#else +# include <sys/wait.h> +#endif + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct ExecPass : public Pass { + ExecPass() : Pass("exec", "execute commands in the operating system shell") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" exec [options] -- [command]\n"); + log("\n"); + log("Execute a command in the operating system shell. All supplied arguments are\n"); + log("concatenated and passed as a command to popen(3). Whitespace is not guaranteed\n"); + log("to be preserved, even if quoted. stdin and stderr are not connected, while stdout is\n"); + log("logged unless the \"-q\" option is specified.\n"); + log("\n"); + log("\n"); + log(" -q\n"); + log(" Suppress stdout and stderr from subprocess\n"); + log("\n"); + log(" -expect-return <int>\n"); + log(" Generate an error if popen() does not return specified value.\n"); + log(" May only be specified once; the final specified value is controlling\n"); + log(" if specified multiple times.\n"); + log("\n"); + log(" -expect-stdout <regex>\n"); + log(" Generate an error if the specified regex does not match any line\n"); + log(" in subprocess's stdout. May be specified multiple times.\n"); + log("\n"); + log(" -not-expect-stdout <regex>\n"); + log(" Generate an error if the specified regex matches any line\n"); + log(" in subprocess's stdout. May be specified multiple times.\n"); + log("\n"); + log("\n"); + log(" Example: exec -q -expect-return 0 -- echo \"bananapie\" | grep \"nana\"\n"); + log("\n"); + log("\n"); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + std::string cmd = ""; + char buf[1024] = {}; + std::string linebuf = ""; + bool flag_cmd = false; + bool flag_quiet = false; + bool flag_expect_return = false; + int expect_return_value = 0; + bool flag_expect_stdout = false; + struct expect_stdout_elem { + bool matched; + bool polarity; //true: this regex must match at least one line + //false: this regex must not match any line + std::string str; + YS_REGEX_TYPE re; + + expect_stdout_elem() : matched(false), polarity(true), str(), re(){}; + }; + std::vector<expect_stdout_elem> expect_stdout; + + if(args.size() == 0) + log_cmd_error("No command provided.\n"); + + for(size_t argidx = 1; argidx < args.size(); ++argidx) { + if (flag_cmd) { + cmd += args[argidx] + (argidx != (args.size() - 1)? " " : ""); + } else { + if (args[argidx] == "--") + flag_cmd = true; + else if (args[argidx] == "-q") + flag_quiet = true; + else if (args[argidx] == "-expect-return") { + flag_expect_return = true; + ++argidx; + if (argidx >= args.size()) + log_cmd_error("No expected return value specified.\n"); + + expect_return_value = atoi(args[argidx].c_str()); + } else if (args[argidx] == "-expect-stdout") { + flag_expect_stdout = true; + ++argidx; + if (argidx >= args.size()) + log_cmd_error("No expected regular expression specified.\n"); + + try{ + expect_stdout_elem x; + x.str = args[argidx]; + x.re = YS_REGEX_COMPILE(args[argidx]); + expect_stdout.push_back(x); + } catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + } + } else if (args[argidx] == "-not-expect-stdout") { + flag_expect_stdout = true; + ++argidx; + if (argidx >= args.size()) + log_cmd_error("No expected regular expression specified.\n"); + + try{ + expect_stdout_elem x; + x.str = args[argidx]; + x.re = YS_REGEX_COMPILE(args[argidx]); + x.polarity = false; + expect_stdout.push_back(x); + } catch (const YS_REGEX_NS::regex_error& e) { + log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + } + + } else + log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.", args[argidx].c_str()); + } + } + + log_header(design, "Executing command \"%s\".\n", cmd.c_str()); + log_push(); + + fflush(stdout); + bool keep_reading = true; + int status = 0; + int retval = 0; + +#ifndef EMSCRIPTEN + FILE *f = popen(cmd.c_str(), "r"); + if (f == nullptr) + log_cmd_error("errno %d after popen() returned NULL.\n", errno); + while (keep_reading) { + keep_reading = (fgets(buf, sizeof(buf), f) != nullptr); + linebuf += buf; + memset(buf, 0, sizeof(buf)); + + auto pos = linebuf.find('\n'); + while (pos != std::string::npos) { + std::string line = linebuf.substr(0, pos); + linebuf.erase(0, pos + 1); + if (!flag_quiet) + log("%s\n", line.c_str()); + + if (flag_expect_stdout) + for(auto &x : expect_stdout) + if (YS_REGEX_NS::regex_search(line, x.re)) + x.matched = true; + + pos = linebuf.find('\n'); + } + } + status = pclose(f); +#endif + + if(WIFEXITED(status)) { + retval = WEXITSTATUS(status); + } + else if(WIFSIGNALED(status)) { + retval = WTERMSIG(status); + } + else if(WIFSTOPPED(status)) { + retval = WSTOPSIG(status); + } + + if (flag_expect_return && retval != expect_return_value) + log_cmd_error("Return value %d did not match expected return value %d.\n", retval, expect_return_value); + + if (flag_expect_stdout) + for (auto &x : expect_stdout) + if (x.polarity ^ x.matched) + log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str.c_str()); + + log_pop(); + } +} ExecPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc index adbe89e31..b178ef951 100644 --- a/passes/cmds/qwp.cc +++ b/passes/cmds/qwp.cc @@ -737,7 +737,7 @@ struct QwpWorker for (auto &node : nodes) if (node.cell != nullptr) - node.cell->attributes["\\qwp_position"] = stringf("%f %f", node.pos, node.alt_pos); + node.cell->attributes[ID::qwp_position] = stringf("%f %f", node.pos, node.alt_pos); vector<double> edge_lengths; vector<double> weighted_edge_lengths; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 1657ef818..b64b077e4 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -625,9 +625,13 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se } } -static void select_stmt(RTLIL::Design *design, std::string arg) +static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_empty_warning = false) { std::string arg_mod, arg_memb; + std::unordered_map<std::string, bool> arg_mod_found; + std::unordered_map<std::string, bool> arg_memb_found; + auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); }; + bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':'; if (arg.size() == 0) return; @@ -758,19 +762,21 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (!design->selected_active_module.empty()) { arg_mod = design->selected_active_module; arg_memb = arg; + if (!prefixed) arg_memb_found[arg_memb] = false; } else - if (GetSize(arg) >= 2 && arg[0] >= 'a' && arg[0] <= 'z' && arg[1] == ':') { + if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') { arg_mod = "*", arg_memb = arg; } else { size_t pos = arg.find('/'); if (pos == std::string::npos) { - if (arg.find(':') == std::string::npos || arg.compare(0, 1, "A") == 0) - arg_mod = arg; - else - arg_mod = "*", arg_memb = arg; + arg_mod = arg; + if (!prefixed) arg_mod_found[arg_mod] = false; } else { arg_mod = arg.substr(0, pos); + if (!prefixed) arg_mod_found[arg_mod] = false; arg_memb = arg.substr(pos+1); + bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':'; + if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false; } } @@ -789,8 +795,14 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (!match_attr(mod->attributes, arg_mod.substr(2))) continue; } else + if (arg_mod.compare(0, 2, "N:") == 0) { + if (!match_ids(mod->name, arg_mod.substr(2))) + continue; + } else if (!match_ids(mod->name, arg_mod)) continue; + else + arg_mod_found[arg_mod] = true; if (arg_memb == "") { sel.selected_modules.insert(mod->name); @@ -839,7 +851,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.compare(0, 2, "c:") ==0) { + if (arg_memb.compare(0, 2, "c:") == 0) { for (auto cell : mod->cells()) if (match_ids(cell->name, arg_memb.substr(2))) sel.selected_members[mod->name].insert(cell->name); @@ -873,24 +885,44 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (match_attr(cell->parameters, arg_memb.substr(2))) sel.selected_members[mod->name].insert(cell->name); } else { + std::string orig_arg_memb = arg_memb; if (arg_memb.compare(0, 2, "n:") == 0) arg_memb = arg_memb.substr(2); for (auto wire : mod->wires()) - if (match_ids(wire->name, arg_memb)) + if (match_ids(wire->name, arg_memb)) { sel.selected_members[mod->name].insert(wire->name); + arg_memb_found[orig_arg_memb] = true; + } for (auto &it : mod->memories) - if (match_ids(it.first, arg_memb)) + if (match_ids(it.first, arg_memb)) { sel.selected_members[mod->name].insert(it.first); + arg_memb_found[orig_arg_memb] = true; + } for (auto cell : mod->cells()) - if (match_ids(cell->name, arg_memb)) + if (match_ids(cell->name, arg_memb)) { sel.selected_members[mod->name].insert(cell->name); + arg_memb_found[orig_arg_memb] = true; + } for (auto &it : mod->processes) - if (match_ids(it.first, arg_memb)) + if (match_ids(it.first, arg_memb)) { sel.selected_members[mod->name].insert(it.first); + arg_memb_found[orig_arg_memb] = true; + } } } select_filter_active_mod(design, work_stack.back()); + + for (auto &it : arg_mod_found) { + if (it.second == false && !disable_empty_warning) { + log_warning("Selection \"%s\" did not match any module.\n", it.first.c_str()); + } + } + for (auto &it : arg_memb_found) { + if (it.second == false && !disable_empty_warning) { + log_warning("Selection \"%s\" did not match any object.\n", it.first.c_str()); + } + } } static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel) @@ -1074,6 +1106,10 @@ struct SelectPass : public Pass { log(" all modules with an attribute matching the given pattern\n"); log(" in addition to = also <, <=, >=, and > are supported\n"); log("\n"); + log(" N:<pattern>\n"); + log(" all modules with a name matching the given pattern\n"); + log(" (i.e. 'N:' is optional as it is the default matching rule)\n"); + log("\n"); log("An <obj_pattern> can be an object name, wildcard expression, or one of\n"); log("the following:\n"); log("\n"); @@ -1276,7 +1312,8 @@ struct SelectPass : public Pass { } if (arg.size() > 0 && arg[0] == '-') log_cmd_error("Unknown option %s.\n", arg.c_str()); - select_stmt(design, arg); + bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1); + select_stmt(design, arg, disable_empty_warning); sel_str += " " + arg; } diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 1ccfc2e86..515f5a4ef 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -38,7 +38,7 @@ struct setunset_t value = RTLIL::Const(set_value.substr(1, GetSize(set_value)-2)); } else { RTLIL::SigSpec sig_value; - if (!RTLIL::SigSpec::parse(sig_value, NULL, set_value)) + if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value)) log_cmd_error("Can't decode value '%s'!\n", set_value.c_str()); value = sig_value.as_const(); } @@ -96,10 +96,8 @@ struct SetattrPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules_) + for (auto module : design->modules()) { - RTLIL::Module *module = mod.second; - if (flag_mod) { if (design->selected_whole_module(module->name)) do_setunset(module->attributes, setunset_list); @@ -109,17 +107,17 @@ struct SetattrPass : public Pass { if (!design->selected(module)) continue; - for (auto &it : module->wires_) - if (design->selected(module, it.second)) - do_setunset(it.second->attributes, setunset_list); + for (auto wire : module->wires()) + if (design->selected(module, wire)) + do_setunset(wire->attributes, setunset_list); for (auto &it : module->memories) if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); - for (auto &it : module->cells_) - if (design->selected(module, it.second)) - do_setunset(it.second->attributes, setunset_list); + for (auto cell : module->cells()) + if (design->selected(module, cell)) + do_setunset(cell->attributes, setunset_list); for (auto &it : module->processes) if (design->selected(module, it.second)) @@ -159,10 +157,10 @@ struct WbflipPass : public Pass { if (!design->selected(module)) continue; - if (module->get_bool_attribute("\\blackbox")) + if (module->get_bool_attribute(ID::blackbox)) continue; - module->set_bool_attribute("\\whitebox", !module->get_bool_attribute("\\whitebox")); + module->set_bool_attribute(ID::whitebox, !module->get_bool_attribute(ID::whitebox)); } } } WbflipPass; @@ -208,19 +206,13 @@ struct SetparamPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules_) + for (auto module : design->selected_modules()) { - RTLIL::Module *module = mod.second; - - if (!design->selected(module)) - continue; - - for (auto &it : module->cells_) - if (design->selected(module, it.second)) { - if (!new_cell_type.empty()) - it.second->type = new_cell_type; - do_setunset(it.second->parameters, setunset_list); - } + for (auto cell : module->selected_cells()) { + if (!new_cell_type.empty()) + cell->type = new_cell_type; + do_setunset(cell->parameters, setunset_list); + } } } } SetparamPass; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 3eedc86b8..5afd40923 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -360,10 +360,10 @@ struct SetundefPass : public Pass { pool<Wire*> initwires; pool<IdString> fftypes; - fftypes.insert("$dff"); - fftypes.insert("$dffe"); - fftypes.insert("$dffsr"); - fftypes.insert("$adff"); + fftypes.insert(ID($dff)); + fftypes.insert(ID($dffe)); + fftypes.insert(ID($dffsr)); + fftypes.insert(ID($adff)); std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'}; @@ -389,7 +389,7 @@ struct SetundefPass : public Pass { if (!fftypes.count(cell->type)) continue; - for (auto bit : sigmap(cell->getPort("\\Q"))) + for (auto bit : sigmap(cell->getPort(ID::Q))) ffbits.insert(bit); } @@ -411,7 +411,7 @@ struct SetundefPass : public Pass { for (auto wire : initwires) { - Const &initval = wire->attributes["\\init"]; + Const &initval = wire->attributes[ID::init]; initval.bits.resize(GetSize(wire), State::Sx); for (int i = 0; i < GetSize(wire); i++) { @@ -423,7 +423,7 @@ struct SetundefPass : public Pass { } if (initval.is_fully_undef()) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); } initwires.clear(); @@ -439,14 +439,14 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; - if (!wire->attributes.count("\\init")) + if (!wire->attributes.count(ID::init)) continue; - Const &initval = wire->attributes["\\init"]; + Const &initval = wire->attributes[ID::init]; initval.bits.resize(GetSize(wire), State::Sx); if (initval.is_fully_undef()) { - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); continue; } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index e0d428811..155ed0fcd 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -41,8 +41,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -using RTLIL::id2cstr; - #undef CLUSTER_CELLS_AND_PORTBOXES struct ShowWorker @@ -101,7 +99,7 @@ struct ShowWorker { sig.sort_and_unify(); for (auto &c : sig.chunks()) { - if (c.wire != NULL) + if (c.wire != nullptr) for (auto &s : color_selections) if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0) return stringf("color=\"%s\"", s.first.c_str()); @@ -218,7 +216,7 @@ struct ShowWorker if (sig.is_chunk()) { const RTLIL::SigChunk &c = sig.as_chunk(); - if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { + if (c.wire != nullptr && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); } else { @@ -230,7 +228,7 @@ struct ShowWorker return std::string(); } - std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = NULL) + std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = nullptr) { std::string code; std::string net = gen_signode_simple(sig); @@ -287,7 +285,7 @@ struct ShowWorker else code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); } - if (node != NULL) + if (node != nullptr) *node = stringf("x%d", idx); } else @@ -300,7 +298,7 @@ struct ShowWorker net_conn_map[net].bits = sig.size(); net_conn_map[net].color = nextColor(sig, net_conn_map[net].color); } - if (node != NULL) + if (node != nullptr) *node = net; } return code; @@ -366,22 +364,20 @@ struct ShowWorker std::set<std::string> all_sources, all_sinks; std::map<std::string, std::string> wires_on_demand; - for (auto &it : module->wires_) { - if (!design->selected_member(module->name, it.first)) - continue; + for (auto wire : module->selected_wires()) { const char *shape = "diamond"; - if (it.second->port_input || it.second->port_output) + if (wire->port_input || wire->port_output) shape = "octagon"; - if (it.first[0] == '\\') { + if (wire->name[0] == '\\') { fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n", - id2num(it.first), shape, findLabel(it.first.str()), - nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str()); - if (it.second->port_input) - all_sources.insert(stringf("n%d", id2num(it.first))); - else if (it.second->port_output) - all_sinks.insert(stringf("n%d", id2num(it.first))); + id2num(wire->name), shape, findLabel(wire->name.str()), + nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str()); + if (wire->port_input) + all_sources.insert(stringf("n%d", id2num(wire->name))); + else if (wire->port_output) + all_sinks.insert(stringf("n%d", id2num(wire->name))); } else { - wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str(); + wires_on_demand[stringf("n%d", id2num(wire->name))] = wire->name.str(); } } @@ -398,15 +394,12 @@ struct ShowWorker fprintf(f, "}\n"); } - for (auto &it : module->cells_) + for (auto cell : module->selected_cells()) { - if (!design->selected_member(module->name, it.first)) - continue; - std::vector<RTLIL::IdString> in_ports, out_ports; - for (auto &conn : it.second->connections()) { - if (!ct.cell_output(it.second->type, conn.first)) + for (auto &conn : cell->connections()) { + if (!ct.cell_output(cell->type, conn.first)) in_ports.push_back(conn.first); else out_ports.push_back(conn.first); @@ -419,12 +412,12 @@ struct ShowWorker for (auto &p : in_ports) label_string += stringf("<p%d> %s%s|", id2num(p), escape(p.str()), - genSignedLabels && it.second->hasParam(p.str() + "_SIGNED") && - it.second->getParam(p.str() + "_SIGNED").as_bool() ? "*" : ""); + genSignedLabels && cell->hasParam(p.str() + "_SIGNED") && + cell->getParam(p.str() + "_SIGNED").as_bool() ? "*" : ""); if (label_string[label_string.size()-1] == '|') label_string = label_string.substr(0, label_string.size()-1); - label_string += stringf("}|%s\\n%s|{", findLabel(it.first.str()), escape(it.second->type.str())); + label_string += stringf("}|%s\\n%s|{", findLabel(cell->name.str()), escape(cell->type.str())); for (auto &p : out_ports) label_string += stringf("<p%d> %s|", id2num(p), escape(p.str())); @@ -434,19 +427,19 @@ struct ShowWorker label_string += "}}"; std::string code; - for (auto &conn : it.second->connections()) { - code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)), - conn.second, ct.cell_output(it.second->type, conn.first)); + for (auto &conn : cell->connections()) { + code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)), + conn.second, ct.cell_output(cell->type, conn.first)); } #ifdef CLUSTER_CELLS_AND_PORTBOXES if (!code.empty()) fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n", - id2num(it.first), id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str()); + id2num(cell->name), id2num(cell->name), label_string.c_str(), findColor(cell->name), code.c_str()); else #endif fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s", - id2num(it.first), label_string.c_str(), findColor(it.first.str()), code.c_str()); + id2num(cell->name), label_string.c_str(), findColor(cell->name.str()), code.c_str()); } for (auto &it : module->processes) @@ -482,8 +475,8 @@ struct ShowWorker } std::string proc_src = RTLIL::unescape_id(proc->name); - if (proc->attributes.count("\\src") > 0) - proc_src = proc->attributes.at("\\src").decode_string(); + if (proc->attributes.count(ID::src) > 0) + proc_src = proc->attributes.at(ID::src).decode_string(); fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name.str()), proc_src.c_str()); } @@ -491,12 +484,12 @@ struct ShowWorker { bool found_lhs_wire = false; for (auto &c : conn.first.chunks()) { - if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) + if (c.wire == nullptr || design->selected_member(module->name, c.wire->name)) found_lhs_wire = true; } bool found_rhs_wire = false; for (auto &c : conn.second.chunks()) { - if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) + if (c.wire == nullptr || design->selected_member(module->name, c.wire->name)) found_rhs_wire = true; } if (!found_lhs_wire || !found_rhs_wire) @@ -572,23 +565,21 @@ struct ShowWorker design->optimize(); page_counter = 0; - for (auto &mod_it : design->modules_) + for (auto mod : design->selected_modules()) { - module = mod_it.second; - if (!design->selected_module(module->name)) - continue; + module = mod; if (design->selected_whole_module(module->name)) { if (module->get_blackbox_attribute()) { - // log("Skipping blackbox module %s.\n", id2cstr(module->name)); + // log("Skipping blackbox module %s.\n", log_id(module->name)); continue; } else - if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) { - log("Skipping empty module %s.\n", id2cstr(module->name)); + if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) { + log("Skipping empty module %s.\n", log_id(module->name)); continue; } else - log("Dumping module %s to page %d.\n", id2cstr(module->name), ++page_counter); + log("Dumping module %s to page %d.\n", log_id(module->name), ++page_counter); } else - log("Dumping selected parts of module %s to page %d.\n", id2cstr(module->name), ++page_counter); + log("Dumping selected parts of module %s to page %d.\n", log_id(module->name), ++page_counter); handle_module(); } } @@ -802,13 +793,12 @@ struct ShowPass : public Pass { if (format != "ps" && format != "dot") { int modcount = 0; - for (auto &mod_it : design->modules_) { - if (mod_it.second->get_blackbox_attribute()) + for (auto module : design->selected_modules()) { + if (module->get_blackbox_attribute()) continue; - if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) + if (module->cells().size() == 0 && module->connections().empty()) continue; - if (design->selected_module(mod_it.first)) - modcount++; + modcount++; } if (modcount > 1) log_cmd_error("For formats different than 'ps' or 'dot' only one module must be selected.\n"); @@ -835,7 +825,7 @@ struct ShowPass : public Pass { FILE *f = fopen(dot_file.c_str(), "w"); if (custom_prefix) yosys_output_files.insert(dot_file); - if (f == NULL) { + if (f == nullptr) { for (auto lib : libs) delete lib; log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); @@ -889,8 +879,8 @@ struct ShowPass : public Pass { if (flag_pause) { #ifdef YOSYS_ENABLE_READLINE - char *input = NULL; - while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != NULL) { + char *input = nullptr; + while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != nullptr) { if (input[strspn(input, " \t\r\n")] == 0) break; char *p = input + strspn(input, " \t\r\n"); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index bafafca4e..ea9e06979 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -75,13 +75,13 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; if (sig_a.size() != sig.size()) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice"); - cell->parameters["\\OFFSET"] = offset; - cell->parameters["\\A_WIDTH"] = sig_a.size(); - cell->parameters["\\Y_WIDTH"] = sig.size(); - cell->setPort("\\A", sig_a); - cell->setPort("\\Y", module->addWire(NEW_ID, sig.size())); - new_sig = cell->getPort("\\Y"); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice)); + cell->parameters[ID::OFFSET] = offset; + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::Y_WIDTH] = sig.size(); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size())); + new_sig = cell->getPort(ID::Y); } sliced_signals_cache[sig] = new_sig; @@ -102,7 +102,7 @@ struct SpliceWorker for (auto &bit : sig.to_sigbit_vector()) { - if (bit.wire == NULL) + if (bit.wire == nullptr) { if (last_bit == 0) chunks.back().append(bit); @@ -132,13 +132,13 @@ struct SpliceWorker RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front()); for (size_t i = 1; i < chunks.size(); i++) { RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]); - RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); - cell->parameters["\\A_WIDTH"] = new_sig.size(); - cell->parameters["\\B_WIDTH"] = sig2.size(); - cell->setPort("\\A", new_sig); - cell->setPort("\\B", sig2); - cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size())); - new_sig = cell->getPort("\\Y"); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat)); + cell->parameters[ID::A_WIDTH] = new_sig.size(); + cell->parameters[ID::B_WIDTH] = sig2.size(); + cell->setPort(ID::A, new_sig); + cell->setPort(ID::B, sig2); + cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size())); + new_sig = cell->getPort(ID::Y); } spliced_signals_cache[sig] = new_sig; @@ -149,23 +149,23 @@ struct SpliceWorker void run() { - log("Splicing signals in module %s:\n", RTLIL::id2cstr(module->name)); + log("Splicing signals in module %s:\n", log_id(module->name)); driven_bits.push_back(RTLIL::State::Sm); driven_bits.push_back(RTLIL::State::Sm); - for (auto &it : module->wires_) - if (it.second->port_input) { - RTLIL::SigSpec sig = sigmap(it.second); + for (auto wire : module->wires()) + if (wire->port_input) { + RTLIL::SigSpec sig = sigmap(wire); driven_chunks.insert(sig); for (auto &bit : sig.to_sigbit_vector()) driven_bits.push_back(bit); driven_bits.push_back(RTLIL::State::Sm); } - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) { + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) + if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) { RTLIL::SigSpec sig = sigmap(conn.second); driven_chunks.insert(sig); for (auto &bit : sig.to_sigbit_vector()) @@ -180,9 +180,8 @@ struct SpliceWorker SigPool selected_bits; if (!sel_by_cell) - for (auto &it : module->wires_) - if (design->selected(module, it.second)) - selected_bits.add(sigmap(it.second)); + for (auto wire : module->selected_wires()) + selected_bits.add(sigmap(wire)); std::vector<Cell*> mod_cells = module->cells(); @@ -343,17 +342,14 @@ struct SplicePass : public Pass { log_header(design, "Executing SPLICE pass (creating cells for signal splicing).\n"); - for (auto &mod_it : design->modules_) + for (auto module : design->selected_modules()) { - if (!design->selected(mod_it.second)) - continue; - - if (mod_it.second->processes.size()) { - log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); + if (module->processes.size()) { + log("Skipping module %s as it contains processes.\n", module->name.c_str()); continue; } - SpliceWorker worker(design, mod_it.second); + SpliceWorker worker(design, module); worker.sel_by_cell = sel_by_cell; worker.sel_by_wire = sel_by_wire; worker.sel_any_bit = sel_any_bit; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index f5a1f17b3..bf693e3d4 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -60,17 +60,17 @@ struct SplitnetsWorker new_wire->port_input = wire->port_input; new_wire->port_output = wire->port_output; - if (wire->attributes.count("\\src")) - new_wire->attributes["\\src"] = wire->attributes.at("\\src"); + if (wire->attributes.count(ID::src)) + new_wire->attributes[ID::src] = wire->attributes.at(ID::src); - if (wire->attributes.count("\\keep")) - new_wire->attributes["\\keep"] = wire->attributes.at("\\keep"); + if (wire->attributes.count(ID::keep)) + new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep); - if (wire->attributes.count("\\init")) { - Const old_init = wire->attributes.at("\\init"), new_init; + if (wire->attributes.count(ID::init)) { + Const old_init = wire->attributes.at(ID::init), new_init; for (int i = offset; i < offset+width; i++) new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx); - new_wire->attributes["\\init"] = new_init; + new_wire->attributes[ID::init] = new_init; } std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector(); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index c8e4f3981..6c4bc0e5b 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -79,18 +79,15 @@ struct statdata_t STAT_NUMERIC_MEMBERS #undef X - for (auto &it : mod->wires_) + for (auto wire : mod->selected_wires()) { - if (!design->selected(mod, it.second)) - continue; - - if (it.first[0] == '\\') { + if (wire->name[0] == '\\') { num_pub_wires++; - num_pub_wire_bits += it.second->width; + num_pub_wire_bits += wire->width; } num_wires++; - num_wire_bits += it.second->width; + num_wire_bits += wire->width; } for (auto &it : mod->memories) { @@ -100,31 +97,28 @@ struct statdata_t num_memory_bits += it.second->width * it.second->size; } - for (auto &it : mod->cells_) + for (auto cell : mod->selected_cells()) { - if (!design->selected(mod, it.second)) - continue; - - RTLIL::IdString cell_type = it.second->type; + RTLIL::IdString cell_type = cell->type; if (width_mode) { - if (cell_type.in("$not", "$pos", "$neg", - "$logic_not", "$logic_and", "$logic_or", - "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", - "$lut", "$and", "$or", "$xor", "$xnor", - "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", - "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", - "$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) { - int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0; - int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0; - int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0; + if (cell_type.in(ID($not), ID($pos), ID($neg), + ID($logic_not), ID($logic_and), ID($logic_or), + ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), + ID($lut), ID($and), ID($or), ID($xor), ID($xnor), + ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), + ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), + ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($alu))) { + int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0; + int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0; + int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0; cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y})); } - else if (cell_type.in("$mux", "$pmux")) - cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y"))); - else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr")) - cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q"))); + else if (cell_type.in(ID($mux), ID($pmux))) + cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y))); + else if (cell_type.in(ID($sr), ID($dff), ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr))) + cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q))); } if (!cell_area.empty()) { @@ -157,7 +151,7 @@ struct statdata_t log(" Number of cells: %6d\n", num_cells); for (auto &it : num_cells_by_type) if (it.second) - log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second); + log(" %-26s %6d\n", log_id(it.first), it.second); if (!unknown_cell_area.empty()) { log("\n"); @@ -172,12 +166,12 @@ struct statdata_t if (tech == "xilinx") { - int lut6_cnt = num_cells_by_type["\\LUT6"]; - int lut5_cnt = num_cells_by_type["\\LUT5"]; - int lut4_cnt = num_cells_by_type["\\LUT4"]; - int lut3_cnt = num_cells_by_type["\\LUT3"]; - int lut2_cnt = num_cells_by_type["\\LUT2"]; - int lut1_cnt = num_cells_by_type["\\LUT1"]; + int lut6_cnt = num_cells_by_type[ID(LUT6)]; + int lut5_cnt = num_cells_by_type[ID(LUT5)]; + int lut4_cnt = num_cells_by_type[ID(LUT4)]; + int lut3_cnt = num_cells_by_type[ID(LUT3)]; + int lut2_cnt = num_cells_by_type[ID(LUT2)]; + int lut1_cnt = num_cells_by_type[ID(LUT1)]; int lc_cnt = 0; lc_cnt += lut6_cnt; @@ -235,7 +229,7 @@ struct statdata_t if (gate_costs.count(ctype)) tran_cnt += cnum * gate_costs.at(ctype); - else if (ctype.in("$_DFF_P_", "$_DFF_N_")) + else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_))) tran_cnt += cnum * 16; else tran_cnt_exact = false; @@ -255,7 +249,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL for (auto &it : num_cells_by_type) if (mod_stat.count(it.first) > 0) { - log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second); + log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, log_id(it.first), it.second); mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second; mod_data.num_cells -= it.second; } else { @@ -281,7 +275,7 @@ void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_fil continue; LibertyAst *ar = cell->find("area"); - if (ar != NULL && !ar->value.empty()) + if (ar != nullptr && !ar->value.empty()) cell_area["\\" + cell->args[0]] = atof(ar->value.c_str()); } } @@ -319,7 +313,7 @@ struct StatPass : public Pass { log_header(design, "Printing statistics.\n"); bool width_mode = false; - RTLIL::Module *top_mod = NULL; + RTLIL::Module *top_mod = nullptr; std::map<RTLIL::IdString, statdata_t> mod_stat; dict<IdString, double> cell_area; string techname; @@ -342,9 +336,9 @@ struct StatPass : public Pass { continue; } if (args[argidx] == "-top" && argidx+1 < args.size()) { - if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0) + if (design->module(RTLIL::escape_id(args[argidx+1])) == nullptr) log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str()); - top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx])); + top_mod = design->module(RTLIL::escape_id(args[++argidx])); continue; } break; @@ -357,25 +351,25 @@ struct StatPass : public Pass { for (auto mod : design->selected_modules()) { if (!top_mod && design->full_selection()) - if (mod->get_bool_attribute("\\top")) + if (mod->get_bool_attribute(ID::top)) top_mod = mod; statdata_t data(design, mod, width_mode, cell_area, techname); mod_stat[mod->name] = data; log("\n"); - log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)"); + log("=== %s%s ===\n", log_id(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)"); log("\n"); data.log_data(mod->name, false); } - if (top_mod != NULL && GetSize(mod_stat) > 1) + if (top_mod != nullptr && GetSize(mod_stat) > 1) { log("\n"); log("=== design hierarchy ===\n"); log("\n"); - log(" %-28s %6d\n", RTLIL::id2cstr(top_mod->name), 1); + log(" %-28s %6d\n", log_id(top_mod->name), 1); statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0); log("\n"); diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc index 3c0eac8de..5748ff7f0 100644 --- a/passes/cmds/torder.cc +++ b/passes/cmds/torder.cc @@ -81,9 +81,9 @@ struct TorderPass : public Pass { continue; if (!noautostop && yosys_celltypes.cell_known(cell->type)) { - if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA")) + if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA)) continue; - if (cell->type == "$memrd" && conn.first == "\\DATA") + if (cell->type == ID($memrd) && conn.first == ID::DATA) continue; } diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index cf3e46ace..8446e27b3 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -35,7 +35,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", log_id(module)); } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 71599f46e..cdc74b0b2 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -152,7 +152,7 @@ struct EquivAddPass : public Pass { for (int i = 0; i < GetSize(gold_signal); i++) { Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]); - equiv_cell->set_bool_attribute("\\keep"); + equiv_cell->set_bool_attribute(ID::keep); to_equiv_bits[gold_signal[i]] = equiv_signal[i]; to_equiv_bits[gate_signal[i]] = equiv_signal[i]; added_equiv_cells.insert(equiv_cell); diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index bcc68d6d2..ec651193e 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -58,9 +58,9 @@ struct EquivInductWorker log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); cell_warn_cache.insert(cell); } - if (cell->type == "$equiv") { - SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit(); - SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit(); + if (cell->type == ID($equiv)) { + SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); + SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit(); if (bit_a != bit_b) { int ez_a = satgen.importSigBit(bit_a, step); int ez_b = satgen.importSigBit(bit_b, step); @@ -125,7 +125,7 @@ struct EquivInductWorker if (!ez->solve(new_step_not_consistent)) { log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset)); for (auto cell : workset) - cell->setPort("\\B", cell->getPort("\\A")); + cell->setPort(ID::B, cell->getPort(ID::A)); success_counter += GetSize(workset); return; } @@ -137,10 +137,10 @@ struct EquivInductWorker for (auto cell : workset) { - SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit(); - SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit(); + SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); + SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit(); - log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort("\\Y")))); + log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y)))); int ez_a = satgen.importSigBit(bit_a, max_seq+1); int ez_b = satgen.importSigBit(bit_b, max_seq+1); @@ -151,7 +151,7 @@ struct EquivInductWorker if (!ez->solve(cond)) { log(" success!\n"); - cell->setPort("\\B", cell->getPort("\\A")); + cell->setPort(ID::B, cell->getPort(ID::A)); success_counter++; } else { log(" failed.\n"); @@ -219,8 +219,8 @@ struct EquivInductPass : public Pass { pool<Cell*> unproven_equiv_cells; for (auto cell : module->selected_cells()) - if (cell->type == "$equiv") { - if (cell->getPort("\\A") != cell->getPort("\\B")) + if (cell->type == ID($equiv)) { + if (cell->getPort(ID::A) != cell->getPort(ID::B)) unproven_equiv_cells.insert(cell); } diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 4855ce29e..50572ae5c 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -406,7 +406,7 @@ struct EquivMakeWorker void init_bit2driven() { for (auto cell : equiv_mod->cells()) { - if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) + if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) continue; for (auto &conn : cell->connections()) { diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc index 135eaf145..737de25d9 100644 --- a/passes/equiv/equiv_mark.cc +++ b/passes/equiv/equiv_mark.cc @@ -48,7 +48,7 @@ struct EquivMarkWorker { for (auto cell : module->cells()) { - if (cell->type == "$equiv") + if (cell->type == ID($equiv)) equiv_cells.insert(cell->name); for (auto &port : cell->connections()) @@ -122,8 +122,8 @@ struct EquivMarkWorker { auto cell = module->cell(cell_name); - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); if (sig_a == sig_b) { for (auto bit : sig_a) @@ -139,11 +139,11 @@ struct EquivMarkWorker for (auto cell : module->cells()) { - if (cell_regions.count(cell->name) || cell->type != "$equiv") + if (cell_regions.count(cell->name) || cell->type != ID($equiv)) continue; - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); log_assert(sig_a != sig_b); @@ -176,10 +176,10 @@ struct EquivMarkWorker { if (cell_regions.count(cell->name)) { int r = final_region_map.at(cell_regions.at(cell->name)); - cell->attributes["\\equiv_region"] = Const(r); + cell->attributes[ID::equiv_region] = Const(r); region_cell_count[r]++; } else - cell->attributes.erase("\\equiv_region"); + cell->attributes.erase(ID::equiv_region); } for (auto wire : module->wires()) @@ -191,10 +191,10 @@ struct EquivMarkWorker if (GetSize(regions) == 1) { int r = final_region_map.at(*regions.begin()); - wire->attributes["\\equiv_region"] = Const(r); + wire->attributes[ID::equiv_region] = Const(r); region_wire_count[r]++; } else - wire->attributes.erase("\\equiv_region"); + wire->attributes.erase(ID::equiv_region); } for (int i = 0; i < next_final_region; i++) diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index e06f9515b..085970189 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -47,7 +47,7 @@ struct EquivMiterWorker if (cone.count(c)) return; - if (c->type == "$equiv" && !seed_cells.count(c)) { + if (c->type == ID($equiv) && !seed_cells.count(c)) { leaves.insert(c); return; } @@ -57,7 +57,7 @@ struct EquivMiterWorker for (auto &conn : c->connections()) { if (!ct.cell_input(c->type, conn.first)) continue; - if (c->type == "$equiv" && (conn.first == "\\A") != gold_mode) + if (c->type == ID($equiv) && (conn.first == ID::A) != gold_mode) continue; for (auto bit : sigmap(conn.second)) if (bit_to_driver.count(bit)) @@ -81,7 +81,7 @@ struct EquivMiterWorker // find seed cells for (auto c : source_module->selected_cells()) - if (c->type == "$equiv") { + if (c->type == ID($equiv)) { log("Seed $equiv cell: %s\n", log_id(c)); seed_cells.insert(c); } @@ -213,18 +213,18 @@ struct EquivMiterWorker vector<Cell*> equiv_cells; for (auto c : miter_module->cells()) - if (c->type == "$equiv" && c->getPort("\\A") != c->getPort("\\B")) + if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B)) equiv_cells.push_back(c); for (auto c : equiv_cells) { SigSpec cmp = mode_undef ? - miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort("\\A"), State::Sx), - miter_module->Eqx(NEW_ID, c->getPort("\\A"), c->getPort("\\B"))) : - miter_module->Eq(NEW_ID, c->getPort("\\A"), c->getPort("\\B")); + miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx), + miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) : + miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B)); if (mode_cmp) { - string cmp_name = string("\\cmp") + log_signal(c->getPort("\\Y")); + string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y))); for (int i = 1; i < GetSize(cmp_name); i++) if (cmp_name[i] == '\\') cmp_name[i] = '_'; @@ -242,7 +242,7 @@ struct EquivMiterWorker } if (mode_trigger) { - auto w = miter_module->addWire("\\trigger"); + auto w = miter_module->addWire(ID(trigger)); w->port_output = true; miter_module->addReduceOr(NEW_ID, trigger_signals, w); } diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index 18b3e7d36..688c20f43 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -102,7 +102,7 @@ struct EquivPurgeWorker for (auto cell : module->cells()) { - if (cell->type != "$equiv") { + if (cell->type != ID($equiv)) { for (auto &port : cell->connections()) { if (cell->input(port.first)) for (auto bit : sigmap(port.second)) @@ -114,9 +114,9 @@ struct EquivPurgeWorker continue; } - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_y = sigmap(cell->getPort("\\Y")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); if (sig_a == sig_b) continue; @@ -130,7 +130,7 @@ struct EquivPurgeWorker for (auto bit : sig_y) visited.insert(bit); - cell->setPort("\\Y", make_output(sig_y, cell->name)); + cell->setPort(ID::Y, make_output(sig_y, cell->name)); } SigSpec srcsig; @@ -167,8 +167,8 @@ struct EquivPurgeWorker rewrite_sigmap.add(chunk, make_input(chunk)); for (auto cell : module->cells()) - if (cell->type == "$equiv") - cell->setPort("\\Y", rewrite_sigmap(sigmap(cell->getPort("\\Y")))); + if (cell->type == ID($equiv)) + cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y)))); module->fixup_ports(); } diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index c5c28c7d9..6daa112b5 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -68,9 +68,9 @@ struct EquivRemovePass : public Pass { for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) - if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort("\\A") == cell->getPort("\\B"))) { - log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort("\\Y"))); - module->connect(cell->getPort("\\Y"), mode_gate ? cell->getPort("\\B") : cell->getPort("\\A")); + if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) { + log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y))); + module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A)); module->remove(cell); remove_count++; } diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index c2fab26f2..4d2839f4d 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -60,8 +60,8 @@ struct EquivSimpleWorker for (auto &conn : cell->connections()) if (yosys_celltypes.cell_input(cell->type, conn.first)) for (auto bit : sigmap(conn.second)) { - if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) { - if (!conn.first.in("\\CLK", "\\C")) + if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) { + if (!conn.first.in(ID::CLK, ID::C)) next_seed.insert(bit); } else find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit); @@ -90,8 +90,8 @@ struct EquivSimpleWorker bool run_cell() { - SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit(); - SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit(); + SigBit bit_a = sigmap(equiv_cell->getPort(ID::A)).as_bit(); + SigBit bit_b = sigmap(equiv_cell->getPort(ID::B)).as_bit(); int ez_context = ez->frozen_literal(); if (satgen.model_undef) @@ -115,9 +115,9 @@ struct EquivSimpleWorker if (verbose) { log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell)); - log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y"))); + log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort(ID::Y))); } else { - log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort("\\Y"))); + log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort(ID::Y))); } int step = max_seq; @@ -199,7 +199,7 @@ struct EquivSimpleWorker if (!ez->solve(ez_context)) { log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n"); - equiv_cell->setPort("\\B", equiv_cell->getPort("\\A")); + equiv_cell->setPort(ID::B, equiv_cell->getPort(ID::A)); ez->assume(ez->NOT(ez_context)); return true; } @@ -256,7 +256,7 @@ struct EquivSimpleWorker if (GetSize(equiv_cells) > 1) { SigSpec sig; for (auto c : equiv_cells) - sig.append(sigmap(c->getPort("\\Y"))); + sig.append(sigmap(c->getPort(ID::Y))); log(" Grouping SAT models for %s:\n", log_signal(sig)); } @@ -344,8 +344,8 @@ struct EquivSimplePass : public Pass { int unproven_cells_counter = 0; for (auto cell : module->selected_cells()) - if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) { - auto bit = sigmap(cell->getPort("\\Y").as_bit()); + if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) { + auto bit = sigmap(cell->getPort(ID::Y).as_bit()); auto bit_group = bit; if (!nogroup && bit_group.wire) bit_group.offset = 0; @@ -360,7 +360,7 @@ struct EquivSimplePass : public Pass { unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module)); for (auto cell : module->cells()) { - if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) + if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) continue; for (auto &conn : cell->connections()) if (yosys_celltypes.cell_output(cell->type, conn.first)) diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc index b4a93ccf5..258e2e45b 100644 --- a/passes/equiv/equiv_status.cc +++ b/passes/equiv/equiv_status.cc @@ -59,8 +59,8 @@ struct EquivStatusPass : public Pass { int proven_equiv_cells = 0; for (auto cell : module->selected_cells()) - if (cell->type == "$equiv") { - if (cell->getPort("\\A") != cell->getPort("\\B")) + if (cell->type == ID($equiv)) { + if (cell->getPort(ID::A) != cell->getPort(ID::B)) unproven_equiv_cells.push_back(cell); else proven_equiv_cells++; @@ -77,7 +77,7 @@ struct EquivStatusPass : public Pass { log(" Equivalence successfully proven!\n"); } else { for (auto cell : unproven_equiv_cells) - log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort("\\A")), log_signal(cell->getPort("\\B"))); + log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B))); } unproven_count += GetSize(unproven_equiv_cells); diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 6672948b9..1b7bf96a8 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -110,9 +110,9 @@ struct EquivStructWorker module->connect(sig_b, sig_a); } - auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged"); + auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged); merged_attr.insert(log_id(cell_b)); - cell_a->add_strpool_attribute("\\equiv_merged", merged_attr); + cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr); module->remove(cell_b); } @@ -126,9 +126,9 @@ struct EquivStructWorker pool<IdString> cells; for (auto cell : module->selected_cells()) - if (cell->type == "$equiv") { - SigBit sig_a = sigmap(cell->getPort("\\A").as_bit()); - SigBit sig_b = sigmap(cell->getPort("\\B").as_bit()); + if (cell->type == ID($equiv)) { + SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); + SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); equiv_bits.add(sig_b, sig_a); equiv_inputs.insert(sig_a); equiv_inputs.insert(sig_b); @@ -139,10 +139,10 @@ struct EquivStructWorker } for (auto cell : module->selected_cells()) - if (cell->type == "$equiv") { - SigBit sig_a = sigmap(cell->getPort("\\A").as_bit()); - SigBit sig_b = sigmap(cell->getPort("\\B").as_bit()); - SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit()); + if (cell->type == ID($equiv)) { + SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); + SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); + SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit()); if (sig_a == sig_b && equiv_inputs.count(sig_y)) { log(" Purging redundant $equiv cell %s.\n", log_id(cell)); module->connect(sig_y, sig_a); @@ -316,7 +316,7 @@ struct EquivStructPass : public Pass { } void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE { - pool<IdString> fwonly_cells({ "$equiv" }); + pool<IdString> fwonly_cells({ ID($equiv) }); bool mode_icells = false; bool mode_fwd = false; int max_iter = -1; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index a1c8067b4..30e9e4dad 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -55,7 +55,7 @@ ret_false: sig2driver.find(sig, cellport_list); for (auto &cellport : cellport_list) { - if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") { + if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != ID::Y) { goto ret_false; } @@ -67,8 +67,8 @@ ret_false: recursion_monitor.insert(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A")); - RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B")); + RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A)); + RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B)); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) { recursion_monitor.erase(cellport.first); @@ -99,18 +99,18 @@ static bool check_state_users(RTLIL::SigSpec sig) RTLIL::Cell *cell = cellport.first; if (muxtree_cells.count(cell) > 0) continue; - if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig) + if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig) continue; - if (cellport.second != "\\A" && cellport.second != "\\B") + if (cellport.second != ID::A && cellport.second != ID::B) return false; - if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y")) + if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y)) return false; for (auto &port_it : cell->connections()) - if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") + if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y) return false; - if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const()) + if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const()) continue; - if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const()) + if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const()) continue; return false; } @@ -120,9 +120,9 @@ static bool check_state_users(RTLIL::SigSpec sig) static void detect_fsm(RTLIL::Wire *wire) { - bool has_fsm_encoding_attr = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() != "none"; - bool has_fsm_encoding_none = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() == "none"; - bool has_init_attr = wire->attributes.count("\\init") > 0; + bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none"; + bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none"; + bool has_init_attr = wire->attributes.count(ID::init) > 0; bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire))); bool looks_like_state_reg = false, looks_like_good_state_reg = false; bool is_self_resetting = false; @@ -133,7 +133,7 @@ static void detect_fsm(RTLIL::Wire *wire) if (wire->width <= 1) { if (has_fsm_encoding_attr) { log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire)); - wire->attributes.erase("\\fsm_encoding"); + wire->attributes.erase(ID::fsm_encoding); } return; } @@ -143,13 +143,13 @@ static void detect_fsm(RTLIL::Wire *wire) for (auto &cellport : cellport_list) { - if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q") + if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != ID::Q) continue; muxtree_cells.clear(); pool<Cell*> recursion_monitor; - RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q")); - RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D")); + RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q)); + RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D)); dict<RTLIL::SigSpec, bool> mux_tree_cache; if (sig_q != assign_map(wire)) @@ -173,10 +173,10 @@ static void detect_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = cellport.first; bool set_output = false, clr_output = false; - if (cell->type.in("$ne", "$reduce_or", "$reduce_bool")) + if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool))) set_output = true; - if (cell->type.in("$eq", "$logic_not", "$reduce_and")) + if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and))) clr_output = true; if (set_output || clr_output) { @@ -234,7 +234,7 @@ static void detect_fsm(RTLIL::Wire *wire) if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting) { log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire)); - wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto"); + wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto"); } else if (looks_like_state_reg) @@ -284,38 +284,34 @@ struct FsmDetectPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules_) + for (auto mod : design->selected_modules()) { - if (!design->selected(mod_it.second)) - continue; - - module = mod_it.second; + module = mod; assign_map.set(module); sig2driver.clear(); sig2user.clear(); sig_at_port.clear(); - for (auto &cell_it : module->cells_) - for (auto &conn_it : cell_it.second->connections()) { - if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { + for (auto cell : module->cells()) + for (auto &conn_it : cell->connections()) { + if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); - sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first)); + sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first)); } - if (!ct.cell_known(cell_it.second->type) || ct.cell_input(cell_it.second->type, conn_it.first)) { + if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); - sig2user.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first)); + sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first)); } } - for (auto &wire_it : module->wires_) - if (wire_it.second->port_id != 0) - sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second))); + for (auto wire : module->wires()) + if (wire->port_id != 0) + sig_at_port.add(assign_map(wire)); - for (auto &wire_it : module->wires_) - if (design->selected(module, wire_it.second)) - detect_fsm(wire_it.second); + for (auto wire : module->selected_wires()) + detect_fsm(wire); } assign_map.clear(); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 1610ec751..ade6c17f5 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -47,42 +47,42 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { - if (full_mode || cell->type == "$_MUX_") + if (full_mode || cell->type == ID($_MUX_)) return true; - if (cell->type.in("$mux", "$pmux")) - if (cell->getPort("\\A").size() < 2) + if (cell->type.in(ID($mux), ID($pmux))) + if (cell->getPort(ID::A).size() < 2) return true; int in_bits = 0; RTLIL::SigSpec new_signals; - if (cell->hasPort("\\A")) { - in_bits += GetSize(cell->getPort("\\A")); - new_signals.append(assign_map(cell->getPort("\\A"))); + if (cell->hasPort(ID::A)) { + in_bits += GetSize(cell->getPort(ID::A)); + new_signals.append(assign_map(cell->getPort(ID::A))); } - if (cell->hasPort("\\B")) { - in_bits += GetSize(cell->getPort("\\B")); - new_signals.append(assign_map(cell->getPort("\\B"))); + if (cell->hasPort(ID::B)) { + in_bits += GetSize(cell->getPort(ID::B)); + new_signals.append(assign_map(cell->getPort(ID::B))); } - if (cell->hasPort("\\S")) { - in_bits += GetSize(cell->getPort("\\S")); - new_signals.append(assign_map(cell->getPort("\\S"))); + if (cell->hasPort(ID::S)) { + in_bits += GetSize(cell->getPort(ID::S)); + new_signals.append(assign_map(cell->getPort(ID::S))); } if (in_bits > 8) return false; - if (cell->hasPort("\\Y")) - new_signals.append(assign_map(cell->getPort("\\Y"))); + if (cell->hasPort(ID::Y)) + new_signals.append(assign_map(cell->getPort(ID::Y))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN"))); - new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT"))); + new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN))); + new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT))); if (new_signals.size() > 3) return false; @@ -94,10 +94,10 @@ struct FsmExpand { std::vector<RTLIL::Cell*> cell_list; - for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN")))) + for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN)))) cell_list.push_back(c); - for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT")))) + for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT)))) cell_list.push_back(c); current_set.clear(); @@ -106,7 +106,7 @@ struct FsmExpand if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0) continue; for (auto &p : c->connections()) { - if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y") + if (p.first != ID::A && p.first != ID::B && p.first != ID::S && p.first != ID::Y) goto next_cell; } if (!is_cell_merge_candidate(c)) { @@ -123,14 +123,14 @@ struct FsmExpand if (already_optimized) return; - int trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int(); + int trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int(); if (trans_num > limit_transitions) { log(" grown transition table to %d entries -> optimize.\n", trans_num); FsmData::optimize_fsm(fsm_cell, module); already_optimized = true; - trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int(); + trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int(); log(" transition table size after optimizaton: %d\n", trans_num); limit_transitions = 16 * trans_num; } @@ -159,12 +159,12 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->hasPort("\\A")) - A = assign_map(cell->getPort("\\A")); - if (cell->hasPort("\\B")) - B = assign_map(cell->getPort("\\B")); - if (cell->hasPort("\\S")) - S = assign_map(cell->getPort("\\S")); + if (cell->hasPort(ID::A)) + A = assign_map(cell->getPort(ID::A)); + if (cell->hasPort(ID::B)) + B = assign_map(cell->getPort(ID::B)); + if (cell->hasPort(ID::S)) + S = assign_map(cell->getPort(ID::S)); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); @@ -178,14 +178,14 @@ struct FsmExpand fsm_data.copy_from_cell(fsm_cell); fsm_data.num_inputs += input_sig.size(); - RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN"); + RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN); new_ctrl_in.append(input_sig); - fsm_cell->setPort("\\CTRL_IN", new_ctrl_in); + fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in); fsm_data.num_outputs += output_sig.size(); - RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT"); + RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT); new_ctrl_out.append(output_sig); - fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out); + fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out); if (GetSize(input_sig) > 10) log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n", @@ -246,7 +246,7 @@ struct FsmExpand log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str()); already_optimized = false; - limit_transitions = 16 * fsm_cell->parameters["\\TRANS_NUM"].as_int(); + limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int(); for (create_current_set(); current_set.size() > 0; create_current_set()) { for (auto c : current_set) @@ -295,15 +295,13 @@ struct FsmExpandPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) { - if (!design->selected(mod_it.second)) - continue; + for (auto mod : design->selected_modules()) { std::vector<RTLIL::Cell*> fsm_cells; - for (auto &cell_it : mod_it.second->cells_) - if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) - fsm_cells.push_back(cell_it.second); + for (auto cell : mod->selected_cells()) + if (cell->type == ID($fsm)) + fsm_cells.push_back(cell); for (auto c : fsm_cells) { - FsmExpand fsm_expand(c, design, mod_it.second, full_mode); + FsmExpand fsm_expand(c, design, mod, full_mode); fsm_expand.execute(); } } diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 8eb1872f0..c02a54ea2 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -57,7 +57,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st std::string kiss_name; size_t i; - attr_it = cell->attributes.find("\\fsm_export"); + attr_it = cell->attributes.find(ID::fsm_export); if (!filename.empty()) { kiss_name.assign(filename); } else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") { @@ -173,16 +173,15 @@ struct FsmExportPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells_) - if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { - attr_it = cell_it.second->attributes.find("\\fsm_export"); - if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) { - write_kiss2(mod_it.second, cell_it.second, filename, flag_origenc); - filename.clear(); - } + for (auto mod : design->selected_modules()) + for (auto cell : mod->selected_cells()) + if (cell->type == ID($fsm)) { + attr_it = cell->attributes.find(ID::fsm_export); + if (!flag_noauto || (attr_it != cell->attributes.end())) { + write_kiss2(mod, cell, filename, flag_origenc); + filename.clear(); } + } } } FsmExportPass; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index a85c3bec0..3840aabc8 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -70,15 +70,15 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") { + if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } - RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); - RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S")); - RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); + RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); + RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S)); + RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); RTLIL::SigSpec sig_aa = sig; sig_aa.replace(sig_y, sig_a); @@ -272,17 +272,17 @@ static void extract_fsm(RTLIL::Wire *wire) sig2driver.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") + if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q) continue; log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); - RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q")); - RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D")); - clk = cell->getPort("\\CLK"); - clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); - if (cell->type == "$adff") { - arst = cell->getPort("\\ARST"); - arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool(); - reset_state = cell->parameters["\\ARST_VALUE"]; + RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q)); + RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D)); + clk = cell->getPort(ID::CLK); + clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool(); + if (cell->type == ID($adff)) { + arst = cell->getPort(ID::ARST); + arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool(); + reset_state = cell->parameters[ID::ARST_VALUE]; } sig_q.replace(dff_out, sig_d, &dff_in); break; @@ -320,14 +320,14 @@ static void extract_fsm(RTLIL::Wire *wire) sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_b; - if (cell->hasPort("\\B")) - sig_b = assign_map(cell->getPort("\\B")); - RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); - if (cellport.second == "\\A" && !sig_b.is_fully_const()) + if (cell->hasPort(ID::B)) + sig_b = assign_map(cell->getPort(ID::B)); + RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y)); + if (cellport.second == ID::A && !sig_b.is_fully_const()) continue; - if (cellport.second == "\\B" && !sig_a.is_fully_const()) + if (cellport.second == ID::B && !sig_a.is_fully_const()) continue; log(" found ctrl output: %s\n", log_signal(sig_y)); ctrl_out.append(sig_y); @@ -368,21 +368,21 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); - fsm_cell->setPort("\\CLK", clk); - fsm_cell->setPort("\\ARST", arst); - fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0; - fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0; - fsm_cell->setPort("\\CTRL_IN", ctrl_in); - fsm_cell->setPort("\\CTRL_OUT", ctrl_out); - fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); + RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), ID($fsm)); + fsm_cell->setPort(ID::CLK, clk); + fsm_cell->setPort(ID::ARST, arst); + fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0; + fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0; + fsm_cell->setPort(ID::CTRL_IN, ctrl_in); + fsm_cell->setPort(ID::CTRL_OUT, ctrl_out); + fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str()); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); // rename original state wire module->wires_.erase(wire->name); - wire->attributes.erase("\\fsm_encoding"); + wire->attributes.erase(ID::fsm_encoding); wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); module->wires_[wire->name] = wire; @@ -422,18 +422,11 @@ struct FsmExtractPass : public Pass { log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n"); extra_args(args, 1, design); - CellTypes ct; - ct.setup_internals(); - ct.setup_internals_mem(); - ct.setup_stdcells(); - ct.setup_stdcells_mem(); + CellTypes ct(design); - for (auto &mod_it : design->modules_) + for (auto mod : design->selected_modules()) { - if (!design->selected(mod_it.second)) - continue; - - module = mod_it.second; + module = mod; assign_map.set(module); sig2driver.clear(); @@ -446,15 +439,15 @@ struct FsmExtractPass : public Pass { assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } - if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort("\\Y") && - cell->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) && + cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } } - if (cell->type == "$pmux") { - RTLIL::SigSpec sel_sig = assign_map(cell->getPort("\\S")); + if (cell->type == ID($pmux)) { + RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S)); for (auto &bit1 : sel_sig) for (auto &bit2 : sel_sig) if (bit1 != bit2) @@ -463,10 +456,9 @@ struct FsmExtractPass : public Pass { } std::vector<RTLIL::Wire*> wire_list; - for (auto &wire_it : module->wires_) - if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none") - if (design->selected(module, wire_it.second)) - wire_list.push_back(wire_it.second); + for (auto wire : module->selected_wires()) + if (wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes[ID::fsm_encoding].decode_string() != "none") + wire_list.push_back(wire); for (auto wire : wire_list) extract_fsm(wire); } diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 0548259ee..90250f9b7 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -46,16 +46,15 @@ struct FsmInfoPass : public Pass { log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells_) - if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { - log("\n"); - log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str()); - FsmData fsm_data; - fsm_data.copy_from_cell(cell_it.second); - fsm_data.log_info(cell_it.second); - } + for (auto mod : design->selected_modules()) + for (auto cell : mod->selected_cells()) + if (cell->type == ID($fsm)) { + log("\n"); + log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod)); + FsmData fsm_data; + fsm_data.copy_from_cell(cell); + fsm_data.log_info(cell); + } } } FsmInfoPass; diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 80913fda8..1765df092 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -74,15 +74,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const RTLIL::Wire *eq_wire = module->addWire(NEW_ID); and_sig.append(RTLIL::SigSpec(eq_wire)); - RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->setPort("\\A", eq_sig_a); - eq_cell->setPort("\\B", eq_sig_b); - eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire)); - eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size()); - eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq)); + eq_cell->setPort(ID::A, eq_sig_a); + eq_cell->setPort(ID::B, eq_sig_b); + eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire)); + eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); + eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false); + eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size()); + eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(eq_sig_b.size()); + eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); } std::set<int> complete_in_state_cache = it.second; @@ -102,12 +102,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const RTLIL::Wire *or_wire = module->addWire(NEW_ID); and_sig.append(RTLIL::SigSpec(or_wire)); - RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->setPort("\\A", or_sig); - or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire)); - or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); - or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or)); + or_cell->setPort(ID::A, or_sig); + or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire)); + or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); + or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size()); + or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); } } @@ -118,15 +118,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const RTLIL::Wire *and_wire = module->addWire(NEW_ID); cases_vector.append(RTLIL::SigSpec(and_wire)); - RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and"); - and_cell->setPort("\\A", and_sig.extract(0, 1)); - and_cell->setPort("\\B", and_sig.extract(1, 1)); - and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire)); - and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1); - and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1); - and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and)); + and_cell->setPort(ID::A, and_sig.extract(0, 1)); + and_cell->setPort(ID::B, and_sig.extract(1, 1)); + and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire)); + and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); + and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false); + and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1); + and_cell->parameters[ID::B_WIDTH] = RTLIL::Const(1); + and_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); break; } case 1: @@ -141,12 +141,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const } if (cases_vector.size() > 1) { - RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->setPort("\\A", cases_vector); - or_cell->setPort("\\Y", output); - or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); - or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or)); + or_cell->setPort(ID::A, cases_vector); + or_cell->setPort(ID::Y, output); + or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); + or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size()); + or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); } else if (cases_vector.size() == 1) { module->connect(RTLIL::SigSig(output, cases_vector)); } else { @@ -161,31 +161,31 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN"); - RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT"); + RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN); + RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT); // create state register - RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits); + RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits); RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); - if (fsm_cell->getPort("\\ARST").is_fully_const()) { - state_dff->type = "$dff"; + if (fsm_cell->getPort(ID::ARST).is_fully_const()) { + state_dff->type = ID($dff); } else { - state_dff->type = "$adff"; - state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"]; - state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state]; - for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits) + state_dff->type = ID($adff); + state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY]; + state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state]; + for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; - state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST")); + state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST)); } - state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits); - state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"]; - state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK")); - state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire)); - state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire)); + state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits); + state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY]; + state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK)); + state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire)); + state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire)); // decode state register @@ -212,20 +212,20 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) { encoding_is_onehot = false; - RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->setPort("\\A", sig_a); - eq_cell->setPort("\\B", sig_b); - eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i)); - eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size()); - eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq)); + eq_cell->setPort(ID::A, sig_a); + eq_cell->setPort(ID::B, sig_b); + eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i)); + eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false); + eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false); + eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size()); + eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(sig_b.size()); + eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); } } if (encoding_is_onehot) - state_wire->set_bool_attribute("\\onehot"); + state_wire->set_bool_attribute(ID::onehot); // generate next_state signal @@ -285,13 +285,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } - RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux"); - mux_cell->setPort("\\A", sig_a); - mux_cell->setPort("\\B", sig_b); - mux_cell->setPort("\\S", sig_s); - mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire)); - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); - mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); + RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux)); + mux_cell->setPort(ID::A, sig_a); + mux_cell->setPort(ID::B, sig_b); + mux_cell->setPort(ID::S, sig_s); + mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire)); + mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size()); + mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size()); } } @@ -336,15 +336,13 @@ struct FsmMapPass : public Pass { log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) { - if (!design->selected(mod_it.second)) - continue; + for (auto mod : design->selected_modules()) { std::vector<RTLIL::Cell*> fsm_cells; - for (auto &cell_it : mod_it.second->cells_) - if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) - fsm_cells.push_back(cell_it.second); + for (auto cell : mod->selected_cells()) + if (cell->type == ID($fsm)) + fsm_cells.push_back(cell); for (auto cell : fsm_cells) - map_fsm(cell, mod_it.second); + map_fsm(cell, mod); } } } FsmMapPass; diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 048daee55..89e8132d4 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -81,10 +81,10 @@ struct FsmOpt { RTLIL::SigBit bit = sig.as_bit(); - if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0) + if (bit.wire == NULL || bit.wire->attributes.count(ID::unused_bits) == 0) return false; - char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str()); + char *str = strdup(bit.wire->attributes[ID::unused_bits].decode_string().c_str()); for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) { if (tok[0] && bit.offset == atoi(tok)) { free(str); @@ -98,7 +98,7 @@ struct FsmOpt void opt_const_and_unused_inputs() { - RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN"); + RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN); std::vector<bool> ctrl_in_used(ctrl_in.size()); std::vector<FsmData::transition_t> new_transition_table; @@ -119,15 +119,15 @@ struct FsmOpt for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) { if (!ctrl_in_used[i]) { - log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1))); + log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1))); for (auto &tr : new_transition_table) { RTLIL::SigSpec tmp(tr.ctrl_in); tmp.remove(i, 1); tr.ctrl_in = tmp.as_const(); } - RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN"); + RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN); new_ctrl_in.remove(i, 1); - cell->setPort("\\CTRL_IN", new_ctrl_in); + cell->setPort(ID::CTRL_IN, new_ctrl_in); fsm_data.num_inputs--; } } @@ -139,12 +139,12 @@ struct FsmOpt void opt_unused_outputs() { for (int i = 0; i < fsm_data.num_outputs; i++) { - RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1); + RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1); if (signal_is_unused(sig)) { log(" Removing unused output signal %s.\n", log_signal(sig)); - RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT"); + RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT); new_ctrl_out.remove(i, 1); - cell->setPort("\\CTRL_OUT", new_ctrl_out); + cell->setPort(ID::CTRL_OUT, new_ctrl_out); for (auto &tr : fsm_data.transition_table) { RTLIL::SigSpec tmp(tr.ctrl_out); tmp.remove(i, 1); @@ -158,7 +158,7 @@ struct FsmOpt void opt_alias_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN]; for (int i = 0; i < ctrl_in.size(); i++) for (int j = i+1; j < ctrl_in.size(); j++) @@ -195,8 +195,8 @@ struct FsmOpt void opt_feedback_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; - RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"]; + RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN]; + RTLIL::SigSpec &ctrl_out = cell->connections_[ID::CTRL_OUT]; for (int j = 0; j < ctrl_out.size(); j++) for (int i = 0; i < ctrl_in.size(); i++) @@ -340,12 +340,10 @@ struct FsmOptPass : public Pass { log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) { - if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells_) - if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) - FsmData::optimize_fsm(cell_it.second, mod_it.second); - } + for (auto mod : design->selected_modules()) + for (auto cell : mod->selected_cells()) + if (cell->type == ID($fsm)) + FsmData::optimize_fsm(cell, mod); } } FsmOptPass; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index fa1ff48cc..7edb923b9 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f) { - std::string name = cell->parameters["\\NAME"].decode_string(); + std::string name = cell->parameters[ID::NAME].decode_string(); fprintf(f, "set_fsm_state_vector {"); for (int i = fsm_data.state_bits-1; i >= 0; i--) @@ -53,7 +53,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding) { - std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto"; + std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto"; log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); @@ -95,7 +95,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); if (encfile) - fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters["\\NAME"].decode_string()).c_str()); + fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str()); int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0; for (int i = 0; i < int(fsm_data.state_table.size()); i++) @@ -181,11 +181,10 @@ struct FsmRecodePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells_) - if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) - fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, encfile, default_encoding); + for (auto mod : design->selected_modules()) + for (auto cell : mod->selected_cells()) + if (cell->type == ID($fsm)) + fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding); if (fm_set_fsm_file != NULL) fclose(fm_set_fsm_file); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 68222769a..47398b558 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -33,31 +33,31 @@ struct FsmData void copy_to_cell(RTLIL::Cell *cell) { - cell->parameters["\\CTRL_IN_WIDTH"] = RTLIL::Const(num_inputs); - cell->parameters["\\CTRL_OUT_WIDTH"] = RTLIL::Const(num_outputs); + cell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs); + cell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs); int state_num_log2 = 0; for (int i = state_table.size(); i > 0; i = i >> 1) state_num_log2++; state_num_log2 = max(state_num_log2, 1); - cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits); - cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size()); - cell->parameters["\\STATE_NUM_LOG2"] = RTLIL::Const(state_num_log2); - cell->parameters["\\STATE_RST"] = RTLIL::Const(reset_state); - cell->parameters["\\STATE_TABLE"] = RTLIL::Const(); + cell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits); + cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size()); + cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2); + cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state); + cell->parameters[ID::STATE_TABLE] = RTLIL::Const(); for (int i = 0; i < int(state_table.size()); i++) { - std::vector<RTLIL::State> &bits_table = cell->parameters["\\STATE_TABLE"].bits; + std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits; std::vector<RTLIL::State> &bits_state = state_table[i].bits; bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end()); } - cell->parameters["\\TRANS_NUM"] = RTLIL::Const(transition_table.size()); - cell->parameters["\\TRANS_TABLE"] = RTLIL::Const(); + cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size()); + cell->parameters[ID::TRANS_TABLE] = RTLIL::Const(); for (int i = 0; i < int(transition_table.size()); i++) { - std::vector<RTLIL::State> &bits_table = cell->parameters["\\TRANS_TABLE"].bits; + std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits; transition_t &tr = transition_table[i]; RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2); @@ -78,21 +78,21 @@ struct FsmData void copy_from_cell(RTLIL::Cell *cell) { - num_inputs = cell->parameters["\\CTRL_IN_WIDTH"].as_int(); - num_outputs = cell->parameters["\\CTRL_OUT_WIDTH"].as_int(); + num_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int(); + num_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int(); - state_bits = cell->parameters["\\STATE_BITS"].as_int(); - reset_state = cell->parameters["\\STATE_RST"].as_int(); + state_bits = cell->parameters[ID::STATE_BITS].as_int(); + reset_state = cell->parameters[ID::STATE_RST].as_int(); - int state_num = cell->parameters["\\STATE_NUM"].as_int(); - int state_num_log2 = cell->parameters["\\STATE_NUM_LOG2"].as_int(); - int trans_num = cell->parameters["\\TRANS_NUM"].as_int(); + int state_num = cell->parameters[ID::STATE_NUM].as_int(); + int state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int(); + int trans_num = cell->parameters[ID::TRANS_NUM].as_int(); if (reset_state < 0 || reset_state >= state_num) reset_state = -1; - RTLIL::Const state_table = cell->parameters["\\STATE_TABLE"]; - RTLIL::Const trans_table = cell->parameters["\\TRANS_TABLE"]; + RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE]; + RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE]; for (int i = 0; i < state_num; i++) { RTLIL::Const state_code; @@ -134,7 +134,7 @@ struct FsmData { log("-------------------------------------\n"); log("\n"); - log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str()); + log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str()); log("\n"); log(" Number of input signals: %3d\n", num_inputs); log(" Number of output signals: %3d\n", num_outputs); @@ -142,13 +142,13 @@ struct FsmData log("\n"); log(" Input signals:\n"); - RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN"); + RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN); for (int i = 0; i < GetSize(sig_in); i++) log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); - RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT"); + RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT); for (int i = 0; i < GetSize(sig_out); i++) log(" %3d: %s\n", i, log_signal(sig_out[i])); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index fa4a8ea29..3880b19fe 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -42,11 +42,10 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, { std::set<RTLIL::IdString> found_celltypes; - for (auto i1 : design->modules_) - for (auto i2 : i1.second->cells_) + for (auto mod : design->modules()) + for (auto cell : mod->cells()) { - RTLIL::Cell *cell = i2.second; - if (design->has(cell->type)) + if (design->module(cell->type) != nullptr) continue; if (cell->type.begins_with("$__")) continue; @@ -62,15 +61,15 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, std::map<RTLIL::IdString, int> portwidths; log("Generate module for cell type %s:\n", celltype.c_str()); - for (auto i1 : design->modules_) - for (auto i2 : i1.second->cells_) - if (i2.second->type == celltype) { - for (auto &conn : i2.second->connections()) { + for (auto mod : design->modules()) + for (auto cell : mod->cells()) + if (cell->type == celltype) { + for (auto &conn : cell->connections()) { if (conn.first[0] != '$') portnames.insert(conn.first); portwidths[conn.first] = max(portwidths[conn.first], conn.second.size()); } - for (auto ¶ : i2.second->parameters) + for (auto ¶ : cell->parameters) parameters.insert(para.first); } @@ -121,7 +120,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; - mod->attributes["\\blackbox"] = RTLIL::Const(1); + mod->attributes[ID::blackbox] = RTLIL::Const(1); design->add(mod); for (auto &decl : ports) { @@ -167,27 +166,25 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // If any of the ports are actually interface ports, we will always need to // reprocess the module: - if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) { - for (auto &wire : module->wires_) { - if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) + if(!module->get_bool_attribute(ID::interfaces_replaced_in_module)) { + for (auto wire : module->wires()) { + if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface)) has_interface_ports = true; } } // Always keep track of all derived interfaces available in the current module in 'interfaces_in_module': dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module; - for (auto &cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; - if(cell->get_bool_attribute("\\is_interface")) { - RTLIL::Module *intf_module = design->modules_[cell->type]; + if(cell->get_bool_attribute(ID::is_interface)) { + RTLIL::Module *intf_module = design->module(cell->type); interfaces_in_module[cell->name] = intf_module; } } - for (auto &cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; bool has_interfaces_not_found = false; std::vector<RTLIL::IdString> connections_to_remove; @@ -208,11 +205,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule; dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule; - if (design->modules_.count(cell->type) == 0) + if (design->module(cell->type) == nullptr) { - if (design->modules_.count("$abstract" + cell->type.str())) + if (design->module("$abstract" + cell->type.str()) != nullptr) { - cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters); + cell->type = design->module("$abstract" + cell->type.str())->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; continue; @@ -246,7 +243,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check continue; loaded_module: - if (design->modules_.count(cell->type) == 0) + if (design->module(cell->type) == nullptr) log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str()); did_something = true; } else { @@ -256,24 +253,24 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to // some lists, so that the ports for sub-modules can be replaced further down: for (auto &conn : cell->connections()) { - if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list - //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type"); + if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list + //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_type); //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness) //} // Find if the sub-module has set a modport for the current interface connection: - const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport"); + const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_modport); std::string interface_modport = ""; for (auto &d : interface_modport_pool) { interface_modport = "\\" + d; } - if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { // Check if the connected wire is a potential interface in the parent module + if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute(ID::is_interface)) { // Check if the connected wire is a potential interface in the parent module std::string interface_name_str = conn.second.bits()[0].wire->name.str(); interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name interface_name_str = "\\" + interface_name_str; RTLIL::IdString interface_name = interface_name_str; bool not_found_interface = false; - if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either + if(module->get_bool_attribute(ID::interfaces_replaced_in_module)) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either // Check if the interface instance is present in module: // Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'. // Check for both of them here @@ -285,11 +282,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (nexactmatch != 0) // Choose the one with the plain name if it exists interface_name2 = interface_name; RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2); - for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists. - std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first); - std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first); + for (auto mod_wire : mod_replace_ports->wires()) { // Go over all wires in interface, and add replacements to lists. + std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire->name); + std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire); connections_to_add_name.push_back(RTLIL::IdString(signal_name1)); - if(module->wires_.count(signal_name2) == 0) { + if(module->wire(signal_name2) == nullptr) { log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name)); } else { @@ -312,7 +309,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // which will delay the expansion of this cell: if (not_found_interface) { // If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error: - if(!(module->get_bool_attribute("\\cells_not_processed"))) { + if(!(module->get_bool_attribute(ID::cells_not_processed))) { log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module)); } else { @@ -344,9 +341,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } } - RTLIL::Module *mod = design->modules_[cell->type]; + RTLIL::Module *mod = design->module(cell->type); - if (design->modules_.at(cell->type)->get_blackbox_attribute()) { + if (design->module(cell->type)->get_blackbox_attribute()) { if (flag_simcheck) log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n", cell->type.c_str(), module->name.c_str(), cell->name.c_str()); @@ -370,10 +367,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // If there are no overridden parameters AND not interfaces, then we can use the existing module instance as the type // for the cell: - if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) { + if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute(ID::module_not_derived)))) { // If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:", // so that the signals of the interface are added to the parent module. - if (mod->get_bool_attribute("\\is_interface")) { + if (mod->get_bool_attribute(ID::is_interface)) { goto handle_interface_instance; } continue; @@ -387,23 +384,23 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter // an interface instance: - if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) { - cell->set_bool_attribute("\\is_interface"); - RTLIL::Module *derived_module = design->modules_[cell->type]; + if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute(ID::module_not_derived)) { + cell->set_bool_attribute(ID::is_interface); + RTLIL::Module *derived_module = design->module(cell->type); interfaces_in_module[cell->name] = derived_module; did_something = true; } // We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell) - cell->attributes.erase("\\module_not_derived"); + cell->attributes.erase(ID::module_not_derived); } // Clear the attribute 'cells_not_processed' such that it can be known that we // have been through all cells at least once, and that we can know whether // to flag an error because of interface instances not found: - module->attributes.erase("\\cells_not_processed"); + module->attributes.erase(ID::cells_not_processed); // If any interface instances or interface ports were found in the module, we need to rederive it completely: - if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute("\\interfaces_replaced_in_module")) { + if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute(ID::interfaces_replaced_in_module)) { module->reprocess_module(design, interfaces_in_module); return did_something; } @@ -414,25 +411,25 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check RTLIL::Cell *cell = it.first; int idx = it.second.first, num = it.second.second; - if (design->modules_.count(cell->type) == 0) + if (design->module(cell->type) == nullptr) log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - RTLIL::Module *mod = design->modules_[cell->type]; + RTLIL::Module *mod = design->module(cell->type); for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); RTLIL::IdString portname = conn.first; if (portname.begins_with("$")) { int port_id = atoi(portname.substr(1).c_str()); - for (auto &wire_it : mod->wires_) - if (wire_it.second->port_id == port_id) { - portname = wire_it.first; + for (auto wire : mod->wires()) + if (wire->port_id == port_id) { + portname = wire->name; break; } } - if (mod->wires_.count(portname) == 0) + if (mod->wire(portname) == nullptr) log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); - int port_size = mod->wires_.at(portname)->width; + int port_size = mod->wire(portname)->width; if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) @@ -470,21 +467,21 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) hierarchy_worker(design, used, top, 0); std::vector<RTLIL::Module*> del_modules; - for (auto &it : design->modules_) - if (used.count(it.second) == 0) - del_modules.push_back(it.second); + for (auto mod : design->modules()) + if (used.count(mod) == 0) + del_modules.push_back(mod); else { // Now all interface ports must have been exploded, and it is hence // safe to delete all of the remaining dummy interface ports: pool<RTLIL::Wire*> del_wires; - for(auto &wire : it.second->wires_) { - if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) { - del_wires.insert(wire.second); + for(auto wire : mod->wires()) { + if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface)) { + del_wires.insert(wire); } } if (del_wires.size() > 0) { - it.second->remove(del_wires); - it.second->fixup_ports(); + mod->remove(del_wires); + mod->fixup_ports(); } } @@ -493,9 +490,8 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) if (!purge_lib && mod->get_blackbox_attribute()) continue; log("Removing unused module `%s'.\n", mod->name.c_str()); - design->modules_.erase(mod->name); + design->remove(mod); del_counter++; - delete mod; } log("Removed %d unused modules.\n", del_counter); @@ -506,7 +502,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover")) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) return cache[mod] = true; } return cache[mod]; @@ -536,11 +532,11 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db) RTLIL::Module *check_if_top_has_changed(Design *design, Module *top_mod) { - if(top_mod != NULL && top_mod->get_bool_attribute("\\initial_top")) + if(top_mod != NULL && top_mod->get_bool_attribute(ID::initial_top)) return top_mod; else { for (auto mod : design->modules()) { - if (mod->get_bool_attribute("\\top")) { + if (mod->get_bool_attribute(ID::top)) { return mod; } } @@ -817,9 +813,9 @@ struct HierarchyPass : public Pass { log_push(); if (top_mod == nullptr) - for (auto &mod_it : design->modules_) - if (mod_it.second->get_bool_attribute("\\top")) - top_mod = mod_it.second; + for (auto mod : design->modules()) + if (mod->get_bool_attribute(ID::top)) + top_mod = mod; if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) { IdString top_name = top_mod->name.substr(strlen("$abstract")); @@ -862,11 +858,11 @@ struct HierarchyPass : public Pass { log_error("Design has no top module.\n"); if (top_mod != NULL) { - for (auto &mod_it : design->modules_) - if (mod_it.second == top_mod) - mod_it.second->attributes["\\initial_top"] = RTLIL::Const(1); + for (auto mod : design->modules()) + if (mod == top_mod) + mod->attributes[ID::initial_top] = RTLIL::Const(1); else - mod_it.second->attributes.erase("\\initial_top"); + mod->attributes.erase(ID::initial_top); } bool did_something = true; @@ -900,9 +896,9 @@ struct HierarchyPass : public Pass { // Delete modules marked as 'to_delete': std::vector<RTLIL::Module *> modules_to_delete; - for(auto &mod_it : design->modules_) { - if (mod_it.second->get_bool_attribute("\\to_delete")) { - modules_to_delete.push_back(mod_it.second); + for(auto mod : design->modules()) { + if (mod->get_bool_attribute(ID::to_delete)) { + modules_to_delete.push_back(mod); } } for(size_t i=0; i<modules_to_delete.size(); i++) { @@ -917,12 +913,12 @@ struct HierarchyPass : public Pass { } if (top_mod != NULL) { - for (auto &mod_it : design->modules_) { - if (mod_it.second == top_mod) - mod_it.second->attributes["\\top"] = RTLIL::Const(1); + for (auto mod : design->modules()) { + if (mod == top_mod) + mod->attributes[ID::top] = RTLIL::Const(1); else - mod_it.second->attributes.erase("\\top"); - mod_it.second->attributes.erase("\\initial_top"); + mod->attributes.erase(ID::top); + mod->attributes.erase(ID::initial_top); } } @@ -931,7 +927,7 @@ struct HierarchyPass : public Pass { for (auto mod : design->modules()) if (set_keep_assert(cache, mod)) { log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", log_id(mod)); - mod->set_bool_attribute("\\keep"); + mod->set_bool_attribute(ID::keep); } } @@ -941,22 +937,20 @@ struct HierarchyPass : public Pass { std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map; std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work; - for (auto &mod_it : design->modules_) - for (auto &cell_it : mod_it.second->cells_) { - RTLIL::Cell *cell = cell_it.second; - if (design->modules_.count(cell->type) == 0) + for (auto mod : design->modules()) + for (auto cell : mod->cells()) { + if (design->module(cell->type) == nullptr) continue; for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { - pos_mods.insert(design->modules_.at(cell->type)); - pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell)); + pos_mods.insert(design->module(cell->type)); + pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod, cell)); break; } } for (auto module : pos_mods) - for (auto &wire_it : module->wires_) { - RTLIL::Wire *wire = wire_it.second; + for (auto wire : module->wires()) { if (wire->port_id > 0) pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name; } @@ -970,7 +964,7 @@ struct HierarchyPass : public Pass { for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); - std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id); + std::pair<RTLIL::Module*,int> key(design->module(cell->type), id); if (pos_map.count(key) == 0) { log(" Failed to map positional argument %d of cell %s.%s (%s).\n", id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); @@ -989,8 +983,8 @@ struct HierarchyPass : public Pass { { for (auto module : design->modules()) for (auto wire : module->wires()) - if (wire->port_input && wire->attributes.count("\\defaultvalue")) - defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue"); + if (wire->port_input && wire->attributes.count(ID::defaultvalue)) + defaults_db[module->name][wire->name] = wire->attributes.at(ID::defaultvalue); } // Process SV implicit wildcard port connections std::set<Module*> blackbox_derivatives; @@ -1000,7 +994,7 @@ struct HierarchyPass : public Pass { { for (auto cell : module->cells()) { - if (!cell->get_bool_attribute(ID(wildcard_port_conns))) + if (!cell->get_bool_attribute(ID::wildcard_port_conns)) continue; Module *m = design->module(cell->type); @@ -1009,7 +1003,7 @@ struct HierarchyPass : public Pass { RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); // Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths - if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { + if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) { IdString new_m_name = m->derive(design, cell->parameters, true); if (new_m_name.empty()) continue; @@ -1042,7 +1036,7 @@ struct HierarchyPass : public Pass { RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); cell->setPort(wire->name, parent_wire); } - cell->attributes.erase(ID(wildcard_port_conns)); + cell->attributes.erase(ID::wildcard_port_conns); } } @@ -1077,11 +1071,11 @@ struct HierarchyPass : public Pass { for (auto wire : module->wires()) { - if (wire->get_bool_attribute("\\wand")) { + if (wire->get_bool_attribute(ID::wand)) { wand_map[wire] = SigSpec(); wand_wor_index.insert(wire); } - if (wire->get_bool_attribute("\\wor")) { + if (wire->get_bool_attribute(ID::wor)) { wor_map[wire] = SigSpec(); wand_wor_index.insert(wire); } @@ -1192,7 +1186,7 @@ struct HierarchyPass : public Pass { if (m == nullptr) continue; - if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { + if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) { IdString new_m_name = m->derive(design, cell->parameters, true); if (new_m_name.empty()) continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 3b4f33a60..2db7cf26b 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -51,7 +51,7 @@ struct SubmodWorker RTLIL::Wire *new_wire; RTLIL::Const is_int_driven; bool is_int_used, is_ext_driven, is_ext_used; - wire_flags_t(RTLIL::Wire* wire) : new_wire(NULL), is_int_driven(State::S0, GetSize(wire)), is_int_used(false), is_ext_driven(false), is_ext_used(false) { } + wire_flags_t(RTLIL::Wire* wire) : new_wire(nullptr), is_int_driven(State::S0, GetSize(wire)), is_int_used(false), is_ext_driven(false), is_ext_used(false) { } }; std::map<RTLIL::Wire*, wire_flags_t> wire_flags; bool flag_found_something; @@ -75,7 +75,7 @@ struct SubmodWorker void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { for (auto &c : sig.chunks()) - if (c.wire != NULL) { + if (c.wire != nullptr) { flag_wire(c.wire, create, set_int_used, set_ext_driven, set_ext_used); if (set_int_driven) for (int i = c.offset; i < c.offset+c.width; i++) { @@ -100,8 +100,7 @@ struct SubmodWorker flag_signal(conn.second, true, true, true, false, false); } } - for (auto &it : module->cells_) { - RTLIL::Cell *cell = it.second; + for (auto cell : module->cells()) { if (submod.cells.count(cell) > 0) continue; if (ct.cell_known(cell->type)) { @@ -176,16 +175,16 @@ struct SubmodWorker new_wire->start_offset = wire->start_offset; new_wire->attributes = wire->attributes; if (!flags.is_int_driven.is_fully_zero()) { - new_wire->attributes.erase(ID(init)); + new_wire->attributes.erase(ID::init); auto sig = sigmap(wire); for (int i = 0; i < GetSize(sig); i++) { if (flags.is_int_driven[i] == State::S0) continue; if (!sig[i].wire) continue; - auto it = sig[i].wire->attributes.find(ID(init)); + auto it = sig[i].wire->attributes.find(ID::init); if (it != sig[i].wire->attributes.end()) { - auto jt = new_wire->attributes.insert(std::make_pair(ID(init), Const(State::Sx, GetSize(sig)))).first; + auto jt = new_wire->attributes.insert(std::make_pair(ID::init, Const(State::Sx, GetSize(sig)))).first; jt->second[i] = it->second[sig[i].offset]; it->second[sig[i].offset] = State::Sx; } @@ -211,7 +210,7 @@ struct SubmodWorker RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) - if (bit.wire != NULL) { + if (bit.wire != nullptr) { log_assert(wire_flags.count(bit.wire) > 0); bit.wire = wire_flags.at(bit.wire).new_wire; } @@ -274,24 +273,23 @@ struct SubmodWorker if (opt_name.empty()) { - for (auto &it : module->wires_) - it.second->attributes.erase("\\submod"); + for (auto wire : module->wires()) + wire->attributes.erase(ID::submod); - for (auto &it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = it.second; - if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) { - cell->attributes.erase("\\submod"); + if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].bits.size() == 0) { + cell->attributes.erase(ID::submod); continue; } - std::string submod_str = cell->attributes["\\submod"].decode_string(); - cell->attributes.erase("\\submod"); + std::string submod_str = cell->attributes[ID::submod].decode_string(); + cell->attributes.erase(ID::submod); if (submodules.count(submod_str) == 0) { submodules[submod_str].name = submod_str; submodules[submod_str].full_name = module->name.str() + "_" + submod_str; - while (design->modules_.count(submodules[submod_str].full_name) != 0 || + while (design->module(submodules[submod_str].full_name) != nullptr || module->count_id(submodules[submod_str].full_name) != 0) submodules[submod_str].full_name += "_"; } @@ -301,9 +299,8 @@ struct SubmodWorker } else { - for (auto &it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = it.second; if (!design->selected(module, cell)) continue; submodules[opt_name].name = opt_name; @@ -392,12 +389,12 @@ struct SubmodPass : public Pass { while (did_something) { did_something = false; std::vector<RTLIL::IdString> queued_modules; - for (auto &mod_it : design->modules_) - if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first)) - queued_modules.push_back(mod_it.first); + for (auto mod : design->modules()) + if (handled_modules.count(mod->name) == 0 && design->selected_whole_module(mod->name)) + queued_modules.push_back(mod->name); for (auto &modname : queued_modules) - if (design->modules_.count(modname) != 0) { - SubmodWorker worker(design, design->modules_[modname], copy_mode, hidden_mode); + if (design->module(modname) != nullptr) { + SubmodWorker worker(design, design->module(modname), copy_mode, hidden_mode); handled_modules.insert(modname); did_something = true; } @@ -407,15 +404,13 @@ struct SubmodPass : public Pass { } else { - RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules_) { - if (!design->selected_module(mod_it.first)) - continue; - if (module != NULL) - log_cmd_error("More than one module selected: %s %s\n", module->name.c_str(), mod_it.first.c_str()); - module = mod_it.second; + RTLIL::Module *module = nullptr; + for (auto mod : design->selected_modules()) { + if (module != nullptr) + log_cmd_error("More than one module selected: %s %s\n", module->name.c_str(), mod->name.c_str()); + module = mod; } - if (module == NULL) + if (module == nullptr) log("Nothing selected -> do nothing.\n"); else { Pass::call_on_module(design, module, "opt_clean"); diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc index ad3220918..5dbd15a7e 100644 --- a/passes/hierarchy/uniquify.cc +++ b/passes/hierarchy/uniquify.cc @@ -64,7 +64,7 @@ struct UniquifyPass : public Pass { for (auto module : design->selected_modules()) { - if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute("\\top")) + if (!module->get_bool_attribute(ID::unique) && !module->get_bool_attribute(ID::top)) continue; for (auto cell : module->selected_cells()) @@ -78,7 +78,7 @@ struct UniquifyPass : public Pass { if (tmod->get_blackbox_attribute()) continue; - if (tmod->get_bool_attribute("\\unique") && newname == tmod->name) + if (tmod->get_bool_attribute(ID::unique) && newname == tmod->name) continue; log("Creating module %s from %s.\n", log_id(newname), log_id(tmod)); @@ -86,9 +86,9 @@ struct UniquifyPass : public Pass { auto smod = tmod->clone(); smod->name = newname; cell->type = newname; - smod->set_bool_attribute("\\unique"); - if (smod->attributes.count("\\hdlname") == 0) - smod->attributes["\\hdlname"] = string(log_id(tmod->name)); + smod->set_bool_attribute(ID::unique); + if (smod->attributes.count(ID::hdlname) == 0) + smod->attributes[ID::hdlname] = string(log_id(tmod->name)); design->add(smod); did_something = true; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 24478f2ee..52ee1e99d 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -105,11 +105,11 @@ struct rules_t log_error("Bram %s variants %d and %d have different values for 'groups'.\n", log_id(name), variant, other.variant); if (abits != other.abits) - variant_params["\\CFG_ABITS"] = abits; + variant_params[ID::CFG_ABITS] = abits; if (dbits != other.dbits) - variant_params["\\CFG_DBITS"] = dbits; + variant_params[ID::CFG_DBITS] = dbits; if (init != other.init) - variant_params["\\CFG_INIT"] = init; + variant_params[ID::CFG_INIT] = init; for (int i = 0; i < groups; i++) { @@ -414,44 +414,44 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant); // bram.dump_config(); - int mem_size = cell->getParam("\\SIZE").as_int(); - int mem_abits = cell->getParam("\\ABITS").as_int(); - int mem_width = cell->getParam("\\WIDTH").as_int(); - // int mem_offset = cell->getParam("\\OFFSET").as_int(); + int mem_size = cell->getParam(ID::SIZE).as_int(); + int mem_abits = cell->getParam(ID::ABITS).as_int(); + int mem_width = cell->getParam(ID::WIDTH).as_int(); + // int mem_offset = cell->getParam(ID::OFFSET).as_int(); - bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef(); + bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef(); vector<Const> initdata; if (cell_init) { - Const initparam = cell->getParam("\\INIT"); + Const initparam = cell->getParam(ID::INIT); initdata.reserve(mem_size); for (int i=0; i < mem_size; i++) initdata.push_back(initparam.extract(mem_width*i, mem_width, State::Sx)); } - int wr_ports = cell->getParam("\\WR_PORTS").as_int(); - auto wr_clken = SigSpec(cell->getParam("\\WR_CLK_ENABLE")); - auto wr_clkpol = SigSpec(cell->getParam("\\WR_CLK_POLARITY")); + int wr_ports = cell->getParam(ID::WR_PORTS).as_int(); + auto wr_clken = SigSpec(cell->getParam(ID::WR_CLK_ENABLE)); + auto wr_clkpol = SigSpec(cell->getParam(ID::WR_CLK_POLARITY)); wr_clken.extend_u0(wr_ports); wr_clkpol.extend_u0(wr_ports); - SigSpec wr_en = cell->getPort("\\WR_EN"); - SigSpec wr_clk = cell->getPort("\\WR_CLK"); - SigSpec wr_data = cell->getPort("\\WR_DATA"); - SigSpec wr_addr = cell->getPort("\\WR_ADDR"); + SigSpec wr_en = cell->getPort(ID::WR_EN); + SigSpec wr_clk = cell->getPort(ID::WR_CLK); + SigSpec wr_data = cell->getPort(ID::WR_DATA); + SigSpec wr_addr = cell->getPort(ID::WR_ADDR); - int rd_ports = cell->getParam("\\RD_PORTS").as_int(); - auto rd_clken = SigSpec(cell->getParam("\\RD_CLK_ENABLE")); - auto rd_clkpol = SigSpec(cell->getParam("\\RD_CLK_POLARITY")); - auto rd_transp = SigSpec(cell->getParam("\\RD_TRANSPARENT")); + int rd_ports = cell->getParam(ID::RD_PORTS).as_int(); + auto rd_clken = SigSpec(cell->getParam(ID::RD_CLK_ENABLE)); + auto rd_clkpol = SigSpec(cell->getParam(ID::RD_CLK_POLARITY)); + auto rd_transp = SigSpec(cell->getParam(ID::RD_TRANSPARENT)); rd_clken.extend_u0(rd_ports); rd_clkpol.extend_u0(rd_ports); rd_transp.extend_u0(rd_ports); - SigSpec rd_en = cell->getPort("\\RD_EN"); - SigSpec rd_clk = cell->getPort("\\RD_CLK"); - SigSpec rd_data = cell->getPort("\\RD_DATA"); - SigSpec rd_addr = cell->getPort("\\RD_ADDR"); + SigSpec rd_en = cell->getPort(ID::RD_EN); + SigSpec rd_clk = cell->getPort(ID::RD_CLK); + SigSpec rd_data = cell->getPort(ID::RD_DATA); + SigSpec rd_addr = cell->getPort(ID::RD_ADDR); if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0) { @@ -915,7 +915,7 @@ grow_read_ports:; else initparam[i*bram.dbits+j] = padding; } - c->setParam("\\INIT", initparam); + c->setParam(ID::INIT, initparam); } for (auto &pi : portinfos) @@ -1048,14 +1048,14 @@ void handle_cell(Cell *cell, const rules_t &rules) { log("Processing %s.%s:\n", log_id(cell->module), log_id(cell)); - bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef(); + bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef(); dict<string, int> match_properties; - match_properties["words"] = cell->getParam("\\SIZE").as_int(); - match_properties["abits"] = cell->getParam("\\ABITS").as_int(); - match_properties["dbits"] = cell->getParam("\\WIDTH").as_int(); - match_properties["wports"] = cell->getParam("\\WR_PORTS").as_int(); - match_properties["rports"] = cell->getParam("\\RD_PORTS").as_int(); + match_properties["words"] = cell->getParam(ID::SIZE).as_int(); + match_properties["abits"] = cell->getParam(ID::ABITS).as_int(); + match_properties["dbits"] = cell->getParam(ID::WIDTH).as_int(); + match_properties["wports"] = cell->getParam(ID::WR_PORTS).as_int(); + match_properties["rports"] = cell->getParam(ID::RD_PORTS).as_int(); match_properties["bits"] = match_properties["words"] * match_properties["dbits"]; match_properties["ports"] = match_properties["wports"] + match_properties["rports"]; @@ -1357,7 +1357,7 @@ struct MemoryBramPass : public Pass { for (auto mod : design->selected_modules()) for (auto cell : mod->selected_cells()) - if (cell->type == "$mem") + if (cell->type == ID($mem)) handle_cell(cell, rules); } } MemoryBramPass; diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 9dcb3f024..a62dcc2c4 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -25,11 +25,11 @@ PRIVATE_NAMESPACE_BEGIN bool memcells_cmp(Cell *a, Cell *b) { - if (a->type == "$memrd" && b->type == "$memrd") + if (a->type == ID($memrd) && b->type == ID($memrd)) return a->name < b->name; - if (a->type == "$memrd" || b->type == "$memrd") - return (a->type == "$memrd") < (b->type == "$memrd"); - return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); + if (a->type == ID($memrd) || b->type == ID($memrd)) + return (a->type == ID($memrd)) < (b->type == ID($memrd)); + return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int(); } Cell *handle_memory(Module *module, RTLIL::Memory *memory) @@ -62,8 +62,8 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) for (auto &cell_it : module->cells_) { Cell *cell = cell_it.second; - if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) { - SigSpec addr = sigmap(cell->getPort("\\ADDR")); + if (cell->type.in(ID($memrd), ID($memwr), ID($meminit)) && memory->name == cell->parameters[ID::MEMID].decode_string()) { + SigSpec addr = sigmap(cell->getPort(ID::ADDR)); for (int i = 0; i < GetSize(addr); i++) if (addr[i] != State::S0) addr_bits = std::max(addr_bits, i+1); @@ -90,10 +90,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) { log(" %s (%s)\n", log_id(cell), log_id(cell->type)); - if (cell->type == "$meminit") + if (cell->type == ID($meminit)) { - SigSpec addr = sigmap(cell->getPort("\\ADDR")); - SigSpec data = sigmap(cell->getPort("\\DATA")); + SigSpec addr = sigmap(cell->getPort(ID::ADDR)); + SigSpec data = sigmap(cell->getPort(ID::DATA)); if (!addr.is_fully_const()) log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell)); @@ -112,14 +112,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) continue; } - if (cell->type == "$memwr") + if (cell->type == ID($memwr)) { - SigSpec clk = sigmap(cell->getPort("\\CLK")); - SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]); - SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]); - SigSpec addr = sigmap(cell->getPort("\\ADDR")); - SigSpec data = sigmap(cell->getPort("\\DATA")); - SigSpec en = sigmap(cell->getPort("\\EN")); + SigSpec clk = sigmap(cell->getPort(ID::CLK)); + SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]); + SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]); + SigSpec addr = sigmap(cell->getPort(ID::ADDR)); + SigSpec data = sigmap(cell->getPort(ID::DATA)); + SigSpec en = sigmap(cell->getPort(ID::EN)); if (!en.is_fully_zero()) { @@ -142,15 +142,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) continue; } - if (cell->type == "$memrd") + if (cell->type == ID($memrd)) { - SigSpec clk = sigmap(cell->getPort("\\CLK")); - SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]); - SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]); - SigSpec transparent = SigSpec(cell->parameters["\\TRANSPARENT"]); - SigSpec addr = sigmap(cell->getPort("\\ADDR")); - SigSpec data = sigmap(cell->getPort("\\DATA")); - SigSpec en = sigmap(cell->getPort("\\EN")); + SigSpec clk = sigmap(cell->getPort(ID::CLK)); + SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]); + SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]); + SigSpec transparent = SigSpec(cell->parameters[ID::TRANSPARENT]); + SigSpec addr = sigmap(cell->getPort(ID::ADDR)); + SigSpec data = sigmap(cell->getPort(ID::DATA)); + SigSpec en = sigmap(cell->getPort(ID::EN)); if (!en.is_fully_zero()) { @@ -178,13 +178,13 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) std::stringstream sstr; sstr << "$mem$" << memory->name.str() << "$" << (autoidx++); - Cell *mem = module->addCell(sstr.str(), "$mem"); - mem->parameters["\\MEMID"] = Const(memory->name.str()); - mem->parameters["\\WIDTH"] = Const(memory->width); - mem->parameters["\\OFFSET"] = Const(memory->start_offset); - mem->parameters["\\SIZE"] = Const(memory->size); - mem->parameters["\\ABITS"] = Const(addr_bits); - mem->parameters["\\INIT"] = init_data; + Cell *mem = module->addCell(sstr.str(), ID($mem)); + mem->parameters[ID::MEMID] = Const(memory->name.str()); + mem->parameters[ID::WIDTH] = Const(memory->width); + mem->parameters[ID::OFFSET] = Const(memory->start_offset); + mem->parameters[ID::SIZE] = Const(memory->size); + mem->parameters[ID::ABITS] = Const(addr_bits); + mem->parameters[ID::INIT] = init_data; log_assert(sig_wr_clk.size() == wr_ports); log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); @@ -193,14 +193,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) log_assert(sig_wr_data.size() == wr_ports * memory->width); log_assert(sig_wr_en.size() == wr_ports * memory->width); - mem->parameters["\\WR_PORTS"] = Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0; - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0; + mem->parameters[ID::WR_PORTS] = Const(wr_ports); + mem->parameters[ID::WR_CLK_ENABLE] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0; + mem->parameters[ID::WR_CLK_POLARITY] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0; - mem->setPort("\\WR_CLK", sig_wr_clk); - mem->setPort("\\WR_ADDR", sig_wr_addr); - mem->setPort("\\WR_DATA", sig_wr_data); - mem->setPort("\\WR_EN", sig_wr_en); + mem->setPort(ID::WR_CLK, sig_wr_clk); + mem->setPort(ID::WR_ADDR, sig_wr_addr); + mem->setPort(ID::WR_DATA, sig_wr_data); + mem->setPort(ID::WR_EN, sig_wr_en); log_assert(sig_rd_clk.size() == rd_ports); log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); @@ -208,15 +208,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) log_assert(sig_rd_addr.size() == rd_ports * addr_bits); log_assert(sig_rd_data.size() == rd_ports * memory->width); - mem->parameters["\\RD_PORTS"] = Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0; - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0; - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : State::S0; + mem->parameters[ID::RD_PORTS] = Const(rd_ports); + mem->parameters[ID::RD_CLK_ENABLE] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0; + mem->parameters[ID::RD_CLK_POLARITY] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0; + mem->parameters[ID::RD_TRANSPARENT] = rd_ports ? sig_rd_transparent.as_const() : State::S0; - mem->setPort("\\RD_CLK", sig_rd_clk); - mem->setPort("\\RD_ADDR", sig_rd_addr); - mem->setPort("\\RD_DATA", sig_rd_data); - mem->setPort("\\RD_EN", sig_rd_en); + mem->setPort(ID::RD_CLK, sig_rd_clk); + mem->setPort(ID::RD_ADDR, sig_rd_addr); + mem->setPort(ID::RD_DATA, sig_rd_data); + mem->setPort(ID::RD_EN, sig_rd_en); // Copy attributes from RTLIL memory to $mem for (auto attr : memory->attributes) diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index be4b3c100..726a5c1ff 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -39,10 +39,10 @@ struct MemoryDffWorker MemoryDffWorker(Module *module) : module(module), sigmap(module) { for (auto wire : module->wires()) { - if (wire->attributes.count("\\init") == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec sig = sigmap(wire); - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++) if (initval[i] == State::S0 || initval[i] == State::S1) init_bits.insert(sig[i]); @@ -66,8 +66,8 @@ struct MemoryDffWorker if (after && forward_merged_dffs.count(cell)) continue; - SigSpec this_clk = cell->getPort("\\CLK"); - bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); + SigSpec this_clk = cell->getPort(ID::CLK); + bool this_clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool(); if (invbits.count(this_clk)) { this_clk = invbits.at(this_clk); @@ -81,10 +81,10 @@ struct MemoryDffWorker continue; } - RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q"); + RTLIL::SigSpec q_norm = cell->getPort(after ? ID::D : ID::Q); sigmap.apply(q_norm); - RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D")); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? ID::Q : ID::D)); if (d.size() != 1) continue; @@ -113,19 +113,19 @@ struct MemoryDffWorker bool clk_polarity = 0; candidate_dffs.clear(); - RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); + RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR); if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) { log("no (compatible) $dff for address input found.\n"); return; } - RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); + RTLIL::SigSpec sig_data = cell->getPort(ID::DATA); if (!find_sig_before_dff(sig_data, clk, clk_polarity)) { log("no (compatible) $dff for data input found.\n"); return; } - RTLIL::SigSpec sig_en = cell->getPort("\\EN"); + RTLIL::SigSpec sig_en = cell->getPort(ID::EN); if (!find_sig_before_dff(sig_en, clk, clk_polarity)) { log("no (compatible) $dff for enable input found.\n"); return; @@ -136,12 +136,12 @@ struct MemoryDffWorker for (auto cell : candidate_dffs) forward_merged_dffs.insert(cell); - cell->setPort("\\CLK", clk); - cell->setPort("\\ADDR", sig_addr); - cell->setPort("\\DATA", sig_data); - cell->setPort("\\EN", sig_en); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); + cell->setPort(ID::CLK, clk); + cell->setPort(ID::ADDR, sig_addr); + cell->setPort(ID::DATA, sig_data); + cell->setPort(ID::EN, sig_en); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); return; @@ -161,10 +161,10 @@ struct MemoryDffWorker RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); for (auto cell : module->cells()) - if (cell->type == "$dff") { - RTLIL::SigSpec new_q = cell->getPort("\\Q"); + if (cell->type == ID($dff)) { + RTLIL::SigSpec new_q = cell->getPort(ID::Q); new_q.replace(sig, new_sig); - cell->setPort("\\Q", new_q); + cell->setPort(ID::Q, new_q); } } @@ -175,7 +175,7 @@ struct MemoryDffWorker bool clk_polarity = 0; RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); + RTLIL::SigSpec sig_data = cell->getPort(ID::DATA); for (auto bit : sigmap(sig_data)) if (sigbit_users_count[bit] > 1) @@ -189,9 +189,9 @@ struct MemoryDffWorker do { bool enable_invert = mux_cells_a.count(sig_data) != 0; Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"))); - sig_data = sigmap(mux->getPort("\\Y")); - en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); + check_q.push_back(sigmap(mux->getPort(enable_invert ? ID::B : ID::A))); + sig_data = sigmap(mux->getPort(ID::Y)); + en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort(ID::S)) : mux->getPort(ID::S)); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); for (auto bit : sig_data) @@ -202,12 +202,12 @@ struct MemoryDffWorker std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; })) { disconnect_dff(sig_data); - cell->setPort("\\CLK", clk_data); - cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en); - cell->setPort("\\DATA", sig_data); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); - cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); + cell->setPort(ID::CLK, clk_data); + cell->setPort(ID::EN, en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en); + cell->setPort(ID::DATA, sig_data); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity); + cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0); log("merged data $dff with rd enable to cell.\n"); return; } @@ -217,12 +217,12 @@ struct MemoryDffWorker if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) { disconnect_dff(sig_data); - cell->setPort("\\CLK", clk_data); - cell->setPort("\\EN", State::S1); - cell->setPort("\\DATA", sig_data); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); - cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); + cell->setPort(ID::CLK, clk_data); + cell->setPort(ID::EN, State::S1); + cell->setPort(ID::DATA, sig_data); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity); + cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0); log("merged data $dff to cell.\n"); return; } @@ -230,16 +230,16 @@ struct MemoryDffWorker skip_ff_after_read_merging:; RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); + RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR); if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) && clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->setPort("\\CLK", clk_addr); - cell->setPort("\\EN", State::S1); - cell->setPort("\\ADDR", sig_addr); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); - cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1); + cell->setPort(ID::CLK, clk_addr); + cell->setPort(ID::EN, State::S1); + cell->setPort(ID::ADDR, sig_addr); + cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity); + cell->parameters[ID::TRANSPARENT] = RTLIL::Const(1); log("merged address $dff to cell.\n"); return; } @@ -256,18 +256,18 @@ struct MemoryDffWorker } for (auto cell : module->cells()) { - if (cell->type == "$dff") + if (cell->type == ID($dff)) dff_cells.push_back(cell); - if (cell->type == "$mux") { - mux_cells_a[sigmap(cell->getPort("\\A"))] = cell; - mux_cells_b[sigmap(cell->getPort("\\B"))] = cell; + if (cell->type == ID($mux)) { + mux_cells_a[sigmap(cell->getPort(ID::A))] = cell; + mux_cells_b[sigmap(cell->getPort(ID::B))] = cell; } - if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_y = cell->getPort("\\Y"); - if (cell->type == "$not") - sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool()); - if (cell->type == "$logic_not") + if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) { + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_y = cell->getPort(ID::Y); + if (cell->type == ID($not)) + sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + if (cell->type == ID($logic_not)) sig_y.extend_u0(1); for (int i = 0; i < GetSize(sig_y); i++) invbits[sig_y[i]] = sig_a[i]; @@ -279,12 +279,12 @@ struct MemoryDffWorker } for (auto cell : module->selected_cells()) - if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + if (cell->type == ID($memwr) && !cell->parameters[ID::CLK_ENABLE].as_bool()) handle_wr_cell(cell); if (!flag_wr_only) for (auto cell : module->selected_cells()) - if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + if (cell->type == ID($memrd) && !cell->parameters[ID::CLK_ENABLE].as_bool()) handle_rd_cell(cell); } }; diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 65bccb5ef..da0673c8f 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -81,15 +81,15 @@ struct MemoryMapWorker std::set<int> static_ports; std::map<int, RTLIL::SigSpec> static_cells_map; - int wr_ports = cell->parameters["\\WR_PORTS"].as_int(); - int rd_ports = cell->parameters["\\RD_PORTS"].as_int(); + int wr_ports = cell->parameters[ID::WR_PORTS].as_int(); + int rd_ports = cell->parameters[ID::RD_PORTS].as_int(); - int mem_size = cell->parameters["\\SIZE"].as_int(); - int mem_width = cell->parameters["\\WIDTH"].as_int(); - int mem_offset = cell->parameters["\\OFFSET"].as_int(); - int mem_abits = cell->parameters["\\ABITS"].as_int(); + int mem_size = cell->parameters[ID::SIZE].as_int(); + int mem_width = cell->parameters[ID::WIDTH].as_int(); + int mem_offset = cell->parameters[ID::OFFSET].as_int(); + int mem_abits = cell->parameters[ID::ABITS].as_int(); - SigSpec init_data = cell->getParam("\\INIT"); + SigSpec init_data = cell->getParam(ID::INIT); init_data.extend_u0(mem_size*mem_width, true); // delete unused memory cell @@ -99,22 +99,22 @@ struct MemoryMapWorker } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); - RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; - RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; + RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK); + RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY]; + RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE]; clocks_pol.bits.resize(wr_ports); clocks_en.bits.resize(wr_ports); RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -155,21 +155,21 @@ struct MemoryMapWorker } else { - RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), ID($dff)); + c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH]; if (clocks_pol.bits.size() > 0) { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->setPort("\\CLK", clocks.extract(0, 1)); + c->parameters[ID::CLK_POLARITY] = RTLIL::Const(clocks_pol.bits[0]); + c->setPort(ID::CLK, clocks.extract(0, 1)); } else { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1); + c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0)); } RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->setPort("\\D", data_reg_in.back()); + c->setPort(ID::D, data_reg_in.back()); - std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); + std::string w_out_name = stringf("%s[%d]", cell->parameters[ID::MEMID].decode_string().c_str(), i); if (module->wires_.count(w_out_name) > 0) w_out_name = genid(cell->name, "", i, "$q"); @@ -177,10 +177,10 @@ struct MemoryMapWorker SigSpec w_init = init_data.extract(i*mem_width, mem_width); if (!w_init.is_fully_undef()) - w_out->attributes["\\init"] = w_init.as_const(); + w_out->attributes[ID::init] = w_init.as_const(); data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->setPort("\\Q", data_reg_out.back()); + c->setPort(ID::Q, data_reg_out.back()); } } @@ -188,55 +188,55 @@ struct MemoryMapWorker int count_dff = 0, count_mux = 0, count_wrmux = 0; - for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) + for (int i = 0; i < cell->parameters[ID::RD_PORTS].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->getPort(ID::RD_ADDR).extract(i*mem_abits, mem_abits); if (mem_offset) rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr))); std::vector<RTLIL::SigSpec> rd_signals; - rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->getPort(ID::RD_DATA).extract(i*mem_width, mem_width)); - if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) + if (cell->parameters[ID::RD_CLK_ENABLE].bits[i] == RTLIL::State::S1) { RTLIL::Cell *dff_cell = nullptr; - if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) + if (cell->parameters[ID::RD_TRANSPARENT].bits[i] == RTLIL::State::S1) { - dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - dff_cell->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); - dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - dff_cell->setPort("\\D", rd_addr); + dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff)); + dff_cell->parameters[ID::WIDTH] = RTLIL::Const(mem_abits); + dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]); + dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1)); + dff_cell->setPort(ID::D, rd_addr); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); - dff_cell->setPort("\\Q", RTLIL::SigSpec(w)); + dff_cell->setPort(ID::Q, RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); } else { - dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - dff_cell->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - dff_cell->setPort("\\Q", rd_signals.back()); + dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff)); + dff_cell->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH]; + dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]); + dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1)); + dff_cell->setPort(ID::Q, rd_signals.back()); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - dff_cell->setPort("\\D", rd_signals.back()); + dff_cell->setPort(ID::D, rd_signals.back()); } - SigBit en_bit = cell->getPort("\\RD_EN").extract(i); + SigBit en_bit = cell->getPort(ID::RD_EN).extract(i); if (en_bit != State::S1) { SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i), - dff_cell->getPort("\\Q"), dff_cell->getPort("\\D"), en_bit); - dff_cell->setPort("\\D", new_d); + dff_cell->getPort(ID::Q), dff_cell->getPort(ID::D), en_bit); + dff_cell->setPort(ID::D, new_d); } } @@ -246,17 +246,17 @@ struct MemoryMapWorker for (size_t k = 0; k < rd_signals.size(); k++) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->setPort("\\Y", rd_signals[k]); - c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), ID($mux)); + c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH]; + c->setPort(ID::Y, rd_signals[k]); + c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1)); count_mux++; - c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); - c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); + c->setPort(ID::A, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort(ID::B, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - next_rd_signals.push_back(c->getPort("\\A")); - next_rd_signals.push_back(c->getPort("\\B")); + next_rd_signals.push_back(c->getPort(ID::A)); + next_rd_signals.push_back(c->getPort(ID::B)); } next_rd_signals.swap(rd_signals); @@ -275,11 +275,11 @@ struct MemoryMapWorker RTLIL::SigSpec sig = data_reg_out[i]; - for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) + for (int j = 0; j < cell->parameters[ID::WR_PORTS].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(j*mem_width, mem_width); if (mem_offset) wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr))); @@ -303,27 +303,27 @@ struct MemoryMapWorker if (wr_bit != State::S1) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", w); - c->setPort("\\B", wr_bit); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), ID($and)); + c->parameters[ID::A_SIGNED] = RTLIL::Const(0); + c->parameters[ID::B_SIGNED] = RTLIL::Const(0); + c->parameters[ID::A_WIDTH] = RTLIL::Const(1); + c->parameters[ID::B_WIDTH] = RTLIL::Const(1); + c->parameters[ID::Y_WIDTH] = RTLIL::Const(1); + c->setPort(ID::A, w); + c->setPort(ID::B, wr_bit); w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); - c->setPort("\\Y", RTLIL::SigSpec(w)); + c->setPort(ID::Y, RTLIL::SigSpec(w)); } - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); - c->parameters["\\WIDTH"] = wr_width; - c->setPort("\\A", sig.extract(wr_offset, wr_width)); - c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); - c->setPort("\\S", RTLIL::SigSpec(w)); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), ID($mux)); + c->parameters[ID::WIDTH] = wr_width; + c->setPort(ID::A, sig.extract(wr_offset, wr_width)); + c->setPort(ID::B, wr_data.extract(wr_offset, wr_width)); + c->setPort(ID::S, RTLIL::SigSpec(w)); w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); - c->setPort("\\Y", w); + c->setPort(ID::Y, w); sig.replace(wr_offset, w); wr_offset += wr_width; @@ -343,7 +343,7 @@ struct MemoryMapWorker { std::vector<RTLIL::Cell*> cells; for (auto cell : module->selected_cells()) - if (cell->type == "$mem" && design->selected(module, cell)) + if (cell->type == ID($mem)) cells.push_back(cell); for (auto cell : cells) handle_cell(cell); diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 958370164..5d5f61c7d 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -47,18 +47,18 @@ struct MemoryMemxPass : public Pass { vector<Cell*> mem_port_cells; for (auto cell : module->selected_cells()) - if (cell->type.in("$memrd", "$memwr")) + if (cell->type.in(ID($memrd), ID($memwr))) mem_port_cells.push_back(cell); for (auto cell : mem_port_cells) { - IdString memid = cell->getParam("\\MEMID").decode_string(); + IdString memid = cell->getParam(ID::MEMID).decode_string(); RTLIL::Memory *mem = module->memories.at(memid); int lowest_addr = mem->start_offset; int highest_addr = mem->start_offset + mem->size - 1; - SigSpec addr = cell->getPort("\\ADDR"); + SigSpec addr = cell->getPort(ID::ADDR); addr.extend_u0(32); SigSpec addr_ok = module->Nex(NEW_ID, module->ReduceXor(NEW_ID, addr), module->ReduceXor(NEW_ID, {addr, State::S1})); @@ -66,23 +66,23 @@ struct MemoryMemxPass : public Pass { addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Ge(NEW_ID, addr, lowest_addr)); addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Le(NEW_ID, addr, highest_addr)); - if (cell->type == "$memrd") + if (cell->type == ID($memrd)) { - if (cell->getParam("\\CLK_ENABLE").as_bool()) + if (cell->getParam(ID::CLK_ENABLE).as_bool()) log_error("Cell %s.%s (%s) has an enabled clock. Clocked $memrd cells are not supported by memory_memx!\n", log_id(module), log_id(cell), log_id(cell->type)); - SigSpec rdata = cell->getPort("\\DATA"); + SigSpec rdata = cell->getPort(ID::DATA); Wire *raw_rdata = module->addWire(NEW_ID, GetSize(rdata)); module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(rdata)), raw_rdata, addr_ok, rdata); - cell->setPort("\\DATA", raw_rdata); + cell->setPort(ID::DATA, raw_rdata); } - if (cell->type == "$memwr") + if (cell->type == ID($memwr)) { - SigSpec en = cell->getPort("\\EN"); + SigSpec en = cell->getPort(ID::EN); en = module->And(NEW_ID, en, addr_ok.repeat(GetSize(en))); - cell->setPort("\\EN", en); + cell->setPort(ID::EN, en); } } } diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc index ba0361c0f..487785397 100644 --- a/passes/memory/memory_nordff.cc +++ b/passes/memory/memory_nordff.cc @@ -52,19 +52,19 @@ struct MemoryNordffPass : public Pass { for (auto module : design->selected_modules()) for (auto cell : vector<Cell*>(module->selected_cells())) { - if (cell->type != "$mem") + if (cell->type != ID($mem)) continue; - int rd_ports = cell->getParam("\\RD_PORTS").as_int(); - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); + int rd_ports = cell->getParam(ID::RD_PORTS).as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); - SigSpec rd_addr = cell->getPort("\\RD_ADDR"); - SigSpec rd_data = cell->getPort("\\RD_DATA"); - SigSpec rd_clk = cell->getPort("\\RD_CLK"); - SigSpec rd_en = cell->getPort("\\RD_EN"); - Const rd_clk_enable = cell->getParam("\\RD_CLK_ENABLE"); - Const rd_clk_polarity = cell->getParam("\\RD_CLK_POLARITY"); + SigSpec rd_addr = cell->getPort(ID::RD_ADDR); + SigSpec rd_data = cell->getPort(ID::RD_DATA); + SigSpec rd_clk = cell->getPort(ID::RD_CLK); + SigSpec rd_en = cell->getPort(ID::RD_EN); + Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE); + Const rd_clk_polarity = cell->getParam(ID::RD_CLK_POLARITY); for (int i = 0; i < rd_ports; i++) { @@ -72,11 +72,11 @@ struct MemoryNordffPass : public Pass { if (clk_enable) { - bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1; - bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1; + bool clk_polarity = cell->getParam(ID::RD_CLK_POLARITY)[i] == State::S1; + bool transparent = cell->getParam(ID::RD_TRANSPARENT)[i] == State::S1; - SigSpec clk = cell->getPort("\\RD_CLK")[i] ; - SigSpec en = cell->getPort("\\RD_EN")[i]; + SigSpec clk = cell->getPort(ID::RD_CLK)[i] ; + SigSpec en = cell->getPort(ID::RD_EN)[i]; Cell *c; if (transparent) @@ -108,12 +108,12 @@ struct MemoryNordffPass : public Pass { rd_clk_polarity[i] = State::S1; } - cell->setPort("\\RD_ADDR", rd_addr); - cell->setPort("\\RD_DATA", rd_data); - cell->setPort("\\RD_CLK", rd_clk); - cell->setPort("\\RD_EN", rd_en); - cell->setParam("\\RD_CLK_ENABLE", rd_clk_enable); - cell->setParam("\\RD_CLK_POLARITY", rd_clk_polarity); + cell->setPort(ID::RD_ADDR, rd_addr); + cell->setPort(ID::RD_DATA, rd_data); + cell->setPort(ID::RD_CLK, rd_clk); + cell->setPort(ID::RD_EN, rd_en); + cell->setParam(ID::RD_CLK_ENABLE, rd_clk_enable); + cell->setParam(ID::RD_CLK_POLARITY, rd_clk_polarity); } } } MemoryNordffPass; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index eb912cfd4..477246687 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -27,11 +27,11 @@ PRIVATE_NAMESPACE_BEGIN bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) { - if (a->type == "$memrd" && b->type == "$memrd") + if (a->type == ID($memrd) && b->type == ID($memrd)) return a->name < b->name; - if (a->type == "$memrd" || b->type == "$memrd") - return (a->type == "$memrd") < (b->type == "$memrd"); - return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); + if (a->type == ID($memrd) || b->type == ID($memrd)) + return (a->type == ID($memrd)) < (b->type == ID($memrd)); + return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int(); } struct MemoryShareWorker @@ -64,18 +64,18 @@ struct MemoryShareWorker RTLIL::Cell *cell = sig_to_mux.at(sig).first; int bit_idx = sig_to_mux.at(sig).second; - std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); - std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); - std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S")); - std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A)); + std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B)); + std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S)); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y)); log_assert(sig_y.at(bit_idx) == sig); for (int i = 0; i < int(sig_s.size()); i++) if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) { - RTLIL::SigSpec new_b = cell->getPort("\\B"); + RTLIL::SigSpec new_b = cell->getPort(ID::B); new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); - cell->setPort("\\B", new_b); + cell->setPort(ID::B, new_b); } return false; } @@ -90,9 +90,9 @@ struct MemoryShareWorker new_state[sig_s[i]] = true; if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) { - RTLIL::SigSpec new_b = cell->getPort("\\B"); + RTLIL::SigSpec new_b = cell->getPort(ID::B); new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); - cell->setPort("\\B", new_b); + cell->setPort(ID::B, new_b); } } @@ -101,9 +101,9 @@ struct MemoryShareWorker new_state[sig_s[i]] = false; if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) { - RTLIL::SigSpec new_a = cell->getPort("\\A"); + RTLIL::SigSpec new_a = cell->getPort(ID::A); new_a.replace(bit_idx, RTLIL::State::Sx); - cell->setPort("\\A", new_a); + cell->setPort(ID::A, new_a); } return false; @@ -120,8 +120,8 @@ struct MemoryShareWorker for (auto &cond : conditions) { RTLIL::SigSpec sig1, sig2; for (auto &it : cond) { - sig1.append_bit(it.first); - sig2.append_bit(it.second ? RTLIL::State::S1 : RTLIL::State::S0); + sig1.append(it.first); + sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0); } terms.append(module->Ne(NEW_ID, sig1, sig2)); created_conditions++; @@ -155,12 +155,12 @@ struct MemoryShareWorker { bool ignore_data_port = false; - if (cell->type.in("$mux", "$pmux")) + if (cell->type.in(ID($mux), ID($pmux))) { - std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); - std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); - std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S")); - std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A)); + std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B)); + std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S)); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y)); non_feedback_nets.insert(sig_s.begin(), sig_s.end()); @@ -173,13 +173,13 @@ struct MemoryShareWorker continue; } - if (cell->type.in("$memwr", "$memrd") && - cell->parameters.at("\\MEMID").decode_string() == memid) + if (cell->type.in(ID($memwr), ID($memrd)) && + cell->parameters.at(ID::MEMID).decode_string() == memid) ignore_data_port = true; for (auto conn : cell->connections()) { - if (ignore_data_port && conn.first == "\\DATA") + if (ignore_data_port && conn.first == ID::DATA) continue; std::vector<RTLIL::SigBit> bits = sigmap(conn.second); non_feedback_nets.insert(bits.begin(), bits.end()); @@ -204,11 +204,11 @@ struct MemoryShareWorker for (auto cell : rd_ports) { - if (cell->parameters.at("\\CLK_ENABLE").as_bool()) + if (cell->parameters.at(ID::CLK_ENABLE).as_bool()) continue; - RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR")); - std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort("\\DATA")); + RTLIL::SigSpec sig_addr = sigmap(cell->getPort(ID::ADDR)); + std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort(ID::DATA)); for (int i = 0; i < int(sig_data.size()); i++) if (non_feedback_nets.count(sig_data[i])) @@ -228,14 +228,14 @@ struct MemoryShareWorker for (auto cell : wr_ports) { - RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR")); + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort(ID::ADDR)); if (!async_rd_bits.count(sig_addr)) continue; log(" Analyzing write port %s.\n", log_id(cell)); - std::vector<RTLIL::SigBit> cell_data = cell->getPort("\\DATA"); - std::vector<RTLIL::SigBit> cell_en = cell->getPort("\\EN"); + std::vector<RTLIL::SigBit> cell_data = cell->getPort(ID::DATA); + std::vector<RTLIL::SigBit> cell_en = cell->getPort(ID::EN); int created_conditions = 0; for (int i = 0; i < int(cell_data.size()); i++) @@ -250,7 +250,7 @@ struct MemoryShareWorker if (created_conditions) { log(" Added enable logic for %d different cases.\n", created_conditions); - cell->setPort("\\EN", cell_en); + cell->setPort(ID::EN, cell_en); } } } @@ -284,8 +284,8 @@ struct MemoryShareWorker std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]); if (groups.count(key) == 0) { groups[key].first = grouped_bits.size(); - grouped_bits.append_bit(v_bits[i]); - grouped_mask_bits.append_bit(v_mask_bits[i]); + grouped_bits.append(v_bits[i]); + grouped_mask_bits.append(v_mask_bits[i]); } groups[key].second.push_back(i); } @@ -295,7 +295,7 @@ struct MemoryShareWorker for (int i = 0; i < bits.size(); i++) { std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]); - result.append_bit(grouped_result.at(groups.at(key).first)); + result.append(grouped_result.at(groups.at(key).first)); } return result; @@ -326,7 +326,7 @@ struct MemoryShareWorker for (int i = 0; i < int(v_old_en.size()); i++) { std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]); - new_merged_en.append_bit(grouped_new_en.at(groups.at(key))); + new_merged_en.append(grouped_new_en.at(groups.at(key))); } // Create the new merged_data signal. @@ -368,15 +368,15 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) { RTLIL::Cell *cell = wr_ports.at(i); - RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR")); + RTLIL::SigSpec addr = sigmap_xmux(cell->getPort(ID::ADDR)); - if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || - cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) + if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable || + (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk || + cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity))) { - cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); - cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->getPort("\\CLK")); + cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool(); + cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool(); + cache_clk = sigmap(cell->getPort(ID::CLK)); last_port_by_addr.clear(); if (cache_clk_enable) @@ -388,7 +388,7 @@ struct MemoryShareWorker log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); log(" Active bits: "); - std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN")); + std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN)); active_bits_on_port.push_back(std::vector<bool>(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) { active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; @@ -410,13 +410,13 @@ struct MemoryShareWorker // Force this ports addr input to addr directly (skip don't care muxes) - cell->setPort("\\ADDR", addr); + cell->setPort(ID::ADDR, addr); // If any of the ports between `last_i' and `i' write to the same address, this // will have priority over whatever `last_i` wrote. So we need to revisit those // ports and mask the EN bits accordingly. - RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN")); + RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort(ID::EN)); for (int j = last_i+1; j < i; j++) { @@ -431,20 +431,20 @@ struct MemoryShareWorker found_overlapping_bits_i_j: log(" Creating collosion-detect logic for port %d.\n", j); RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); - module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr); - merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN"))); + module->addEq(NEW_ID, addr, wr_ports[j]->getPort(ID::ADDR), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort(ID::EN))); } } // Then we need to merge the (masked) EN and the DATA signals. - RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA"); + RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort(ID::DATA); if (found_overlapping_bits) { log(" Creating logic for merging DATA and EN ports.\n"); - merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA"))); + merge_en_data(merged_en, merged_data, sigmap(cell->getPort(ID::EN)), sigmap(cell->getPort(ID::DATA))); } else { - RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN")); - RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA")); + RTLIL::SigSpec cell_en = sigmap(cell->getPort(ID::EN)); + RTLIL::SigSpec cell_data = sigmap(cell->getPort(ID::DATA)); for (int k = 0; k < int(en_bits.size()); k++) if (!active_bits_on_port[last_i][k]) { merged_en.replace(k, cell_en.extract(k, 1)); @@ -454,14 +454,14 @@ struct MemoryShareWorker // Connect the new EN and DATA signals and remove the old write port. - cell->setPort("\\EN", merged_en); - cell->setPort("\\DATA", merged_data); + cell->setPort(ID::EN, merged_en); + cell->setPort(ID::DATA, merged_data); module->remove(wr_ports[last_i]); wr_ports[last_i] = NULL; log(" Active bits: "); - std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN")); + std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN)); active_bits_on_port.push_back(std::vector<bool>(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) log("%c", active_bits_on_port[i][k] ? '1' : '0'); @@ -500,7 +500,7 @@ struct MemoryShareWorker std::set<int> considered_port_pairs; for (int i = 0; i < int(wr_ports.size()); i++) { - std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); + std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort(ID::EN)); for (auto bit : bits) if (bit == RTLIL::State::S1) goto port_is_always_active; @@ -519,13 +519,13 @@ struct MemoryShareWorker { RTLIL::Cell *cell = wr_ports.at(i); - if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || - cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) + if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable || + (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk || + cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity))) { - cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); - cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->getPort("\\CLK")); + cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool(); + cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool(); + cache_clk = sigmap(cell->getPort(ID::CLK)); } else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) considered_port_pairs.insert(i); @@ -554,7 +554,7 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) { - RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); + RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort(ID::EN)); port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig)); std::vector<RTLIL::SigBit> bits = sig; @@ -564,7 +564,7 @@ struct MemoryShareWorker while (!bits_queue.empty()) { for (auto bit : bits_queue) - if (bit.wire && bit.wire->get_bool_attribute("\\onehot")) + if (bit.wire && bit.wire->get_bool_attribute(ID::onehot)) one_hot_wires.insert(bit.wire); pool<ModWalker::PortBit> portbits; @@ -609,13 +609,13 @@ struct MemoryShareWorker log(" Merging port %d into port %d.\n", i-1, i); port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); - RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR"); - RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA"); - std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN")); + RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort(ID::ADDR); + RTLIL::SigSpec last_data = wr_ports[i-1]->getPort(ID::DATA); + std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort(ID::EN)); - RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR"); - RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA"); - std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); + RTLIL::SigSpec this_addr = wr_ports[i]->getPort(ID::ADDR); + RTLIL::SigSpec this_data = wr_ports[i]->getPort(ID::DATA); + std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort(ID::EN)); RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); @@ -624,9 +624,9 @@ struct MemoryShareWorker else this_addr.extend_u0(GetSize(last_addr)); - wr_ports[i]->setParam("\\ABITS", GetSize(this_addr)); - wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); - wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); + wr_ports[i]->setParam(ID::ABITS, GetSize(this_addr)); + wr_ports[i]->setPort(ID::ADDR, module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); + wr_ports[i]->setPort(ID::DATA, module->Mux(NEW_ID, last_data, this_data, this_en_active)); std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; @@ -635,8 +635,8 @@ struct MemoryShareWorker for (int j = 0; j < int(this_en.size()); j++) { std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]); if (!groups_en.count(key)) { - grouped_last_en.append_bit(last_en[j]); - grouped_this_en.append_bit(this_en[j]); + grouped_last_en.append(last_en[j]); + grouped_this_en.append(this_en[j]); groups_en[key] = grouped_en->width; grouped_en->width++; } @@ -644,7 +644,7 @@ struct MemoryShareWorker } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); - wr_ports[i]->setPort("\\EN", en); + wr_ports[i]->setPort(ID::EN, en); module->remove(wr_ports[i-1]); wr_ports[i-1] = NULL; @@ -665,34 +665,40 @@ struct MemoryShareWorker // Setup and run // ------------- - MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) : - design(design), module(module), sigmap(module) + MemoryShareWorker(RTLIL::Design *design) : design(design), modwalker(design) {} + + void operator()(RTLIL::Module* module) { std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex; + this->module = module; + sigmap.set(module); + sig_to_mux.clear(); + conditions_logic_cache.clear(); + sigmap_xmux = sigmap; for (auto cell : module->cells()) { - if (cell->type == "$memrd") - memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell); + if (cell->type == ID($memrd)) + memindex[cell->parameters.at(ID::MEMID).decode_string()].first.push_back(cell); - if (cell->type == "$memwr") - memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell); + if (cell->type == ID($memwr)) + memindex[cell->parameters.at(ID::MEMID).decode_string()].second.push_back(cell); - if (cell->type == "$mux") + if (cell->type == ID($mux)) { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A")); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B")); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A)); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B)); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->getPort("\\Y"), sig_b); + sigmap_xmux.add(cell->getPort(ID::Y), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->getPort("\\Y"), sig_a); + sigmap_xmux.add(cell->getPort(ID::Y), sig_a); } - if (cell->type.in("$mux", "$pmux")) + if (cell->type.in(ID($mux), ID($pmux))) { - std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y)); for (int i = 0; i < int(sig_y.size()); i++) sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i); } @@ -706,18 +712,18 @@ struct MemoryShareWorker } cone_ct.setup_internals(); - cone_ct.cell_types.erase("$mul"); - cone_ct.cell_types.erase("$mod"); - cone_ct.cell_types.erase("$div"); - cone_ct.cell_types.erase("$pow"); - cone_ct.cell_types.erase("$shl"); - cone_ct.cell_types.erase("$shr"); - cone_ct.cell_types.erase("$sshl"); - cone_ct.cell_types.erase("$sshr"); - cone_ct.cell_types.erase("$shift"); - cone_ct.cell_types.erase("$shiftx"); - - modwalker.setup(design, module, &cone_ct); + cone_ct.cell_types.erase(ID($mul)); + cone_ct.cell_types.erase(ID($mod)); + cone_ct.cell_types.erase(ID($div)); + cone_ct.cell_types.erase(ID($pow)); + cone_ct.cell_types.erase(ID($shl)); + cone_ct.cell_types.erase(ID($shr)); + cone_ct.cell_types.erase(ID($sshl)); + cone_ct.cell_types.erase(ID($sshr)); + cone_ct.cell_types.erase(ID($shift)); + cone_ct.cell_types.erase(ID($shiftx)); + + modwalker.setup(module, &cone_ct); for (auto &it : memindex) consolidate_wr_using_sat(it.first, it.second.second); @@ -755,8 +761,10 @@ struct MemorySharePass : public Pass { void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); + MemoryShareWorker msw(design); + for (auto module : design->selected_modules()) - MemoryShareWorker(design, module); + msw(module); } } MemorySharePass; diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 49ec66792..9173c791b 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -31,53 +31,53 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) log("Creating $memrd and $memwr for memory `%s' in module `%s':\n", memory->name.c_str(), module->name.c_str()); - RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string()); + RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at(ID::MEMID).decode_string()); while (module->memories.count(mem_name) != 0) mem_name = mem_name.str() + stringf("_%d", autoidx++); RTLIL::Memory *mem = new RTLIL::Memory; mem->name = mem_name; - mem->width = memory->parameters.at("\\WIDTH").as_int(); - mem->start_offset = memory->parameters.at("\\OFFSET").as_int(); - mem->size = memory->parameters.at("\\SIZE").as_int(); + mem->width = memory->parameters.at(ID::WIDTH).as_int(); + mem->start_offset = memory->parameters.at(ID::OFFSET).as_int(); + mem->size = memory->parameters.at(ID::SIZE).as_int(); module->memories[mem_name] = mem; - int abits = memory->parameters.at("\\ABITS").as_int(); - int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int(); - int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int(); + int abits = memory->parameters.at(ID::ABITS).as_int(); + int num_rd_ports = memory->parameters.at(ID::RD_PORTS).as_int(); + int num_wr_ports = memory->parameters.at(ID::WR_PORTS).as_int(); for (int i = 0; i < num_rd_ports; i++) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd"); - cell->parameters["\\MEMID"] = mem_name.str(); - cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); - cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); - cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); - cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); - cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); - cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1)); - cell->setPort("\\EN", memory->getPort("\\RD_EN").extract(i, 1)); - cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits)); - cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width)); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memrd)); + cell->parameters[ID::MEMID] = mem_name.str(); + cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS); + cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH); + cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_ENABLE)).extract(i, 1).as_const(); + cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_POLARITY)).extract(i, 1).as_const(); + cell->parameters[ID::TRANSPARENT] = RTLIL::SigSpec(memory->parameters.at(ID::RD_TRANSPARENT)).extract(i, 1).as_const(); + cell->setPort(ID::CLK, memory->getPort(ID::RD_CLK).extract(i, 1)); + cell->setPort(ID::EN, memory->getPort(ID::RD_EN).extract(i, 1)); + cell->setPort(ID::ADDR, memory->getPort(ID::RD_ADDR).extract(i*abits, abits)); + cell->setPort(ID::DATA, memory->getPort(ID::RD_DATA).extract(i*mem->width, mem->width)); } for (int i = 0; i < num_wr_ports; i++) { - RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr"); - cell->parameters["\\MEMID"] = mem_name.str(); - cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); - cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); - cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); - cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); - cell->parameters["\\PRIORITY"] = i; - cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1)); - cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width)); - cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits)); - cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width)); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memwr)); + cell->parameters[ID::MEMID] = mem_name.str(); + cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS); + cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH); + cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_ENABLE)).extract(i, 1).as_const(); + cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_POLARITY)).extract(i, 1).as_const(); + cell->parameters[ID::PRIORITY] = i; + cell->setPort(ID::CLK, memory->getPort(ID::WR_CLK).extract(i, 1)); + cell->setPort(ID::EN, memory->getPort(ID::WR_EN).extract(i*mem->width, mem->width)); + cell->setPort(ID::ADDR, memory->getPort(ID::WR_ADDR).extract(i*abits, abits)); + cell->setPort(ID::DATA, memory->getPort(ID::WR_DATA).extract(i*mem->width, mem->width)); } - Const initval = memory->parameters.at("\\INIT"); + Const initval = memory->parameters.at(ID::INIT); RTLIL::Cell *last_init_cell = nullptr; SigSpec last_init_data; int last_init_addr=0; @@ -90,19 +90,19 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) continue; found_non_undef_initval: if (last_init_cell && last_init_addr+1 == i/mem->width) { - last_init_cell->parameters["\\WORDS"] = last_init_cell->parameters["\\WORDS"].as_int() + 1; + last_init_cell->parameters[ID::WORDS] = last_init_cell->parameters[ID::WORDS].as_int() + 1; last_init_data.append(val); last_init_addr++; } else { if (last_init_cell) - last_init_cell->setPort("\\DATA", last_init_data); - RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit"); - cell->parameters["\\MEMID"] = mem_name.str(); - cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); - cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); - cell->parameters["\\WORDS"] = 1; - cell->parameters["\\PRIORITY"] = i/mem->width; - cell->setPort("\\ADDR", SigSpec(i/mem->width, abits)); + last_init_cell->setPort(ID::DATA, last_init_data); + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($meminit)); + cell->parameters[ID::MEMID] = mem_name.str(); + cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS); + cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH); + cell->parameters[ID::WORDS] = 1; + cell->parameters[ID::PRIORITY] = i/mem->width; + cell->setPort(ID::ADDR, SigSpec(i/mem->width, abits)); last_init_cell = cell; last_init_addr = i/mem->width; last_init_data = val; @@ -110,7 +110,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) } if (last_init_cell) - last_init_cell->setPort("\\DATA", last_init_data); + last_init_cell->setPort(ID::DATA, last_init_data); module->remove(memory); } @@ -119,7 +119,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector<RTLIL::IdString> memcells; for (auto &cell_it : module->cells_) - if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second)) + if (cell_it.second->type == ID($mem) && design->selected(module, cell_it.second)) memcells.push_back(cell_it.first); for (auto &it : memcells) handle_memory(module, module->cells_.at(it)); diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index c40c02acd..9df49ab3c 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -208,8 +208,8 @@ struct MuxpackWorker { Cell *prev_cell = sig_chain_prev.at(a_sig); log_assert(prev_cell); - SigSpec s_sig = sigmap(cell->getPort(ID(S))); - s_sig.append(sigmap(prev_cell->getPort(ID(S)))); + SigSpec s_sig = sigmap(cell->getPort(ID::S)); + s_sig.append(sigmap(prev_cell->getPort(ID::S))); if (!excl_db.query(s_sig)) goto start_cell; } @@ -271,26 +271,26 @@ struct MuxpackWorker first_cell->type = ID($pmux); SigSpec b_sig = first_cell->getPort(ID::B); - SigSpec s_sig = first_cell->getPort(ID(S)); + SigSpec s_sig = first_cell->getPort(ID::S); for (int i = 1; i < cases; i++) { Cell* prev_cell = chain[cursor+i-1]; Cell* cursor_cell = chain[cursor+i]; if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) { b_sig.append(cursor_cell->getPort(ID::B)); - s_sig.append(cursor_cell->getPort(ID(S))); + s_sig.append(cursor_cell->getPort(ID::S)); } else { log_assert(cursor_cell->type == ID($mux)); b_sig.append(cursor_cell->getPort(ID::A)); - s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID(S)))); + s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S))); } remove_cells.insert(cursor_cell); } first_cell->setPort(ID::B, b_sig); - first_cell->setPort(ID(S), s_sig); - first_cell->setParam(ID(S_WIDTH), GetSize(s_sig)); + first_cell->setPort(ID::S, s_sig); + first_cell->setParam(ID::S_WIDTH, GetSize(s_sig)); first_cell->setPort(ID::Y, last_cell->getPort(ID::Y)); cursor += cases; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index cac265a52..da3961218 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -183,8 +183,8 @@ void rmunused_module_cells(Module *module, bool verbose) int count_nontrivial_wire_attrs(RTLIL::Wire *w) { int count = w->attributes.size(); - count -= w->attributes.count(ID(src)); - count -= w->attributes.count(ID(unused_bits)); + count -= w->attributes.count(ID::src); + count -= w->attributes.count(ID::unused_bits); return count; } @@ -203,8 +203,8 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo return !(w2->port_input && w2->port_output); if (w1->name[0] == '\\' && w2->name[0] == '\\') { - if (regs.check_any(s1) != regs.check_any(s2)) - return regs.check_any(s2); + if (regs.check(s1) != regs.check(s2)) + return regs.check(s2); if (direct_wires.count(w1) != direct_wires.count(w2)) return direct_wires.count(w2) != 0; if (conns.check_any(s1) != conns.check_any(s2)) @@ -317,12 +317,12 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos log_assert(GetSize(s1) == GetSize(s2)); Const initval; - if (wire->attributes.count(ID(init))) - initval = wire->attributes.at(ID(init)); + if (wire->attributes.count(ID::init)) + initval = wire->attributes.at(ID::init); if (GetSize(initval) != GetSize(wire)) initval.bits.resize(GetSize(wire), State::Sx); if (initval.is_fully_undef()) - wire->attributes.erase(ID(init)); + wire->attributes.erase(ID::init); if (GetSize(wire) == 0) { // delete zero-width wires, unless they are module ports @@ -358,14 +358,14 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos s2[i] = initval[i]; initval[i] = State::Sx; } - new_conn.first.append_bit(s1[i]); - new_conn.second.append_bit(s2[i]); + new_conn.first.append(s1[i]); + new_conn.second.append(s2[i]); } if (new_conn.first.size() > 0) { if (initval.is_fully_undef()) - wire->attributes.erase(ID(init)); + wire->attributes.erase(ID::init); else - wire->attributes.at(ID(init)) = initval; + wire->attributes.at(ID::init) = initval; used_signals.add(new_conn.first); used_signals.add(new_conn.second); module->connect(new_conn); @@ -383,11 +383,11 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos } } if (unused_bits.empty() || wire->port_id != 0) - wire->attributes.erase(ID(unused_bits)); + wire->attributes.erase(ID::unused_bits); else - wire->attributes[ID(unused_bits)] = RTLIL::Const(unused_bits); + wire->attributes[ID::unused_bits] = RTLIL::Const(unused_bits); } else { - wire->attributes.erase(ID(unused_bits)); + wire->attributes.erase(ID::unused_bits); } } } @@ -419,18 +419,18 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) dict<SigBit, State> qbits; for (auto cell : module->cells()) - if (fftypes.cell_known(cell->type) && cell->hasPort(ID(Q))) + if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q)) { - SigSpec sig = cell->getPort(ID(Q)); + SigSpec sig = cell->getPort(ID::Q); for (int i = 0; i < GetSize(sig); i++) { SigBit bit = sig[i]; - if (bit.wire == nullptr || bit.wire->attributes.count(ID(init)) == 0) + if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0) continue; - Const init = bit.wire->attributes.at(ID(init)); + Const init = bit.wire->attributes.at(ID::init); if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz) continue; @@ -445,10 +445,10 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) if (!purge_mode && wire->name[0] == '\\') continue; - if (wire->attributes.count(ID(init)) == 0) + if (wire->attributes.count(ID::init) == 0) continue; - Const init = wire->attributes.at(ID(init)); + Const init = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++) { @@ -471,7 +471,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) if (verbose) log_debug(" removing redundant init attribute on %s.\n", log_id(wire)); - wire->attributes.erase(ID(init)); + wire->attributes.erase(ID::init); did_something = true; next_wire:; } @@ -487,7 +487,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool std::vector<RTLIL::Cell*> delcells; for (auto cell : module->cells()) if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) { - bool is_signed = cell->type == ID($pos) && cell->getParam(ID(A_SIGNED)).as_bool(); + bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool(); RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec y = cell->getPort(ID::Y); a.extend_u0(GetSize(y), is_signed); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 4a2f170b8..1a4dd9239 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -31,9 +31,8 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; -void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) +void replace_undriven(RTLIL::Module *module, const CellTypes &ct) { - CellTypes ct(design); SigMap sigmap(module); SigPool driven_signals; SigPool used_signals; @@ -51,9 +50,9 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } for (auto wire : module->wires()) { - if (wire->attributes.count(ID(init))) { + if (wire->attributes.count(ID::init)) { SigSpec sig = sigmap(wire); - Const initval = wire->attributes.at(ID(init)); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) { if (initval[i] == State::S0 || initval[i] == State::S1) initbits[sig[i]] = make_pair(wire, initval[i]); @@ -99,18 +98,18 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) for (auto wire : revisit_initwires) { SigSpec sig = sm2(wire); - Const initval = wire->attributes.at(ID(init)); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) { if (SigBit(initval[i]) == sig[i]) initval[i] = State::Sx; } if (initval.is_fully_undef()) { log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire)); - wire->attributes.erase(ID(init)); + wire->attributes.erase(ID::init); did_something = true; - } else if (initval != wire->attributes.at(ID(init))) { + } else if (initval != wire->attributes.at(ID::init)) { log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval)); - wire->attributes[ID(init)] = initval; + wire->attributes[ID::init] = initval; did_something = true; } } @@ -137,7 +136,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ { IdString b_name = cell->hasPort(ID::B) ? ID::B : ID::A; - bool a_signed = cell->parameters.at(ID(A_SIGNED)).as_bool(); + bool a_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); bool b_signed = cell->parameters.at(b_name.str() + "_SIGNED").as_bool(); RTLIL::SigSpec sig_a = sigmap(cell->getPort(ID::A)); @@ -193,11 +192,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ for (auto &it : grouped_bits[i]) { for (auto &bit : it.second) { - new_conn.first.append_bit(bit); - new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size())); + new_conn.first.append(bit); + new_conn.second.append(RTLIL::SigBit(new_y, new_a.size())); } - new_a.append_bit(it.first.first); - new_b.append_bit(it.first.second); + new_a.append(it.first.first); + new_b.append(it.first.second); } if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) { @@ -210,17 +209,17 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); c->setPort(ID::A, new_a); - c->parameters[ID(A_WIDTH)] = new_a.size(); - c->parameters[ID(A_SIGNED)] = false; + c->parameters[ID::A_WIDTH] = new_a.size(); + c->parameters[ID::A_SIGNED] = false; if (b_name == ID::B) { c->setPort(ID::B, new_b); - c->parameters[ID(B_WIDTH)] = new_b.size(); - c->parameters[ID(B_SIGNED)] = false; + c->parameters[ID::B_WIDTH] = new_b.size(); + c->parameters[ID::B_SIGNED] = false; } c->setPort(ID::Y, new_y); - c->parameters[ID(Y_WIDTH)] = new_y->width; + c->parameters[ID::Y_WIDTH] = new_y->width; c->check(); module->connect(new_conn); @@ -373,7 +372,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A)); if (cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0)) - invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID(S))); + invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::S)); if (ct_combinational.cell_known(cell->type)) for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = assign_map(conn.second); @@ -402,36 +401,36 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (clkinv) { if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr))) - handle_polarity_inv(cell, ID(CLK), ID(CLK_POLARITY), assign_map, invert_map); + handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map); if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) { - handle_polarity_inv(cell, ID(SET), ID(SET_POLARITY), assign_map, invert_map); - handle_polarity_inv(cell, ID(CLR), ID(CLR_POLARITY), assign_map, invert_map); + handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map); + handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map); } if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr))) - handle_polarity_inv(cell, ID(EN), ID(EN_POLARITY), assign_map, invert_map); + handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID(S), assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID(R), assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID(C), assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID(C), assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID(E), assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID(C), assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID(R), assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID(C), assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID(S), assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID(R), assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID(E), assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID(E), assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID(S), assign_map, invert_map); - handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID(R), assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map); + handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map); } bool detect_const_and = false; @@ -440,13 +439,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($reduce_and), ID($_AND_))) detect_const_and = true; - if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()) + if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()) detect_const_and = true; if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_))) detect_const_or = true; - if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()) + if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()) detect_const_or = true; if (detect_const_and || detect_const_or) @@ -496,6 +495,42 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } + if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())) + { + SigBit sig_a = assign_map(cell->getPort(ID::A)); + SigBit sig_b = assign_map(cell->getPort(ID::B)); + if (!sig_a.wire) + std::swap(sig_a, sig_b); + if (sig_b == State::S0 || sig_b == State::S1) { + if (cell->type.in(ID($xor), ID($_XOR_))) { + cover("opt.opt_expr.xor_buffer"); + SigSpec sig_y; + if (cell->type == ID($xor)) + sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a); + else if (cell->type == ID($_XOR_)) + sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); + else log_abort(); + replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y); + goto next_cell; + } + if (cell->type.in(ID($xnor), ID($_XNOR_))) { + cover("opt.opt_expr.xnor_buffer"); + SigSpec sig_y; + if (cell->type == ID($xnor)) { + sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit()); + int width = cell->getParam(ID::Y_WIDTH).as_int(); + sig_y.append(RTLIL::Const(State::S1, width-1)); + } + else if (cell->type == ID($_XNOR_)) + sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); + else log_abort(); + replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y); + goto next_cell; + } + log_abort(); + } + } + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) { @@ -536,7 +571,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a)); cell->setPort(ID::A, new_sig_a); - cell->parameters.at(ID(A_WIDTH)) = GetSize(new_sig_a); + cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a); did_something = true; } } @@ -559,7 +594,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b)); cell->setPort(ID::B, new_sig_b); - cell->parameters.at(ID(B_WIDTH)) = GetSize(new_sig_b); + cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b); did_something = true; } } @@ -585,7 +620,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(ID::A, sig_a = new_a); - cell->parameters.at(ID(A_WIDTH)) = 1; + cell->parameters.at(ID::A_WIDTH) = 1; did_something = true; } } @@ -611,7 +646,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(ID::A, sig_a = new_a); - cell->parameters.at(ID(A_WIDTH)) = 1; + cell->parameters.at(ID::A_WIDTH) = 1; did_something = true; } } @@ -637,7 +672,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort(ID::B, sig_b = new_b); - cell->parameters.at(ID(B_WIDTH)) = 1; + cell->parameters.at(ID::B_WIDTH) = 1; did_something = true; } } @@ -651,10 +686,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons int i; for (i = 0; i < GetSize(sig_y); i++) { - if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) - module->connect(sig_y[i], sig_a[i]); - else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) - module->connect(sig_y[i], sig_b[i]); + RTLIL::SigBit b = sig_b.at(i, State::Sx); + RTLIL::SigBit a = sig_a.at(i, State::Sx); + if (b == State::S0 && a != State::Sx) + module->connect(sig_y[i], a); + else if (sub && b == State::S1 && a == State::S1) + module->connect(sig_y[i], State::S0); + else if (!sub && a == State::S0 && b != State::Sx) + module->connect(sig_y[i], b); else break; } @@ -668,18 +707,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == "$alu") + if (cell->type == ID($alu)) { RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); - RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI))); - RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI))); - RTLIL::SigSpec sig_x = cell->getPort(ID(X)); + RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI)); + RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI)); + RTLIL::SigSpec sig_x = cell->getPort(ID::X); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); - RTLIL::SigSpec sig_co = cell->getPort(ID(CO)); - - if (sig_ci.wire || sig_bi.wire) - goto next_cell; + RTLIL::SigSpec sig_co = cell->getPort(ID::CO); bool sub = (sig_ci == State::S1 && sig_bi == State::S1); @@ -690,14 +726,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons int i; for (i = 0; i < GetSize(sig_y); i++) { - if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) { - module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]); + RTLIL::SigBit b = sig_b.at(i, State::Sx); + RTLIL::SigBit a = sig_a.at(i, State::Sx); + if (b == State::S0 && a != State::Sx) { module->connect(sig_y[i], sig_a[i]); + module->connect(sig_x[i], sub ? module->Not(NEW_ID, a).as_bit() : a); module->connect(sig_co[i], sub ? State::S1 : State::S0); } - else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) { - module->connect(sig_x[i], sig_b[i]); - module->connect(sig_y[i], sig_b[i]); + else if (sub && b == State::S1 && a == State::S1) { + module->connect(sig_y[i], State::S0); + module->connect(sig_x[i], module->Not(NEW_ID, a)); + module->connect(sig_co[i], State::S0); + } + else if (!sub && a == State::S0 && b != State::Sx) { + module->connect(sig_y[i], b); + module->connect(sig_x[i], b); module->connect(sig_co[i], State::S0); } else @@ -707,9 +750,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover("opt.opt_expr.fine.$alu"); cell->setPort(ID::A, sig_a.extract_end(i)); cell->setPort(ID::B, sig_b.extract_end(i)); - cell->setPort(ID(X), sig_x.extract_end(i)); + cell->setPort(ID::X, sig_x.extract_end(i)); cell->setPort(ID::Y, sig_y.extract_end(i)); - cell->setPort(ID(CO), sig_co.extract_end(i)); + cell->setPort(ID::CO, sig_co.extract_end(i)); cell->fixup_parameters(); did_something = true; } @@ -761,7 +804,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str()); sig_a.remove(width, GetSize(sig_a)-width); cell->setPort(ID::A, sig_a); - cell->setParam(ID(A_WIDTH), width); + cell->setParam(ID::A_WIDTH, width); did_something = true; goto next_cell; } @@ -774,13 +817,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons goto next_cell; } - if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID(S)))) != 0) { + if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) { cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str()); log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module)); RTLIL::SigSpec tmp = cell->getPort(ID::A); cell->setPort(ID::A, cell->getPort(ID::B)); cell->setPort(ID::B, tmp); - cell->setPort(ID(S), invert_map.at(assign_map(cell->getPort(ID(S))))); + cell->setPort(ID::S, invert_map.at(assign_map(cell->getPort(ID::S)))); did_something = true; goto next_cell; } @@ -842,13 +885,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (input.match("11")) ACTION_DO_Y(0); if (input.match(" *")) ACTION_DO_Y(x); if (input.match("* ")) ACTION_DO_Y(x); - if (input.match(" 0")) ACTION_DO(ID::Y, input.extract(1, 1)); - if (input.match("0 ")) ACTION_DO(ID::Y, input.extract(0, 1)); } if (cell->type == ID($_MUX_)) { RTLIL::SigSpec input; - input.append(cell->getPort(ID(S))); + input.append(cell->getPort(ID::S)); input.append(cell->getPort(ID::B)); input.append(cell->getPort(ID::A)); assign_map.apply(input); @@ -862,7 +903,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->type = ID($_NOT_); cell->setPort(ID::A, input.extract(0, 1)); cell->unsetPort(ID::B); - cell->unsetPort(ID(S)); + cell->unsetPort(ID::S); goto next_cell; } if (input.match("11 ")) ACTION_DO_Y(1); @@ -878,7 +919,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (cell->type.in(ID($_TBUF_), ID($tribuf))) { - RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID(E) : ID(EN)); + RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID::E : ID::EN); RTLIL::SigSpec a = cell->getPort(ID::A); assign_map.apply(input); assign_map.apply(a); @@ -899,10 +940,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec b = cell->getPort(ID::B); - if (cell->parameters[ID(A_WIDTH)].as_int() != cell->parameters[ID(B_WIDTH)].as_int()) { - int width = max(cell->parameters[ID(A_WIDTH)].as_int(), cell->parameters[ID(B_WIDTH)].as_int()); - a.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()); - b.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()); + if (cell->parameters[ID::A_WIDTH].as_int() != cell->parameters[ID::B_WIDTH].as_int()) { + int width = max(cell->parameters[ID::A_WIDTH].as_int(), cell->parameters[ID::B_WIDTH].as_int()); + a.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()); + b.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()); } RTLIL::SigSpec new_a, new_b; @@ -912,7 +953,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1); - new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false); + new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false); replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y); goto next_cell; } @@ -925,7 +966,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (new_a.size() == 0) { cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0); - new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false); + new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false); replace_cell(assign_map, module, cell, "empty", ID::Y, new_y); goto next_cell; } @@ -934,13 +975,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cell->setPort(ID::A, new_a); cell->setPort(ID::B, new_b); - cell->parameters[ID(A_WIDTH)] = new_a.size(); - cell->parameters[ID(B_WIDTH)] = new_b.size(); + cell->parameters[ID::A_WIDTH] = new_a.size(); + cell->parameters[ID::B_WIDTH] = new_b.size(); } } - if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID(Y_WIDTH)].as_int() == 1 && - cell->parameters[ID(A_WIDTH)].as_int() == 1 && cell->parameters[ID(B_WIDTH)].as_int() == 1) + if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 && + cell->parameters[ID::A_WIDTH].as_int() == 1 && cell->parameters[ID::B_WIDTH].as_int() == 1) { RTLIL::SigSpec a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec b = assign_map(cell->getPort(ID::B)); @@ -964,8 +1005,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->type = ID($not); - cell->parameters.erase(ID(B_WIDTH)); - cell->parameters.erase(ID(B_SIGNED)); + cell->parameters.erase(ID::B_WIDTH); + cell->parameters.erase(ID::B_SIGNED); cell->unsetPort(ID::B); did_something = true; } @@ -982,29 +1023,29 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); if (assign_map(cell->getPort(ID::A)).is_fully_zero()) { cell->setPort(ID::A, cell->getPort(ID::B)); - cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED))); - cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH))); + cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED)); + cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH)); } cell->unsetPort(ID::B); - cell->unsetParam(ID(B_SIGNED)); - cell->unsetParam(ID(B_WIDTH)); + cell->unsetParam(ID::B_SIGNED); + cell->unsetParam(ID::B_WIDTH); did_something = true; goto next_cell; } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && assign_map(cell->getPort(ID::B)).is_fully_const()) { - bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID(A_SIGNED)).as_bool(); - int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID(B_SIGNED)).as_bool()); + bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID::A_SIGNED).as_bool(); + int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool()); if (cell->type.in(ID($shl), ID($sshl))) shift_bits *= -1; RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); - RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID(Y_WIDTH)).as_int()); + RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int()); if (GetSize(sig_a) < GetSize(sig_y)) - sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID(A_SIGNED)).as_bool()); + sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_y); i++) { int idx = i + shift_bits; @@ -1032,12 +1073,26 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons bool identity_wrt_b = false; bool arith_inverse = false; - if (cell->type.in(ID($add), ID($sub), ID($or), ID($xor))) + if (cell->type.in(ID($add), ID($sub), ID($alu), ID($or), ID($xor))) { RTLIL::SigSpec a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec b = assign_map(cell->getPort(ID::B)); - if (cell->type != ID($sub) && a.is_fully_const() && a.as_bool() == false) + bool sub = cell->type == ID($sub); + + if (cell->type == ID($alu)) { + RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI)); + RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI)); + + sub = (sig_ci == State::S1 && sig_bi == State::S1); + + // If not a subtraction, yet there is a carry or B is inverted + // then no optimisation is possible as carry will not be constant + if (!sub && (sig_ci != State::S0 || sig_bi != State::S0)) + goto next_cell; + } + + if (!sub && a.is_fully_const() && a.as_bool() == false) identity_wrt_b = true; if (b.is_fully_const() && b.as_bool() == false) @@ -1057,10 +1112,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec b = assign_map(cell->getPort(ID::B)); - if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID(A_SIGNED)).as_bool(), arith_inverse)) + if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID::A_SIGNED).as_bool(), arith_inverse)) identity_wrt_b = true; else - if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID(B_SIGNED)).as_bool(), arith_inverse)) + if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID::B_SIGNED).as_bool(), arith_inverse)) identity_wrt_a = true; } @@ -1075,23 +1130,33 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (identity_wrt_a || identity_wrt_b) { if (identity_wrt_a) - cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); + cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); if (identity_wrt_b) - cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); + cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); + if (cell->type == ID($alu)) { + int y_width = GetSize(cell->getPort(ID::Y)); + module->connect(cell->getPort(ID::X), RTLIL::Const(State::S0, y_width)); + module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S0, y_width)); + cell->unsetPort(ID::BI); + cell->unsetPort(ID::CI); + cell->unsetPort(ID::X); + cell->unsetPort(ID::CO); + } + if (!identity_wrt_a) { cell->setPort(ID::A, cell->getPort(ID::B)); - cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH)); - cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED)); + cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH)); + cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED)); } cell->type = arith_inverse ? ID($neg) : ID($pos); cell->unsetPort(ID::B); - cell->parameters.erase(ID(B_WIDTH)); - cell->parameters.erase(ID(B_SIGNED)); + cell->parameters.erase(ID::B_WIDTH); + cell->parameters.erase(ID::B_SIGNED); cell->check(); did_something = true; @@ -1102,7 +1167,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) { cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str()); - replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID(S))); + replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID::S)); goto next_cell; } @@ -1110,15 +1175,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) { cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); - cell->setPort(ID::A, cell->getPort(ID(S))); + cell->setPort(ID::A, cell->getPort(ID::S)); cell->unsetPort(ID::B); - cell->unsetPort(ID(S)); + cell->unsetPort(ID::S); if (cell->type == ID($mux)) { - Const width = cell->parameters[ID(WIDTH)]; - cell->parameters[ID(A_WIDTH)] = width; - cell->parameters[ID(Y_WIDTH)] = width; - cell->parameters[ID(A_SIGNED)] = 0; - cell->parameters.erase(ID(WIDTH)); + Const width = cell->parameters[ID::WIDTH]; + cell->parameters[ID::A_WIDTH] = width; + cell->parameters[ID::Y_WIDTH] = width; + cell->parameters[ID::A_SIGNED] = 0; + cell->parameters.erase(ID::WIDTH); cell->type = ID($not); } else cell->type = ID($_NOT_); @@ -1129,16 +1194,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) { cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); - cell->setPort(ID::A, cell->getPort(ID(S))); - cell->unsetPort(ID(S)); + cell->setPort(ID::A, cell->getPort(ID::S)); + cell->unsetPort(ID::S); if (cell->type == ID($mux)) { - Const width = cell->parameters[ID(WIDTH)]; - cell->parameters[ID(A_WIDTH)] = width; - cell->parameters[ID(B_WIDTH)] = width; - cell->parameters[ID(Y_WIDTH)] = width; - cell->parameters[ID(A_SIGNED)] = 0; - cell->parameters[ID(B_SIGNED)] = 0; - cell->parameters.erase(ID(WIDTH)); + Const width = cell->parameters[ID::WIDTH]; + cell->parameters[ID::A_WIDTH] = width; + cell->parameters[ID::B_WIDTH] = width; + cell->parameters[ID::Y_WIDTH] = width; + cell->parameters[ID::A_SIGNED] = 0; + cell->parameters[ID::B_SIGNED] = 0; + cell->parameters.erase(ID::WIDTH); cell->type = ID($and); } else cell->type = ID($_AND_); @@ -1149,16 +1214,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) { cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); - cell->setPort(ID::B, cell->getPort(ID(S))); - cell->unsetPort(ID(S)); + cell->setPort(ID::B, cell->getPort(ID::S)); + cell->unsetPort(ID::S); if (cell->type == ID($mux)) { - Const width = cell->parameters[ID(WIDTH)]; - cell->parameters[ID(A_WIDTH)] = width; - cell->parameters[ID(B_WIDTH)] = width; - cell->parameters[ID(Y_WIDTH)] = width; - cell->parameters[ID(A_SIGNED)] = 0; - cell->parameters[ID(B_SIGNED)] = 0; - cell->parameters.erase(ID(WIDTH)); + Const width = cell->parameters[ID::WIDTH]; + cell->parameters[ID::A_WIDTH] = width; + cell->parameters[ID::B_WIDTH] = width; + cell->parameters[ID::Y_WIDTH] = width; + cell->parameters[ID::A_SIGNED] = 0; + cell->parameters[ID::B_SIGNED] = 0; + cell->parameters.erase(ID::WIDTH); cell->type = ID($or); } else cell->type = ID($_OR_); @@ -1170,14 +1235,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec new_a, new_b, new_s; int width = GetSize(cell->getPort(ID::A)); if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) || - cell->getPort(ID(S)).is_fully_undef()) { + cell->getPort(ID::S).is_fully_undef()) { cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A)); goto next_cell; } - for (int i = 0; i < cell->getPort(ID(S)).size(); i++) { + for (int i = 0; i < cell->getPort(ID::S).size(); i++) { RTLIL::SigSpec old_b = cell->getPort(ID::B).extract(i*width, width); - RTLIL::SigSpec old_s = cell->getPort(ID(S)).extract(i, 1); + RTLIL::SigSpec old_s = cell->getPort(ID::S).extract(i, 1); if (old_b.is_fully_undef() || old_s.is_fully_undef()) continue; new_b.append(old_b); @@ -1199,48 +1264,48 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons replace_cell(assign_map, module, cell, "mux_sel01", ID::Y, new_s); goto next_cell; } - if (cell->getPort(ID(S)).size() != new_s.size()) { + if (cell->getPort(ID::S).size() != new_s.size()) { cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str()); log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n", - GetSize(cell->getPort(ID(S))) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module)); + GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module)); cell->setPort(ID::A, new_a); cell->setPort(ID::B, new_b); - cell->setPort(ID(S), new_s); + cell->setPort(ID::S, new_s); if (new_s.size() > 1) { cell->type = ID($pmux); - cell->parameters[ID(S_WIDTH)] = new_s.size(); + cell->parameters[ID::S_WIDTH] = new_s.size(); } else { cell->type = ID($mux); - cell->parameters.erase(ID(S_WIDTH)); + cell->parameters.erase(ID::S_WIDTH); } did_something = true; } } #define FOLD_1ARG_CELL(_t) \ - if (cell->type == "$" #_t) { \ + if (cell->type == ID($##_t)) { \ RTLIL::SigSpec a = cell->getPort(ID::A); \ assign_map.apply(a); \ if (a.is_fully_const()) { \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \ - cell->parameters[ID(A_SIGNED)].as_bool(), false, \ - cell->parameters[ID(Y_WIDTH)].as_int())); \ + cell->parameters[ID::A_SIGNED].as_bool(), false, \ + cell->parameters[ID::Y_WIDTH].as_int())); \ cover("opt.opt_expr.const.$" #_t); \ replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID::Y, y); \ goto next_cell; \ } \ } #define FOLD_2ARG_CELL(_t) \ - if (cell->type == "$" #_t) { \ + if (cell->type == ID($##_t)) { \ RTLIL::SigSpec a = cell->getPort(ID::A); \ RTLIL::SigSpec b = cell->getPort(ID::B); \ assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \ - cell->parameters[ID(A_SIGNED)].as_bool(), \ - cell->parameters[ID(B_SIGNED)].as_bool(), \ - cell->parameters[ID(Y_WIDTH)].as_int())); \ + cell->parameters[ID::A_SIGNED].as_bool(), \ + cell->parameters[ID::B_SIGNED].as_bool(), \ + cell->parameters[ID::Y_WIDTH].as_int())); \ cover("opt.opt_expr.const.$" #_t); \ replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \ goto next_cell; \ @@ -1289,7 +1354,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons // be very conservative with optimizing $mux cells as we do not want to break mux trees if (cell->type == ID($mux)) { - RTLIL::SigSpec input = assign_map(cell->getPort(ID(S))); + RTLIL::SigSpec input = assign_map(cell->getPort(ID::S)); RTLIL::SigSpec inA = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec inB = assign_map(cell->getPort(ID::B)); if (input.is_fully_const()) @@ -1300,8 +1365,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!keepdc && cell->type == ID($mul)) { - bool a_signed = cell->parameters[ID(A_SIGNED)].as_bool(); - bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool(); + bool a_signed = cell->parameters[ID::A_SIGNED].as_bool(); + bool b_signed = cell->parameters[ID::B_SIGNED].as_bool(); bool swapped_ab = false; RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); @@ -1342,8 +1407,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!swapped_ab) { cell->setPort(ID::A, cell->getPort(ID::B)); - cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH)); - cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED)); + cell->parameters.at(ID::A_WIDTH) = cell->parameters.at(ID::B_WIDTH); + cell->parameters.at(ID::A_SIGNED) = cell->parameters.at(ID::B_SIGNED); } std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6); @@ -1352,8 +1417,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons new_b.pop_back(); cell->type = ID($shl); - cell->parameters[ID(B_WIDTH)] = GetSize(new_b); - cell->parameters[ID(B_SIGNED)] = false; + cell->parameters[ID::B_WIDTH] = GetSize(new_b); + cell->parameters[ID::B_SIGNED] = false; cell->setPort(ID::B, new_b); cell->check(); @@ -1365,7 +1430,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!keepdc && cell->type.in(ID($div), ID($mod))) { - bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool(); + bool b_signed = cell->parameters[ID::B_SIGNED].as_bool(); SigSpec sig_b = assign_map(cell->getPort(ID::B)); SigSpec sig_y = assign_map(cell->getPort(ID::Y)); @@ -1403,8 +1468,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons new_b.pop_back(); cell->type = ID($shr); - cell->parameters[ID(B_WIDTH)] = GetSize(new_b); - cell->parameters[ID(B_SIGNED)] = false; + cell->parameters[ID::B_WIDTH] = GetSize(new_b); + cell->parameters[ID::B_SIGNED] = false; cell->setPort(ID::B, new_b); cell->check(); } @@ -1421,7 +1486,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons new_b.push_back(State::S0); cell->type = ID($and); - cell->parameters[ID(B_WIDTH)] = GetSize(new_b); + cell->parameters[ID::B_WIDTH] = GetSize(new_b); cell->setPort(ID::B, new_b); cell->check(); } @@ -1442,10 +1507,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons contradiction_cache.promote(State::S0); contradiction_cache.promote(State::S1); - int a_width = cell->getParam(ID(A_WIDTH)).as_int(); - int b_width = cell->getParam(ID(B_WIDTH)).as_int(); + int a_width = cell->getParam(ID::A_WIDTH).as_int(); + int b_width = cell->getParam(ID::B_WIDTH).as_int(); - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); int width = is_signed ? std::min(a_width, b_width) : std::max(a_width, b_width); SigSpec sig_a = cell->getPort(ID::A); @@ -1499,8 +1564,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->setPort(ID::A, sig_a); cell->setPort(ID::B, sig_b); - cell->setParam(ID(A_WIDTH), GetSize(sig_a)); - cell->setParam(ID(B_WIDTH), GetSize(sig_b)); + cell->setParam(ID::A_WIDTH, GetSize(sig_a)); + cell->setParam(ID::B_WIDTH, GetSize(sig_b)); did_something = true; goto next_cell; @@ -1513,9 +1578,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons IdString cmp_type = cell->type; SigSpec var_sig = cell->getPort(ID::A); SigSpec const_sig = cell->getPort(ID::B); - int var_width = cell->parameters[ID(A_WIDTH)].as_int(); - int const_width = cell->parameters[ID(B_WIDTH)].as_int(); - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); + int var_width = cell->parameters[ID::A_WIDTH].as_int(); + int const_width = cell->parameters[ID::B_WIDTH].as_int(); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); if (!const_sig.is_fully_const()) { @@ -1590,7 +1655,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } int const_bit_set = get_highest_hot_index(const_sig); - if(const_bit_set >= var_width) + if (const_bit_set >= var_width) { string cmp_name; if (cmp_type == ID($lt) || cmp_type == ID($le)) @@ -1737,13 +1802,14 @@ struct OptExprPass : public Pass { } extra_args(args, argidx, design); + CellTypes ct(design); for (auto module : design->selected_modules()) { log("Optimizing module %s.\n", log_id(module)); if (undriven) { did_something = false; - replace_undriven(design, module); + replace_undriven(module, ct); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index c4f278706..12927d052 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -41,8 +41,8 @@ struct OptLutWorker bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs) { SigSpec lut_input = sigmap(lut->getPort(ID::A)); - int lut_width = lut->getParam(ID(WIDTH)).as_int(); - Const lut_table = lut->getParam(ID(LUT)); + int lut_width = lut->getParam(ID::WIDTH).as_int(); + Const lut_table = lut->getParam(ID::LUT); int lut_index = 0; for (int i = 0; i < lut_width; i++) @@ -107,7 +107,7 @@ struct OptLutWorker if (lut_output.wire->get_bool_attribute(ID::keep)) continue; - int lut_width = cell->getParam(ID(WIDTH)).as_int(); + int lut_width = cell->getParam(ID::WIDTH).as_int(); SigSpec lut_input = cell->getPort(ID::A); int lut_arity = 0; @@ -305,7 +305,7 @@ struct OptLutWorker auto lutA = worklist.pop(); SigSpec lutA_input = sigmap(lutA->getPort(ID::A)); SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]); - int lutA_width = lutA->getParam(ID(WIDTH)).as_int(); + int lutA_width = lutA->getParam(ID::WIDTH).as_int(); int lutA_arity = luts_arity[lutA]; pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA]; @@ -323,7 +323,7 @@ struct OptLutWorker auto lutB = port.cell; SigSpec lutB_input = sigmap(lutB->getPort(ID::A)); SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]); - int lutB_width = lutB->getParam(ID(WIDTH)).as_int(); + int lutB_width = lutB->getParam(ID::WIDTH).as_int(); int lutB_arity = luts_arity[lutB]; pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB]; @@ -372,7 +372,7 @@ struct OptLutWorker log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n"); else if (lutB_dlogic_inputs.size() > 0) log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n"); - else if (lutB->get_bool_attribute(ID(lut_keep))) + else if (lutB->get_bool_attribute(ID::lut_keep)) log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n"); else combine_mask |= COMBINE_A; @@ -380,7 +380,7 @@ struct OptLutWorker log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n"); else if (lutA_dlogic_inputs.size() > 0) log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n"); - else if (lutA->get_bool_attribute(ID(lut_keep))) + else if (lutA->get_bool_attribute(ID::lut_keep)) log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n"); else combine_mask |= COMBINE_B; @@ -440,7 +440,7 @@ struct OptLutWorker lutR_unique.insert(bit); } - int lutM_width = lutM->getParam(ID(WIDTH)).as_int(); + int lutM_width = lutM->getParam(ID::WIDTH).as_int(); SigSpec lutM_input = sigmap(lutM->getPort(ID::A)); std::vector<SigBit> lutM_new_inputs; for (int i = 0; i < lutM_width; i++) @@ -482,11 +482,11 @@ struct OptLutWorker lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs); } - log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID(LUT)).as_string().c_str()); - log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID(LUT)).as_string().c_str()); + log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str()); + log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str()); log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str()); - lutM->setParam(ID(LUT), lutM_new_table); + lutM->setParam(ID::LUT, lutM_new_table); lutM->setPort(ID::A, lutM_new_inputs); lutM->setPort(ID::Y, lutB_output); diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index cf5248ced..1d32e84bb 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -80,7 +80,7 @@ struct OptLutInsPass : public Pass { continue; inputs = cell->getPort(ID::A).bits(); output = cell->getPort(ID::Y); - lut = cell->getParam(ID(LUT)); + lut = cell->getParam(ID::LUT); } else if (techname == "xilinx" || techname == "gowin") { if (cell->type == ID(LUT1)) { inputs = { @@ -125,20 +125,20 @@ struct OptLutInsPass : public Pass { // Not a LUT. continue; } - lut = cell->getParam(ID(INIT)); + lut = cell->getParam(ID::INIT); if (techname == "xilinx") - output = cell->getPort(ID(O)); + output = cell->getPort(ID::O); else - output = cell->getPort(ID(F)); + output = cell->getPort(ID::F); } else if (techname == "ecp5") { if (cell->type == ID(LUT4)) { inputs = { cell->getPort(ID::A), cell->getPort(ID::B), - cell->getPort(ID(C)), - cell->getPort(ID(D)), + cell->getPort(ID::C), + cell->getPort(ID::D), }; - lut = cell->getParam(ID(INIT)); + lut = cell->getParam(ID::INIT); output = cell->getPort(ID(Z)); ignore_const = true; } else { @@ -217,19 +217,19 @@ struct OptLutInsPass : public Pass { module->connect(output, new_lut[0]); } else { if (techname == "") { - cell->setParam(ID(LUT), new_lut); - cell->setParam(ID(WIDTH), GetSize(new_inputs)); + cell->setParam(ID::LUT, new_lut); + cell->setParam(ID::WIDTH, GetSize(new_inputs)); cell->setPort(ID::A, new_inputs); } else if (techname == "ecp5") { log_assert(GetSize(new_inputs) == 4); - cell->setParam(ID(INIT), new_lut); + cell->setParam(ID::INIT, new_lut); cell->setPort(ID::A, new_inputs[0]); cell->setPort(ID::B, new_inputs[1]); - cell->setPort(ID(C), new_inputs[2]); - cell->setPort(ID(D), new_inputs[3]); + cell->setPort(ID::C, new_inputs[2]); + cell->setPort(ID::D, new_inputs[3]); } else { // xilinx, gowin - cell->setParam(ID(INIT), new_lut); + cell->setParam(ID::INIT, new_lut); if (techname == "xilinx") log_assert(GetSize(new_inputs) <= 6); else diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index 98d3551eb..ff9c06453 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -45,17 +45,17 @@ struct OptMemWorker for (auto cell : module->cells()) { if (cell->type == ID($memrd)) { - IdString id = cell->getParam(ID(MEMID)).decode_string(); + IdString id = cell->getParam(ID::MEMID).decode_string(); memrd.at(id).push_back(cell->name); } if (cell->type == ID($memwr)) { - IdString id = cell->getParam(ID(MEMID)).decode_string(); + IdString id = cell->getParam(ID::MEMID).decode_string(); memwr.at(id).push_back(cell->name); } if (cell->type == ID($meminit)) { - IdString id = cell->getParam(ID(MEMID)).decode_string(); + IdString id = cell->getParam(ID::MEMID).decode_string(); meminit.at(id).push_back(cell->name); } } diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 8823a9061..a861bd7a4 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -26,7 +26,6 @@ #include <stdio.h> #include <set> -#define USE_CELL_HASH_CACHE USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -41,13 +40,11 @@ struct OptMergeWorker CellTypes ct; int total_count; -#ifdef USE_CELL_HASH_CACHE - dict<const RTLIL::Cell*, std::string> cell_hash_cache; -#endif + SHA1 checksum; static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn) { - SigSpec sig_s = conn.at(ID(S)); + SigSpec sig_s = conn.at(ID::S); SigSpec sig_b = conn.at(ID::B); int s_width = GetSize(sig_s); @@ -59,16 +56,15 @@ struct OptMergeWorker std::sort(sb_pairs.begin(), sb_pairs.end()); - conn[ID(S)] = SigSpec(); + conn[ID::S] = SigSpec(); conn[ID::B] = SigSpec(); for (auto &it : sb_pairs) { - conn[ID(S)].append(it.first); + conn[ID::S].append(it.first); conn[ID::B].append(it.second); } } -#ifdef USE_CELL_HASH_CACHE std::string int_to_hash_string(unsigned int v) { if (v == 0) @@ -83,14 +79,9 @@ struct OptMergeWorker std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell) { - if (cell_hash_cache.count(cell) > 0) - return cell_hash_cache[cell]; - + vector<string> hash_conn_strings; std::string hash_string = cell->type.str() + "\n"; - for (auto &it : cell->parameters) - hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n"; - const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections(); dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn; @@ -119,18 +110,27 @@ struct OptMergeWorker alt_conn = *conn; assign_map.apply(alt_conn.at(ID::A)); assign_map.apply(alt_conn.at(ID::B)); - assign_map.apply(alt_conn.at(ID(S))); + assign_map.apply(alt_conn.at(ID::S)); sort_pmux_conn(alt_conn); conn = &alt_conn; } - vector<string> hash_conn_strings; - for (auto &it : *conn) { - if (cell->output(it.first)) - continue; - RTLIL::SigSpec sig = it.second; - assign_map.apply(sig); + RTLIL::SigSpec sig; + if (cell->output(it.first)) { + if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || + cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") || + cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) { + // For the 'Q' output of state elements, + // use its (* init *) attribute value + for (const auto &b : dff_init_map(it.second)) + sig.append(b.wire ? State::Sx : b); + } + else + continue; + } + else + sig = assign_map(it.second); string s = "C " + it.first.str() + "="; for (auto &chunk : sig.chunks()) { if (chunk.wire) @@ -143,50 +143,59 @@ struct OptMergeWorker hash_conn_strings.push_back(s + "\n"); } + for (auto &it : cell->parameters) + hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n"); + std::sort(hash_conn_strings.begin(), hash_conn_strings.end()); for (auto it : hash_conn_strings) hash_string += it; - cell_hash_cache[cell] = sha1(hash_string); - return cell_hash_cache[cell]; + checksum.update(hash_string); + return checksum.final(); } -#endif - bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2, bool <) + bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) { -#ifdef USE_CELL_HASH_CACHE - std::string hash1 = hash_cell_parameters_and_connections(cell1); - std::string hash2 = hash_cell_parameters_and_connections(cell2); - - if (hash1 != hash2) { - lt = hash1 < hash2; - return true; - } -#endif - - if (cell1->parameters != cell2->parameters) { - std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end()); - std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end()); - lt = p1 < p2; - return true; - } - - dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections(); - dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections(); - - for (auto &it : conn1) { - if (cell1->output(it.first)) - it.second = RTLIL::SigSpec(); - else - assign_map.apply(it.second); - } - - for (auto &it : conn2) { - if (cell2->output(it.first)) - it.second = RTLIL::SigSpec(); - else - assign_map.apply(it.second); + log_assert(cell1 != cell2); + if (cell1->type != cell2->type) return false; + + if (cell1->parameters != cell2->parameters) + return false; + + if (cell1->connections_.size() != cell2->connections_.size()) + return false; + for (const auto &it : cell1->connections_) + if (!cell2->connections_.count(it.first)) + return false; + + decltype(Cell::connections_) conn1, conn2; + conn1.reserve(cell1->connections_.size()); + conn2.reserve(cell1->connections_.size()); + + for (const auto &it : cell1->connections_) { + if (cell1->output(it.first)) { + if (it.first == ID::Q && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || + cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") || + cell1->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) { + // For the 'Q' output of state elements, + // use the (* init *) attribute value + auto &sig1 = conn1[it.first]; + for (const auto &b : dff_init_map(it.second)) + sig1.append(b.wire ? State::Sx : b); + auto &sig2 = conn2[it.first]; + for (const auto &b : dff_init_map(cell2->getPort(it.first))) + sig2.append(b.wire ? State::Sx : b); + } + else { + conn1[it.first] = RTLIL::SigSpec(); + conn2[it.first] = RTLIL::SigSpec(); + } + } + else { + conn1[it.first] = assign_map(it.second); + conn2[it.first] = assign_map(cell2->getPort(it.first)); + } } if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) || @@ -215,54 +224,9 @@ struct OptMergeWorker sort_pmux_conn(conn2); } - if (conn1 != conn2) { - std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end()); - std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end()); - lt = c1 < c2; - return true; - } - - if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || - cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") || - cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) { - std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector(); - std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector(); - for (size_t i = 0; i < q1.size(); i++) - if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) { - lt = q1.at(i) < q2.at(i); - return true; - } - } - - return false; + return conn1 == conn2; } - bool compare_cells(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) - { - if (cell1->type != cell2->type) - return cell1->type < cell2->type; - - if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known()) - return cell1 < cell2; - - if (cell1->has_keep_attr() || cell2->has_keep_attr()) - return cell1 < cell2; - - bool lt; - if (compare_cell_parameters_and_connections(cell1, cell2, lt)) - return lt; - - return false; - } - - struct CompareCells { - OptMergeWorker *that; - CompareCells(OptMergeWorker *that) : that(that) {} - bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const { - return that->compare_cells(cell1, cell2); - } - }; - OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) : design(design), module(module), assign_map(module), mode_share_all(mode_share_all) { @@ -289,8 +253,8 @@ struct OptMergeWorker dff_init_map.set(module); for (auto &it : module->wires_) - if (it.second->attributes.count(ID(init)) != 0) { - Const initval = it.second->attributes.at(ID(init)); + if (it.second->attributes.count(ID::init) != 0) { + Const initval = it.second->attributes.at(ID::init); for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++) if (initval[i] == State::S0 || initval[i] == State::S1) dff_init_map.add(SigBit(it.second, i), initval[i]); @@ -299,9 +263,6 @@ struct OptMergeWorker bool did_something = true; while (did_something) { -#ifdef USE_CELL_HASH_CACHE - cell_hash_cache.clear(); -#endif std::vector<RTLIL::Cell*> cells; cells.reserve(module->cells_.size()); for (auto &it : module->cells_) { @@ -312,42 +273,51 @@ struct OptMergeWorker } did_something = false; - std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this)); + dict<std::string, RTLIL::Cell*> sharemap; for (auto cell : cells) { - if (sharemap.count(cell) > 0) { - did_something = true; - log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str()); - for (auto &it : cell->connections()) { - if (cell->output(it.first)) { - RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first); - log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(), - log_signal(it.second), log_signal(other_sig)); - module->connect(RTLIL::SigSig(it.second, other_sig)); - assign_map.add(it.second, other_sig); - - if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || - cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") || - cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) { - for (auto c : it.second.chunks()) { - auto jt = c.wire->attributes.find(ID(init)); - if (jt == c.wire->attributes.end()) - continue; - for (int i = c.offset; i < c.offset + c.width; i++) - jt->second[i] = State::Sx; + if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known()) + continue; + + auto hash = hash_cell_parameters_and_connections(cell); + auto r = sharemap.insert(std::make_pair(hash, cell)); + if (!r.second) { + if (compare_cell_parameters_and_connections(cell, r.first->second)) { + if (cell->has_keep_attr()) { + if (r.first->second->has_keep_attr()) + continue; + std::swap(r.first->second, cell); + } + + + did_something = true; + log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str()); + for (auto &it : cell->connections()) { + if (cell->output(it.first)) { + RTLIL::SigSpec other_sig = r.first->second->getPort(it.first); + log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(), + log_signal(it.second), log_signal(other_sig)); + module->connect(RTLIL::SigSig(it.second, other_sig)); + assign_map.add(it.second, other_sig); + + if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || + cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") || + cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) { + for (auto c : it.second.chunks()) { + auto jt = c.wire->attributes.find(ID::init); + if (jt == c.wire->attributes.end()) + continue; + for (int i = c.offset; i < c.offset + c.width; i++) + jt->second[i] = State::Sx; + } + dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second))); } - dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second))); } } + log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); + module->remove(cell); + total_count++; } - log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); -#ifdef USE_CELL_HASH_CACHE - cell_hash_cache.erase(cell); -#endif - module->remove(cell); - total_count++; - } else { - sharemap[cell] = cell; } } } diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 3c486bbcc..d076addae 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -88,7 +88,7 @@ struct OptMuxtreeWorker { RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID(S)); + RTLIL::SigSpec sig_s = cell->getPort(ID::S); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); muxinfo_t muxinfo; @@ -229,7 +229,7 @@ struct OptMuxtreeWorker RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A); RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B); - RTLIL::SigSpec sig_s = mi.cell->getPort(ID(S)); + RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S); RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y); RTLIL::SigSpec sig_ports = sig_b; @@ -257,12 +257,12 @@ struct OptMuxtreeWorker mi.cell->setPort(ID::A, new_sig_a); mi.cell->setPort(ID::B, new_sig_b); - mi.cell->setPort(ID(S), new_sig_s); + mi.cell->setPort(ID::S, new_sig_s); if (GetSize(new_sig_s) == 1) { mi.cell->type = ID($mux); - mi.cell->parameters.erase(ID(S_WIDTH)); + mi.cell->parameters.erase(ID::S_WIDTH); } else { - mi.cell->parameters[ID(S_WIDTH)] = RTLIL::Const(GetSize(new_sig_s)); + mi.cell->parameters[ID::S_WIDTH] = RTLIL::Const(GetSize(new_sig_s)); } } } @@ -366,7 +366,7 @@ struct OptMuxtreeWorker idict<int> ctrl_bits; if (portname == ID::B) width = GetSize(muxinfo.cell->getPort(ID::A)); - for (int bit : sig2bits(muxinfo.cell->getPort(ID(S)), false)) + for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false)) ctrl_bits(bit); int port_idx = 0, port_off = 0; diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index f74655d1c..f640f50a0 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -96,7 +96,7 @@ struct OptReduceWorker } cell->setPort(ID::A, new_sig_a); - cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size()); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size()); return; } @@ -104,7 +104,7 @@ struct OptReduceWorker { RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); - RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S))); + RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S)); RTLIL::SigSpec new_sig_b, new_sig_s; pool<RTLIL::SigSpec> handled_sig; @@ -127,9 +127,9 @@ struct OptReduceWorker { RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or)); reduce_or_cell->setPort(ID::A, this_s); - reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0); - reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size()); - reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1); + reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); + reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size()); + reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); this_s = RTLIL::SigSpec(reduce_or_wire); @@ -156,12 +156,12 @@ struct OptReduceWorker else { cell->setPort(ID::B, new_sig_b); - cell->setPort(ID(S), new_sig_s); + cell->setPort(ID::S, new_sig_s); if (new_sig_s.size() > 1) { - cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size()); + cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size()); } else { cell->type = ID($mux); - cell->parameters.erase(ID(S_WIDTH)); + cell->parameters.erase(ID::S_WIDTH); } } } @@ -192,13 +192,13 @@ struct OptReduceWorker if (all_tuple_bits_same) { - old_sig_conn.first.append_bit(sig_y.at(i)); - old_sig_conn.second.append_bit(sig_a.at(i)); + old_sig_conn.first.append(sig_y.at(i)); + old_sig_conn.second.append(sig_a.at(i)); } else if (consolidated_in_tuples_map.count(in_tuple)) { - old_sig_conn.first.append_bit(sig_y.at(i)); - old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple)); + old_sig_conn.first.append(sig_y.at(i)); + old_sig_conn.second.append(consolidated_in_tuples_map.at(in_tuple)); } else { @@ -222,14 +222,14 @@ struct OptReduceWorker } cell->setPort(ID::B, RTLIL::SigSpec()); - for (int i = 1; i <= cell->getPort(ID(S)).size(); i++) + for (int i = 1; i <= cell->getPort(ID::S).size(); i++) for (auto &in_tuple : consolidated_in_tuples) { RTLIL::SigSpec new_b = cell->getPort(ID::B); new_b.append(in_tuple.at(i)); cell->setPort(ID::B, new_b); } - cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size()); + cell->parameters[ID::WIDTH] = RTLIL::Const(new_sig_y.size()); cell->setPort(ID::Y, new_sig_y); log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), @@ -255,14 +255,14 @@ struct OptReduceWorker for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == ID($mem)) - mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN)))); + mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN))); if (cell->type == ID($memwr)) - mem_wren_sigs.add(assign_map(cell->getPort(ID(EN)))); + mem_wren_sigs.add(assign_map(cell->getPort(ID::EN))); } for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q))))) - mem_wren_sigs.add(assign_map(cell->getPort(ID(D)))); + if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q)))) + mem_wren_sigs.add(assign_map(cell->getPort(ID::D))); } bool keep_expanding_mem_wren_sigs = true; diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 0bf74098a..81326a417 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -41,7 +41,7 @@ void remove_init_attr(SigSpec sig) for (auto bit : assign_map(sig)) if (init_attributes.count(bit)) for (auto wbit : init_attributes.at(bit)) - wbit.wire->attributes.at(ID(init))[wbit.offset] = State::Sx; + wbit.wire->attributes.at(ID::init)[wbit.offset] = State::Sx; } bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) @@ -49,17 +49,17 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) SigSpec sig_set, sig_clr; State pol_set, pol_clr; - if (cell->hasPort(ID(S))) - sig_set = cell->getPort(ID(S)); + if (cell->hasPort(ID::S)) + sig_set = cell->getPort(ID::S); - if (cell->hasPort(ID(R))) - sig_clr = cell->getPort(ID(R)); + if (cell->hasPort(ID::R)) + sig_clr = cell->getPort(ID::R); - if (cell->hasPort(ID(SET))) - sig_set = cell->getPort(ID(SET)); + if (cell->hasPort(ID::SET)) + sig_set = cell->getPort(ID::SET); - if (cell->hasPort(ID(CLR))) - sig_clr = cell->getPort(ID(CLR)); + if (cell->hasPort(ID::CLR)) + sig_clr = cell->getPort(ID::CLR); log_assert(GetSize(sig_set) == GetSize(sig_clr)); @@ -72,16 +72,16 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; } else if (cell->type.in(ID($dffsr), ID($dlatchsr))) { - pol_set = cell->parameters[ID(SET_POLARITY)].as_bool() ? State::S1 : State::S0; - pol_clr = cell->parameters[ID(CLR_POLARITY)].as_bool() ? State::S1 : State::S0; + pol_set = cell->parameters[ID::SET_POLARITY].as_bool() ? State::S1 : State::S0; + pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool() ? State::S1 : State::S0; } else log_abort(); State npol_set = pol_set == State::S0 ? State::S1 : State::S0; State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0; - SigSpec sig_d = cell->getPort(ID(D)); - SigSpec sig_q = cell->getPort(ID(Q)); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); bool did_something = false; bool proper_sr = false; @@ -139,18 +139,18 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) if (cell->type.in(ID($dffsr), ID($dlatchsr))) { - cell->setParam(ID(WIDTH), GetSize(sig_d)); - cell->setPort(ID(SET), sig_set); - cell->setPort(ID(CLR), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setParam(ID::WIDTH, GetSize(sig_d)); + cell->setPort(ID::SET, sig_set); + cell->setPort(ID::CLR, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); } else { - cell->setPort(ID(S), sig_set); - cell->setPort(ID(R), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::S, sig_set); + cell->setPort(ID::R, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); } if (proper_sr) @@ -171,24 +171,24 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod)); cell->type = ID($adff); - cell->setParam(ID(ARST_POLARITY), unified_pol); - cell->setParam(ID(ARST_VALUE), reset_val); - cell->setPort(ID(ARST), sig_reset); - - cell->unsetParam(ID(SET_POLARITY)); - cell->unsetParam(ID(CLR_POLARITY)); - cell->unsetPort(ID(SET)); - cell->unsetPort(ID(CLR)); + cell->setParam(ID::ARST_POLARITY, unified_pol); + cell->setParam(ID::ARST_VALUE, reset_val); + cell->setPort(ID::ARST, sig_reset); + + cell->unsetParam(ID::SET_POLARITY); + cell->unsetParam(ID::CLR_POLARITY); + cell->unsetPort(ID::SET); + cell->unsetPort(ID::CLR); } else { log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod)); cell->type = ID($dff); - cell->unsetParam(ID(SET_POLARITY)); - cell->unsetParam(ID(CLR_POLARITY)); - cell->unsetPort(ID(SET)); - cell->unsetPort(ID(CLR)); + cell->unsetParam(ID::SET_POLARITY); + cell->unsetParam(ID::CLR_POLARITY); + cell->unsetPort(ID::SET); + cell->unsetPort(ID::CLR); } return true; @@ -208,8 +208,8 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod)); cell->type = new_type; - cell->unsetPort(ID(S)); - cell->unsetPort(ID(R)); + cell->unsetPort(ID::S); + cell->unsetPort(ID::R); return true; } @@ -223,17 +223,17 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) State on_state, off_state; if (dlatch->type == ID($dlatch)) { - sig_e = assign_map(dlatch->getPort(ID(EN))); - on_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S1 : State::S0; - off_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S0 : State::S1; + sig_e = assign_map(dlatch->getPort(ID::EN)); + on_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S1 : State::S0; + off_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S0 : State::S1; } else if (dlatch->type == ID($_DLATCH_P_)) { - sig_e = assign_map(dlatch->getPort(ID(E))); + sig_e = assign_map(dlatch->getPort(ID::E)); on_state = State::S1; off_state = State::S0; } else if (dlatch->type == ID($_DLATCH_N_)) { - sig_e = assign_map(dlatch->getPort(ID(E))); + sig_e = assign_map(dlatch->getPort(ID::E)); on_state = State::S0; off_state = State::S1; } else @@ -242,15 +242,15 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) if (sig_e == off_state) { RTLIL::Const val_init; - for (auto bit : dff_init_map(dlatch->getPort(ID(Q)))) + for (auto bit : dff_init_map(dlatch->getPort(ID::Q))) val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx); - mod->connect(dlatch->getPort(ID(Q)), val_init); + mod->connect(dlatch->getPort(ID::Q), val_init); goto delete_dlatch; } if (sig_e == on_state) { - mod->connect(dlatch->getPort(ID(Q)), dlatch->getPort(ID(D))); + mod->connect(dlatch->getPort(ID::Q), dlatch->getPort(ID::D)); goto delete_dlatch; } @@ -258,7 +258,7 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) delete_dlatch: log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod)); - remove_init_attr(dlatch->getPort(ID(Q))); + remove_init_attr(dlatch->getPort(ID::Q)); mod->remove(dlatch); return true; } @@ -269,23 +269,23 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) RTLIL::Const val_cp, val_rp, val_rv, val_ep; if (dff->type == ID($_FF_)) { - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); } else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) { - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); - sig_c = dff->getPort(ID(C)); + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); + sig_c = dff->getPort(ID::C); val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1); } else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 && (dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == '0' || dff->type[8] == '1')) { - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); - sig_c = dff->getPort(ID(C)); - sig_r = dff->getPort(ID(R)); + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); + sig_c = dff->getPort(ID::C); + sig_r = dff->getPort(ID::R); val_cp = RTLIL::Const(dff->type[6] == 'P', 1); val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); @@ -293,39 +293,39 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == 'N' || dff->type[8] == 'P')) { - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); - sig_c = dff->getPort(ID(C)); - sig_e = dff->getPort(ID(E)); + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); + sig_c = dff->getPort(ID::C); + sig_e = dff->getPort(ID::E); val_cp = RTLIL::Const(dff->type[7] == 'P', 1); val_ep = RTLIL::Const(dff->type[8] == 'P', 1); } else if (dff->type == ID($ff)) { - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); } else if (dff->type == ID($dff)) { - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); - sig_c = dff->getPort(ID(CLK)); - val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1); + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); + sig_c = dff->getPort(ID::CLK); + val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); } else if (dff->type == ID($dffe)) { - sig_e = dff->getPort(ID(EN)); - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); - sig_c = dff->getPort(ID(CLK)); - val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1); - val_ep = RTLIL::Const(dff->parameters[ID(EN_POLARITY)].as_bool(), 1); + sig_e = dff->getPort(ID::EN); + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); + sig_c = dff->getPort(ID::CLK); + val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); + val_ep = RTLIL::Const(dff->parameters[ID::EN_POLARITY].as_bool(), 1); } else if (dff->type == ID($adff)) { - sig_d = dff->getPort(ID(D)); - sig_q = dff->getPort(ID(Q)); - sig_c = dff->getPort(ID(CLK)); - sig_r = dff->getPort(ID(ARST)); - val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1); - val_rp = RTLIL::Const(dff->parameters[ID(ARST_POLARITY)].as_bool(), 1); - val_rv = dff->parameters[ID(ARST_VALUE)]; + sig_d = dff->getPort(ID::D); + sig_q = dff->getPort(ID::Q); + sig_c = dff->getPort(ID::CLK); + sig_r = dff->getPort(ID::ARST); + val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); + val_rp = RTLIL::Const(dff->parameters[ID::ARST_POLARITY].as_bool(), 1); + val_rv = dff->parameters[ID::ARST_VALUE]; } else log_abort(); @@ -422,15 +422,15 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) if (dff->type == ID($adff)) { dff->type = ID($dff); - dff->unsetPort(ID(ARST)); - dff->unsetParam(ID(ARST_POLARITY)); - dff->unsetParam(ID(ARST_VALUE)); + dff->unsetPort(ID::ARST); + dff->unsetParam(ID::ARST_POLARITY); + dff->unsetParam(ID::ARST_VALUE); return true; } log_assert(dff->type.begins_with("$_DFF_")); dff->type = stringf("$_DFF_%c_", + dff->type[6]); - dff->unsetPort(ID(R)); + dff->unsetPort(ID::R); } // If enable signal is present, and is fully constant @@ -447,14 +447,14 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) if (dff->type == ID($dffe)) { dff->type = ID($dff); - dff->unsetPort(ID(EN)); - dff->unsetParam(ID(EN_POLARITY)); + dff->unsetPort(ID::EN); + dff->unsetParam(ID::EN_POLARITY); return true; } log_assert(dff->type.begins_with("$_DFFE_")); dff->type = stringf("$_DFF_%c_", + dff->type[7]); - dff->unsetPort(ID(E)); + dff->unsetPort(ID::E); } if (sat && has_init && (!sig_r.size() || val_init == val_rv)) @@ -509,9 +509,9 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0, position, log_id(dff), log_id(dff->type), log_id(mod)); - SigSpec tmp = dff->getPort(ID(D)); + SigSpec tmp = dff->getPort(ID::D); tmp[position] = sigbit_init_val; - dff->setPort(ID(D), tmp); + dff->setPort(ID::D, tmp); removed_sigbits = true; } @@ -528,7 +528,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) delete_dff: log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); - remove_init_attr(dff->getPort(ID(Q))); + remove_init_attr(dff->getPort(ID::Q)); mod->remove(dff); for (auto &entry : bit2driver) @@ -588,8 +588,8 @@ struct OptRmdffPass : public Pass { for (auto wire : module->wires()) { - if (wire->attributes.count(ID(init)) != 0) { - Const initval = wire->attributes.at(ID(init)); + if (wire->attributes.count(ID::init) != 0) { + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) if (initval[i] == State::S0 || initval[i] == State::S1) dff_init_map.add(SigBit(wire, i), initval[i]); diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index f59f978a6..1f69c98f4 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -98,8 +98,8 @@ struct ExtSigSpec { bool cell_supported(RTLIL::Cell *cell) { if (cell->type.in(ID($alu))) { - RTLIL::SigSpec sig_bi = cell->getPort(ID(BI)); - RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); + RTLIL::SigSpec sig_bi = cell->getPort(ID::BI); + RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci) return true; @@ -139,7 +139,7 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) { if (cell->type == ID($alu) && port_name == ID::B) - return cell->getPort(ID(BI)); + return cell->getPort(ID::BI); else if (cell->type == ID($sub) && port_name == ID::B) return RTLIL::Const(1, 1); @@ -190,7 +190,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< auto shared_op = ports[0].op; if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; })) - max_width = std::max(max_width, shared_op->getParam(ID(Y_WIDTH)).as_int()); + max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int()); for (auto &operand : muxed_operands) @@ -210,7 +210,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< RTLIL::SigSpec mux_y = mux->getPort(ID::Y); RTLIL::SigSpec mux_a = mux->getPort(ID::A); RTLIL::SigSpec mux_b = mux->getPort(ID::B); - RTLIL::SigSpec mux_s = mux->getPort(ID(S)); + RTLIL::SigSpec mux_s = mux->getPort(ID::S); RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width); RTLIL::SigSpec shared_pmux_b; @@ -237,7 +237,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< mux->setPort(ID::A, mux_a); mux->setPort(ID::B, mux_b); mux->setPort(ID::Y, mux_y); - mux->setPort(ID(S), mux_s); + mux->setPort(ID::S, mux_s); for (const auto &op : muxed_operands) shared_pmux_b.append(op.sig); @@ -245,26 +245,26 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); if (shared_op->type.in(ID($alu))) { - RTLIL::SigSpec alu_x = shared_op->getPort(ID(X)); - RTLIL::SigSpec alu_co = shared_op->getPort(ID(CO)); + RTLIL::SigSpec alu_x = shared_op->getPort(ID::X); + RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO); - shared_op->setPort(ID(X), alu_x.extract(0, conn_width)); - shared_op->setPort(ID(CO), alu_co.extract(0, conn_width)); + shared_op->setPort(ID::X, alu_x.extract(0, conn_width)); + shared_op->setPort(ID::CO, alu_co.extract(0, conn_width)); } bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); if (!is_fine) - shared_op->setParam(ID(Y_WIDTH), conn_width); + shared_op->setParam(ID::Y_WIDTH, conn_width); if (decode_port(shared_op, ID::A, &assign_map) == operand) { shared_op->setPort(ID::B, mux_to_oper); if (!is_fine) - shared_op->setParam(ID(B_WIDTH), max_width); + shared_op->setParam(ID::B_WIDTH, max_width); } else { shared_op->setPort(ID::A, mux_to_oper); if (!is_fine) - shared_op->setParam(ID(A_WIDTH), max_width); + shared_op->setParam(ID::A_WIDTH, max_width); } } @@ -452,7 +452,7 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d for (auto cell : module->cells()) { if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) { - remove_connected_ops(cell->getPort(ID(S))); + remove_connected_ops(cell->getPort(ID::S)); find_op_mux_conns(cell); } else { for (auto &conn : cell->connections()) @@ -510,7 +510,7 @@ struct OptSharePass : public Pass { continue; if (cell->type == ID($alu)) { - for (RTLIL::IdString port_name : {ID(X), ID(CO)}) { + for (RTLIL::IdString port_name : {ID::X, ID::CO}) { auto mux_insig = assign_map(cell->getPort(port_name)); outsig_to_operator[mux_insig] = cell; for (auto outbit : mux_insig) @@ -552,7 +552,7 @@ struct OptSharePass : public Pass { if (p.mux->type.in(ID($mux), ID($_MUX_))) mux_port_num = 2; else - mux_port_num = p.mux->getPort(ID(S)).size(); + mux_port_num = p.mux->getPort(ID::S).size(); mux_port_conns.resize(mux_port_num); } diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 92b5794ac..11b80b6b3 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -46,7 +46,7 @@ struct OnehotDatabase for (auto wire : module->wires()) { - auto it = wire->attributes.find(ID(init)); + auto it = wire->attributes.find(ID::init); if (it == wire->attributes.end()) continue; @@ -65,10 +65,10 @@ struct OnehotDatabase if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff))) { - output = cell->getPort(ID(Q)); + output = cell->getPort(ID::Q); if (cell->type == ID($adff)) - inputs.push_back(cell->getParam(ID(ARST_VALUE))); - inputs.push_back(cell->getPort(ID(D))); + inputs.push_back(cell->getParam(ID::ARST_VALUE)); + inputs.push_back(cell->getPort(ID::D)); } if (cell->type.in(ID($mux), ID($pmux))) @@ -299,16 +299,16 @@ struct Pmux2ShiftxPass : public Pass { SigSpec A = sigmap(cell->getPort(ID::A)); SigSpec B = sigmap(cell->getPort(ID::B)); - int a_width = cell->getParam(ID(A_WIDTH)).as_int(); - int b_width = cell->getParam(ID(B_WIDTH)).as_int(); + int a_width = cell->getParam(ID::A_WIDTH).as_int(); + int b_width = cell->getParam(ID::B_WIDTH).as_int(); if (a_width < b_width) { - bool a_signed = cell->getParam(ID(A_SIGNED)).as_int(); + bool a_signed = cell->getParam(ID::A_SIGNED).as_int(); A.extend_u0(b_width, a_signed); } if (b_width < a_width) { - bool b_signed = cell->getParam(ID(B_SIGNED)).as_int(); + bool b_signed = cell->getParam(ID::B_SIGNED).as_int(); B.extend_u0(a_width, b_signed); } @@ -331,7 +331,7 @@ struct Pmux2ShiftxPass : public Pass { pair<SigSpec, Const> entry; for (auto it : bits) { - entry.first.append_bit(it.first); + entry.first.append(it.first); entry.second.bits.push_back(it.second); } @@ -352,7 +352,7 @@ struct Pmux2ShiftxPass : public Pass { pair<SigSpec, Const> entry; for (auto it : bits) { - entry.first.append_bit(it.first); + entry.first.append(it.first); entry.second.bits.push_back(it.second); } @@ -368,7 +368,7 @@ struct Pmux2ShiftxPass : public Pass { continue; string src = cell->get_src_attribute(); - int width = cell->getParam(ID(WIDTH)).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); int width_bits = ceil_log2(width); int extwidth = width; @@ -379,7 +379,7 @@ struct Pmux2ShiftxPass : public Pass { SigSpec A = cell->getPort(ID::A); SigSpec B = cell->getPort(ID::B); - SigSpec S = sigmap(cell->getPort(ID(S))); + SigSpec S = sigmap(cell->getPort(ID::S)); for (int i = 0; i < GetSize(S); i++) { if (!eqdb.count(S[i])) @@ -400,7 +400,7 @@ struct Pmux2ShiftxPass : public Pass { log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits); } - SigSpec updated_S = cell->getPort(ID(S)); + SigSpec updated_S = cell->getPort(ID::S); SigSpec updated_B = cell->getPort(ID::B); while (!seldb.empty()) @@ -727,9 +727,9 @@ struct Pmux2ShiftxPass : public Pass { } // update $pmux cell - cell->setPort(ID(S), updated_S); + cell->setPort(ID::S, updated_S); cell->setPort(ID::B, updated_B); - cell->setParam(ID(S_WIDTH), GetSize(updated_S)); + cell->setParam(ID::S_WIDTH, GetSize(updated_S)); } } } @@ -785,16 +785,16 @@ struct OnehotPass : public Pass { SigSpec A = sigmap(cell->getPort(ID::A)); SigSpec B = sigmap(cell->getPort(ID::B)); - int a_width = cell->getParam(ID(A_WIDTH)).as_int(); - int b_width = cell->getParam(ID(B_WIDTH)).as_int(); + int a_width = cell->getParam(ID::A_WIDTH).as_int(); + int b_width = cell->getParam(ID::B_WIDTH).as_int(); if (a_width < b_width) { - bool a_signed = cell->getParam(ID(A_SIGNED)).as_int(); + bool a_signed = cell->getParam(ID::A_SIGNED).as_int(); A.extend_u0(b_width, a_signed); } if (b_width < a_width) { - bool b_signed = cell->getParam(ID(B_SIGNED)).as_int(); + bool b_signed = cell->getParam(ID::B_SIGNED).as_int(); B.extend_u0(a_width, b_signed); } diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 92ce3fd11..2839507b0 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -41,7 +41,8 @@ struct ShareWorkerConfig struct ShareWorker { - ShareWorkerConfig config; + const ShareWorkerConfig config; + int limit; pool<RTLIL::IdString> generic_ops; RTLIL::Design *design; @@ -49,7 +50,6 @@ struct ShareWorker CellTypes fwd_ct, cone_ct; ModWalker modwalker; - ModIndex mi; pool<RTLIL::Cell*> cells_to_remove; pool<RTLIL::Cell*> recursion_state; @@ -90,7 +90,7 @@ struct ShareWorker for (auto &pbit : portbits) { if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) { - pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID(S))).to_sigbit_pool(); + pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool(); terminal_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); @@ -331,7 +331,7 @@ struct ShareWorker supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y))); supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y))); - supercell->setParam(ID(Y_WIDTH), width); + supercell->setParam(ID::Y_WIDTH, width); supercell->setPort(ID::Y, sig_y); supermacc.optimize(width); @@ -369,21 +369,21 @@ struct ShareWorker } if (cell->type == ID($memrd)) { - if (cell->parameters.at(ID(CLK_ENABLE)).as_bool()) + if (cell->parameters.at(ID::CLK_ENABLE).as_bool()) continue; - if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID(ADDR))).is_fully_const()) + if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const()) shareable_cells.insert(cell); continue; } if (cell->type.in(ID($mul), ID($div), ID($mod))) { - if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 4) + if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4) shareable_cells.insert(cell); continue; } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { - if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 8) + if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 8) shareable_cells.insert(cell); continue; } @@ -403,7 +403,7 @@ struct ShareWorker if (c1->type == ID($memrd)) { - if (c1->parameters.at(ID(MEMID)).decode_string() != c2->parameters.at(ID(MEMID)).decode_string()) + if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string()) return false; return true; @@ -413,11 +413,11 @@ struct ShareWorker { if (!config.opt_aggressive) { - int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int(); - int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int(); + int a1_width = c1->parameters.at(ID::A_WIDTH).as_int(); + int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int(); - int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int(); - int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int(); + int a2_width = c2->parameters.at(ID::A_WIDTH).as_int(); + int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int(); if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false; if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false; @@ -430,13 +430,13 @@ struct ShareWorker { if (!config.opt_aggressive) { - int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int(); - int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int(); - int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int(); + int a1_width = c1->parameters.at(ID::A_WIDTH).as_int(); + int b1_width = c1->parameters.at(ID::B_WIDTH).as_int(); + int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int(); - int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int(); - int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int(); - int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int(); + int a2_width = c2->parameters.at(ID::A_WIDTH).as_int(); + int b2_width = c2->parameters.at(ID::B_WIDTH).as_int(); + int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int(); if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false; if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false; @@ -450,13 +450,13 @@ struct ShareWorker { if (!config.opt_aggressive) { - int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int(); - int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int(); - int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int(); + int a1_width = c1->parameters.at(ID::A_WIDTH).as_int(); + int b1_width = c1->parameters.at(ID::B_WIDTH).as_int(); + int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int(); - int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int(); - int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int(); - int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int(); + int a2_width = c2->parameters.at(ID::A_WIDTH).as_int(); + int b2_width = c2->parameters.at(ID::B_WIDTH).as_int(); + int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int(); int min1_width = min(a1_width, b1_width); int max1_width = max(a1_width, b1_width); @@ -510,21 +510,21 @@ struct ShareWorker if (config.generic_uni_ops.count(c1->type)) { - if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool()) + if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool()) { - RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1; + RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1; if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { - unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1; + unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1; RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); - new_a.append_bit(RTLIL::State::S0); + new_a.append(RTLIL::State::S0); unsigned_cell->setPort(ID::A, new_a); } - unsigned_cell->parameters.at(ID(A_SIGNED)) = true; + unsigned_cell->parameters.at(ID::A_SIGNED) = true; unsigned_cell->check(); } - bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool(); - log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool()); + bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool(); + log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool()); RTLIL::SigSpec a1 = c1->getPort(ID::A); RTLIL::SigSpec y1 = c1->getPort(ID::Y); @@ -544,9 +544,9 @@ struct ShareWorker RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); - supercell->parameters[ID(A_SIGNED)] = a_signed; - supercell->parameters[ID(A_WIDTH)] = a_width; - supercell->parameters[ID(Y_WIDTH)] = y_width; + supercell->parameters[ID::A_SIGNED] = a_signed; + supercell->parameters[ID::A_WIDTH] = a_width; + supercell->parameters[ID::Y_WIDTH] = y_width; supercell->setPort(ID::A, a); supercell->setPort(ID::Y, y); @@ -563,11 +563,11 @@ struct ShareWorker if (config.generic_cbin_ops.count(c1->type)) { - int score_unflipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()) + - max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()); + int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) + + max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int()); - int score_flipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()) + - max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()); + int score_flipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int()) + + max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()); if (score_flipped < score_unflipped) { @@ -575,36 +575,36 @@ struct ShareWorker c2->setPort(ID::A, c2->getPort(ID::B)); c2->setPort(ID::B, tmp); - std::swap(c2->parameters.at(ID(A_WIDTH)), c2->parameters.at(ID(B_WIDTH))); - std::swap(c2->parameters.at(ID(A_SIGNED)), c2->parameters.at(ID(B_SIGNED))); + std::swap(c2->parameters.at(ID::A_WIDTH), c2->parameters.at(ID::B_WIDTH)); + std::swap(c2->parameters.at(ID::A_SIGNED), c2->parameters.at(ID::B_SIGNED)); modified_src_cells = true; } } - if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool()) + if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool()) { - RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1; + RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1; if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { - unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1; + unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1; RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); - new_a.append_bit(RTLIL::State::S0); + new_a.append(RTLIL::State::S0); unsigned_cell->setPort(ID::A, new_a); } - unsigned_cell->parameters.at(ID(A_SIGNED)) = true; + unsigned_cell->parameters.at(ID::A_SIGNED) = true; modified_src_cells = true; } - if (c1->parameters.at(ID(B_SIGNED)).as_bool() != c2->parameters.at(ID(B_SIGNED)).as_bool()) + if (c1->parameters.at(ID::B_SIGNED).as_bool() != c2->parameters.at(ID::B_SIGNED).as_bool()) { - RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(B_SIGNED)).as_bool() ? c2 : c1; + RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::B_SIGNED).as_bool() ? c2 : c1; if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) { - unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1; + unsigned_cell->parameters.at(ID::B_WIDTH) = unsigned_cell->parameters.at(ID::B_WIDTH).as_int() + 1; RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B); - new_b.append_bit(RTLIL::State::S0); + new_b.append(RTLIL::State::S0); unsigned_cell->setPort(ID::B, new_b); } - unsigned_cell->parameters.at(ID(B_SIGNED)) = true; + unsigned_cell->parameters.at(ID::B_SIGNED) = true; modified_src_cells = true; } @@ -613,11 +613,11 @@ struct ShareWorker c2->check(); } - bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool(); - bool b_signed = c1->parameters.at(ID(B_SIGNED)).as_bool(); + bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool(); + bool b_signed = c1->parameters.at(ID::B_SIGNED).as_bool(); - log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool()); - log_assert(b_signed == c2->parameters.at(ID(B_SIGNED)).as_bool()); + log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool()); + log_assert(b_signed == c2->parameters.at(ID::B_SIGNED).as_bool()); if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr)) b_signed = false; @@ -664,32 +664,32 @@ struct ShareWorker RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr; RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); - supercell->parameters[ID(A_SIGNED)] = a_signed; - supercell->parameters[ID(B_SIGNED)] = b_signed; - supercell->parameters[ID(A_WIDTH)] = a_width; - supercell->parameters[ID(B_WIDTH)] = b_width; - supercell->parameters[ID(Y_WIDTH)] = y_width; + supercell->parameters[ID::A_SIGNED] = a_signed; + supercell->parameters[ID::B_SIGNED] = b_signed; + supercell->parameters[ID::A_WIDTH] = a_width; + supercell->parameters[ID::B_WIDTH] = b_width; + supercell->parameters[ID::Y_WIDTH] = y_width; supercell->setPort(ID::A, a); supercell->setPort(ID::B, b); supercell->setPort(ID::Y, y); if (c1->type == ID($alu)) { RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(CI)), c1->getPort(ID(CI)), act, ci)); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(BI)), c1->getPort(ID(BI)), act, bi)); - supercell->setPort(ID(CI), ci); - supercell->setPort(ID(BI), bi); - supercell->setPort(ID(CO), co); - supercell->setPort(ID(X), x); + supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci)); + supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi)); + supercell->setPort(ID::CI, ci); + supercell->setPort(ID::BI, bi); + supercell->setPort(ID::CO, co); + supercell->setPort(ID::X, x); } supercell->check(); supercell_aux.insert(module->addPos(NEW_ID, y, y1)); supercell_aux.insert(module->addPos(NEW_ID, y, y2)); if (c1->type == ID($alu)) { - supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID(CO)))); - supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID(CO)))); - supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID(X)))); - supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID(X)))); + supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO))); + supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO))); + supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X))); + supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X))); } supercell_aux.insert(supercell); @@ -708,15 +708,15 @@ struct ShareWorker if (c1->type == ID($memrd)) { RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); - RTLIL::SigSpec addr1 = c1->getPort(ID(ADDR)); - RTLIL::SigSpec addr2 = c2->getPort(ID(ADDR)); + RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR); + RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR); if (GetSize(addr1) < GetSize(addr2)) addr1.extend_u0(GetSize(addr2)); else addr2.extend_u0(GetSize(addr1)); - supercell->setPort(ID(ADDR), addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); - supercell->parameters[ID(ABITS)] = RTLIL::Const(GetSize(addr1)); - supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID(DATA)), c2->getPort(ID(DATA)))); + supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); + supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1)); + supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA))); supercell_aux.insert(supercell); return supercell; } @@ -747,8 +747,8 @@ struct ShareWorker modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]); for (auto &bit : pbits) { - if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID(S)) - forbidden_controls_cache[cell].insert(bit.cell->getPort(ID(S)).extract(bit.offset, 1)); + if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S) + forbidden_controls_cache[cell].insert(bit.cell->getPort(ID::S).extract(bit.offset, 1)); consumer_cells.insert(bit.cell); } @@ -790,7 +790,7 @@ struct ShareWorker p.second.bits.clear(); for (auto &it : p_bits) { - p.first.append_bit(it.first); + p.first.append(it.first); p.second.bits.push_back(it.second); } @@ -890,10 +890,10 @@ struct ShareWorker bool used_in_a = false; std::set<int> used_in_b_parts; - int width = c->parameters.at(ID(WIDTH)).as_int(); + int width = c->parameters.at(ID::WIDTH).as_int(); std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID::A)); std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID::B)); - std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID(S))); + std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID::S)); for (auto &bit : sig_a) if (cell_out_bits.count(bit)) @@ -906,14 +906,14 @@ struct ShareWorker if (used_in_a) for (auto p : c_patterns) { for (int i = 0; i < GetSize(sig_s); i++) - p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); + p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } for (int idx : used_in_b_parts) for (auto p : c_patterns) { - p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); + p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } @@ -948,7 +948,7 @@ struct ShareWorker RTLIL::SigSpec signal; for (auto &bit : all_bits) - signal.append_bit(bit); + signal.append(bit); return signal; } @@ -963,7 +963,7 @@ struct ShareWorker for (int i = 0; i < GetSize(p_first); i++) if (filter_bits.count(p_first[i]) == 0) { - new_p.first.append_bit(p_first[i]); + new_p.first.append(p_first[i]); new_p.second.bits.push_back(p.second.bits.at(i)); } @@ -1071,6 +1071,8 @@ struct ShareWorker ct.setup_internals(); ct.setup_stdcells(); + ModIndex mi(module); + pool<RTLIL::Cell*> queue, covered; queue.insert(cell); @@ -1117,13 +1119,9 @@ struct ShareWorker module->remove(cell); } - ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : - config(config), design(design), module(module), mi(module) + ShareWorker(ShareWorkerConfig config, RTLIL::Design* design) : + config(config), design(design), modwalker(design) { - #ifndef NDEBUG - bool before_scc = module_has_scc(); - #endif - generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end()); @@ -1140,8 +1138,27 @@ struct ShareWorker cone_ct.cell_types.erase(ID($shr)); cone_ct.cell_types.erase(ID($sshl)); cone_ct.cell_types.erase(ID($sshr)); + } - modwalker.setup(design, module); + void operator()(RTLIL::Module *module) { + this->module = module; + + #ifndef NDEBUG + bool before_scc = module_has_scc(); + #endif + + limit = config.limit; + modwalker.setup(module); + + cells_to_remove.clear(); + recursion_state.clear(); + topo_cell_drivers.clear(); + topo_bit_drivers.clear(); + exclusive_ctrls.clear(); + terminal_bits.clear(); + shareable_cells.clear(); + forbidden_controls_cache.clear(); + activation_patterns_cache.clear(); find_terminal_bits(); find_shareable_cells(); @@ -1154,8 +1171,8 @@ struct ShareWorker for (auto cell : module->cells()) if (cell->type == ID($pmux)) - for (auto bit : cell->getPort(ID(S))) - for (auto other_bit : cell->getPort(ID(S))) + for (auto bit : cell->getPort(ID::S)) + for (auto other_bit : cell->getPort(ID::S)) if (bit < other_bit) exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit)); @@ -1399,8 +1416,8 @@ struct ShareWorker topo_cell_drivers[cell] = { supercell }; topo_cell_drivers[other_cell] = { supercell }; - if (config.limit > 0) - config.limit--; + if (limit > 0) + limit--; break; } @@ -1528,9 +1545,10 @@ struct SharePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - ShareWorker(config, design, mod_it.second); + ShareWorker sw(config, design); + + for (auto module : design->selected_modules()) + sw(module); } } SharePass; diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 04b882db9..195400bf0 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -65,7 +65,7 @@ struct WreduceWorker SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)); SigSpec sig_b = mi.sigmap(cell->getPort(ID::B)); - SigSpec sig_s = mi.sigmap(cell->getPort(ID(S))); + SigSpec sig_s = mi.sigmap(cell->getPort(ID::S)); SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y)); std::vector<SigBit> bits_removed; @@ -98,7 +98,7 @@ struct WreduceWorker SigSpec sig_removed; for (int i = GetSize(bits_removed)-1; i >= 0; i--) - sig_removed.append_bit(bits_removed[i]); + sig_removed.append(bits_removed[i]); if (GetSize(bits_removed) == GetSize(sig_y)) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); @@ -141,8 +141,8 @@ struct WreduceWorker { // Reduce size of FF if inputs are just sign/zero extended or output bit is not used - SigSpec sig_d = mi.sigmap(cell->getPort(ID(D))); - SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q))); + SigSpec sig_d = mi.sigmap(cell->getPort(ID::D)); + SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q)); bool is_adff = (cell->type == ID($adff)); Const initval, arst_value; @@ -151,8 +151,8 @@ struct WreduceWorker if (width_before == 0) return; - if (cell->parameters.count(ID(ARST_VALUE))) { - arst_value = cell->parameters[ID(ARST_VALUE)]; + if (cell->parameters.count(ID::ARST_VALUE)) { + arst_value = cell->parameters[ID::ARST_VALUE]; } bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0; @@ -220,13 +220,13 @@ struct WreduceWorker work_queue_bits.insert(bit); // Narrow ARST_VALUE parameter to new size. - if (cell->parameters.count(ID(ARST_VALUE))) { + if (cell->parameters.count(ID::ARST_VALUE)) { arst_value.bits.resize(GetSize(sig_q)); - cell->setParam(ID(ARST_VALUE), arst_value); + cell->setParam(ID::ARST_VALUE, arst_value); } - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->fixup_parameters(); } @@ -306,8 +306,8 @@ struct WreduceWorker GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { log("Converting cell %s.%s (%s) from signed to unsigned.\n", log_id(module), log_id(cell), log_id(cell->type)); - cell->setParam(ID(A_SIGNED), 0); - cell->setParam(ID(B_SIGNED), 0); + cell->setParam(ID::A_SIGNED, 0); + cell->setParam(ID::B_SIGNED, 0); port_a_signed = false; port_b_signed = false; did_something = true; @@ -319,7 +319,7 @@ struct WreduceWorker if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { log("Converting cell %s.%s (%s) from signed to unsigned.\n", log_id(module), log_id(cell), log_id(cell->type)); - cell->setParam(ID(A_SIGNED), 0); + cell->setParam(ID::A_SIGNED, 0); port_a_signed = false; did_something = true; } @@ -349,7 +349,7 @@ struct WreduceWorker if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub))) { - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool() || cell->type == ID($sub); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub); int a_size = 0, b_size = 0; if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A)); @@ -392,8 +392,8 @@ struct WreduceWorker static int count_nontrivial_wire_attrs(RTLIL::Wire *w) { int count = w->attributes.size(); - count -= w->attributes.count(ID(src)); - count -= w->attributes.count(ID(unused_bits)); + count -= w->attributes.count(ID::src); + count -= w->attributes.count(ID::unused_bits); return count; } @@ -406,8 +406,8 @@ struct WreduceWorker if (w->get_bool_attribute(ID::keep)) for (auto bit : mi.sigmap(w)) keep_bits.insert(bit); - if (w->attributes.count(ID(init))) { - Const initval = w->attributes.at(ID(init)); + if (w->attributes.count(ID::init)) { + Const initval = w->attributes.at(ID::init); SigSpec initsig = init_attr_sigmap(w); int width = std::min(GetSize(initval), GetSize(initsig)); for (int i = 0; i < width; i++) @@ -464,8 +464,8 @@ struct WreduceWorker if (!remove_init_bits.empty()) { for (auto w : module->wires()) { - if (w->attributes.count(ID(init))) { - Const initval = w->attributes.at(ID(init)); + if (w->attributes.count(ID::init)) { + Const initval = w->attributes.at(ID::init); Const new_initval(State::Sx, GetSize(w)); SigSpec initsig = init_attr_sigmap(w); int width = std::min(GetSize(initval), GetSize(initsig)); @@ -473,7 +473,7 @@ struct WreduceWorker if (!remove_init_bits.count(initsig[i])) new_initval[i] = initval[i]; } - w->attributes.at(ID(init)) = new_initval; + w->attributes.at(ID::init) = new_initval; } } } @@ -539,7 +539,7 @@ struct WreducePass : public Pass { SigSpec sig = c->getPort(ID::Y); if (!sig.has_const()) { c->setPort(ID::Y, sig[0]); - c->setParam(ID(Y_WIDTH), 1); + c->setParam(ID::Y_WIDTH, 1); sig.remove(0); module->connect(sig, Const(0, GetSize(sig))); } @@ -549,7 +549,7 @@ struct WreducePass : public Pass { { SigSpec A = c->getPort(ID::A); int original_a_width = GetSize(A); - if (c->getParam(ID(A_SIGNED)).as_bool()) { + if (c->getParam(ID::A_SIGNED).as_bool()) { while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0) A.remove(GetSize(A)-1, 1); } else { @@ -560,12 +560,12 @@ struct WreducePass : public Pass { log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n", original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type)); c->setPort(ID::A, A); - c->setParam(ID(A_WIDTH), GetSize(A)); + c->setParam(ID::A_WIDTH, GetSize(A)); } SigSpec B = c->getPort(ID::B); int original_b_width = GetSize(B); - if (c->getParam(ID(B_SIGNED)).as_bool()) { + if (c->getParam(ID::B_SIGNED).as_bool()) { while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0) B.remove(GetSize(B)-1, 1); } else { @@ -576,23 +576,23 @@ struct WreducePass : public Pass { log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n", original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type)); c->setPort(ID::B, B); - c->setParam(ID(B_WIDTH), GetSize(B)); + c->setParam(ID::B_WIDTH, GetSize(B)); } } if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) { - IdString memid = c->getParam(ID(MEMID)).decode_string(); + IdString memid = c->getParam(ID::MEMID).decode_string(); RTLIL::Memory *mem = module->memories.at(memid); if (mem->start_offset >= 0) { - int cur_addrbits = c->getParam(ID(ABITS)).as_int(); + int cur_addrbits = c->getParam(ID::ABITS).as_int(); int max_addrbits = ceil_log2(mem->start_offset + mem->size); if (cur_addrbits > max_addrbits) { log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n", cur_addrbits-max_addrbits, cur_addrbits, c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init", log_id(module), log_id(c), log_id(memid)); - c->setParam(ID(ABITS), max_addrbits); - c->setPort(ID(ADDR), c->getPort(ID(ADDR)).extract(0, max_addrbits)); + c->setParam(ID::ABITS, max_addrbits); + c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits)); } } } diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index c364cd91a..bfddfd0eb 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -73,11 +73,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Input Interface SigSpec A = st.sigA; - A.extend_u0(16, st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool()); + A.extend_u0(16, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool()); log_assert(GetSize(A) == 16); SigSpec B = st.sigB; - B.extend_u0(16, st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool()); + B.extend_u0(16, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool()); log_assert(GetSize(B) == 16); SigSpec CD = st.sigCD; @@ -88,8 +88,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setPort(ID::A, A); cell->setPort(ID::B, B); - cell->setPort(ID(C), CD.extract(16, 16)); - cell->setPort(ID(D), CD.extract(0, 16)); + cell->setPort(ID::C, CD.extract(16, 16)); + cell->setPort(ID::D, CD.extract(0, 16)); cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0); cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0); @@ -98,15 +98,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec AHOLD, BHOLD, CDHOLD; if (st.ffAholdmux) - AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID(S))); + AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID::S)); else AHOLD = State::S0; if (st.ffBholdmux) - BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID(S))); + BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID::S)); else BHOLD = State::S0; if (st.ffCDholdmux) - CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID(S))); + CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID::S)); else CDHOLD = State::S0; cell->setPort(ID(AHOLD), AHOLD); @@ -116,11 +116,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec IRSTTOP, IRSTBOT; if (st.ffArstmux) - IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID(S))); + IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID::S)); else IRSTTOP = State::S0; if (st.ffBrstmux) - IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID(S))); + IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID::S)); else IRSTBOT = State::S0; cell->setPort(ID(IRSTTOP), IRSTTOP); @@ -128,7 +128,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID(CLK), st.clock); + cell->setPort(ID::CLK, st.clock); cell->setPort(ID(CE), State::S1); cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1); @@ -156,7 +156,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) } else { - cell->setPort(ID(CLK), State::S0); + cell->setPort(ID::CLK, State::S0); cell->setPort(ID(CE), State::S0); cell->setParam(ID(NEG_TRIGGER), State::S0); } @@ -166,7 +166,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setPort(ID(SIGNEXTIN), State::Sx); cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID)); - cell->setPort(ID(CI), State::Sx); + cell->setPort(ID::CI, State::Sx); cell->setPort(ID(ACCUMCI), State::Sx); cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID)); @@ -178,19 +178,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm) if (O_width == 33) { log_assert(st.add); // If we have a signed multiply-add, then perform sign extension - if (st.add->getParam(ID(A_SIGNED)).as_bool() && st.add->getParam(ID(B_SIGNED)).as_bool()) + if (st.add->getParam(ID::A_SIGNED).as_bool() && st.add->getParam(ID::B_SIGNED).as_bool()) pm.module->connect(O[32], O[31]); else - cell->setPort(ID(CO), O[32]); + cell->setPort(ID::CO, O[32]); O.remove(O_width-1); } else - cell->setPort(ID(CO), pm.module->addWire(NEW_ID)); + cell->setPort(ID::CO, pm.module->addWire(NEW_ID)); log_assert(GetSize(O) <= 32); if (GetSize(O) < 32) O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); - cell->setPort(ID(O), O); + cell->setPort(ID::O, O); bool accum = false; if (st.add) { @@ -208,7 +208,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec OHOLD; if (st.ffOholdmux) - OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID(S))); + OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID::S)); else OHOLD = State::S0; cell->setPort(ID(OHOLDTOP), OHOLD); @@ -216,7 +216,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec ORST; if (st.ffOrstmux) - ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID(S))); + ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID::S)); else ORST = State::S0; cell->setPort(ID(ORSTTOP), ORST); @@ -225,9 +225,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec acc_reset = State::S0; if (st.mux) { if (st.muxAB == ID::A) - acc_reset = st.mux->getPort(ID(S)); + acc_reset = st.mux->getPort(ID::S); else - acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID(S))); + acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S)); } cell->setPort(ID(OLOADTOP), acc_reset); cell->setPort(ID(OLOADBOT), acc_reset); @@ -248,8 +248,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2)); cell->setParam(ID(MODE_8x8), State::S0); - cell->setParam(ID(A_SIGNED), st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool()); - cell->setParam(ID(B_SIGNED), st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool()); + cell->setParam(ID::A_SIGNED, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool()); + cell->setParam(ID::B_SIGNED, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool()); if (st.ffO) { if (st.o_lo) @@ -257,7 +257,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) else cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2)); - st.ffO->connections_.at(ID(Q)).replace(O, pm.module->addWire(NEW_ID, GetSize(O))); + st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O))); cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2)); } else { diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index 0053c8872..97d2008c2 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -37,26 +37,26 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n"); - Cell *cell = pm.module->addCell(NEW_ID, "$__ICE40_CARRY_WRAPPER"); + Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER)); pm.module->swap_names(cell, st.carry); - cell->setPort("\\A", st.carry->getPort("\\I0")); - cell->setPort("\\B", st.carry->getPort("\\I1")); - auto CI = st.carry->getPort("\\CI"); - cell->setPort("\\CI", CI); - cell->setPort("\\CO", st.carry->getPort("\\CO")); + cell->setPort(ID::A, st.carry->getPort(ID(I0))); + cell->setPort(ID::B, st.carry->getPort(ID(I1))); + auto CI = st.carry->getPort(ID::CI); + cell->setPort(ID::CI, CI); + cell->setPort(ID::CO, st.carry->getPort(ID::CO)); - cell->setPort("\\I0", st.lut->getPort("\\I0")); - auto I3 = st.lut->getPort("\\I3"); + cell->setPort(ID(I0), st.lut->getPort(ID(I0))); + auto I3 = st.lut->getPort(ID(I3)); if (pm.sigmap(CI) == pm.sigmap(I3)) { - cell->setParam("\\I3_IS_CI", State::S1); + cell->setParam(ID(I3_IS_CI), State::S1); I3 = State::Sx; } else - cell->setParam("\\I3_IS_CI", State::S0); - cell->setPort("\\I3", I3); - cell->setPort("\\O", st.lut->getPort("\\O")); - cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT")); + cell->setParam(ID(I3_IS_CI), State::S0); + cell->setPort(ID(I3), I3); + cell->setPort(ID::O, st.lut->getPort(ID::O)); + cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT))); for (const auto &a : st.carry->attributes) cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second; @@ -117,18 +117,18 @@ struct Ice40WrapCarryPass : public Pass { continue; auto carry = module->addCell(NEW_ID, ID(SB_CARRY)); - carry->setPort(ID(I0), cell->getPort(ID(A))); - carry->setPort(ID(I1), cell->getPort(ID(B))); - carry->setPort(ID(CI), cell->getPort(ID(CI))); - carry->setPort(ID(CO), cell->getPort(ID(CO))); + carry->setPort(ID(I0), cell->getPort(ID::A)); + carry->setPort(ID(I1), cell->getPort(ID::B)); + carry->setPort(ID::CI, cell->getPort(ID::CI)); + carry->setPort(ID::CO, cell->getPort(ID::CO)); module->swap_names(carry, cell); auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string(); auto lut = module->addCell(lut_name, ID($lut)); - lut->setParam(ID(WIDTH), 4); - lut->setParam(ID(LUT), cell->getParam(ID(LUT))); - auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); - lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) }); - lut->setPort(ID(Y), cell->getPort(ID(O))); + lut->setParam(ID::WIDTH, 4); + lut->setParam(ID::LUT, cell->getParam(ID::LUT)); + auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)); + lut->setPort(ID::A, { I3, cell->getPort(ID::B), cell->getPort(ID::A), cell->getPort(ID(I0)) }); + lut->setPort(ID::Y, cell->getPort(ID::O)); Const src; for (const auto &a : cell->attributes) @@ -136,16 +136,16 @@ struct Ice40WrapCarryPass : public Pass { carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second; else if (a.first.begins_with("\\SB_LUT4.\\")) lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second; - else if (a.first == ID(src)) + else if (a.first == ID::src) src = a.second; - else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived))) + else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived)) continue; else log_abort(); if (!src.empty()) { - carry->attributes.insert(std::make_pair(ID(src), src)); - lut->attributes.insert(std::make_pair(ID(src), src)); + carry->attributes.insert(std::make_pair(ID::src, src)); + lut->attributes.insert(std::make_pair(ID::src, src)); } module->remove(cell); diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 2230145df..4379ce1e6 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -87,7 +87,7 @@ struct PeepoptPass : public Pass { peepopt_pm pm(module); for (auto w : module->wires()) { - auto it = w->attributes.find(ID(init)); + auto it = w->attributes.find(ID::init); if (it != w->attributes.end()) { SigSpec sig = pm.sigmap(w); Const val = it->second; @@ -109,7 +109,7 @@ struct PeepoptPass : public Pass { pm.run_dffmux(); for (auto w : module->wires()) { - auto it = w->attributes.find(ID(init)); + auto it = w->attributes.find(ID::init); if (it != w->attributes.end()) { SigSpec sig = pm.sigmap(w); Const &val = it->second; diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 72dc18dcc..9cfad03ef 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -40,16 +40,16 @@ void reduce_chain(test_pmgen_pm &pm) log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); SigSpec A; - SigSpec Y = ud.longest_chain.front().first->getPort(ID(Y)); + SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y); auto last_cell = ud.longest_chain.back().first; for (auto it : ud.longest_chain) { auto cell = it.first; if (cell == last_cell) { - A.append(cell->getPort(ID(A))); - A.append(cell->getPort(ID(B))); + A.append(cell->getPort(ID::A)); + A.append(cell->getPort(ID::B)); } else { - A.append(cell->getPort(it.second == ID(A) ? ID(B) : ID(A))); + A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A)); } log(" %s\n", log_id(cell)); pm.autoremove(cell); @@ -78,7 +78,7 @@ void reduce_tree(test_pmgen_pm &pm) return; SigSpec A = ud.leaves; - SigSpec Y = st.first->getPort(ID(Y)); + SigSpec Y = st.first->getPort(ID::Y); pm.autoremove(st.first); log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type), diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index ae7967d7c..f1f4b4206 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -52,7 +52,7 @@ static Cell* addDsp(Module *module) { cell->setParam(ID(USE_SIMD), Const("ONE48")); cell->setParam(ID(USE_DPORT), Const("FALSE")); - cell->setPort(ID(D), Const(0, 25)); + cell->setPort(ID::D, Const(0, 25)); cell->setPort(ID(INMODE), Const(0, 5)); cell->setPort(ID(ALUMODE), Const(0, 4)); cell->setPort(ID(OPMODE), Const(0, 7)); @@ -72,15 +72,15 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells) for (auto cell : selected_cells) { if (!cell->type.in(ID($add), ID($sub))) continue; - SigSpec Y = cell->getPort(ID(Y)); + SigSpec Y = cell->getPort(ID::Y); if (!Y.is_chunk()) continue; if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd")) continue; if (GetSize(Y) > 25) continue; - SigSpec A = cell->getPort(ID(A)); - SigSpec B = cell->getPort(ID(B)); + SigSpec A = cell->getPort(ID::A); + SigSpec B = cell->getPort(ID::B); if (GetSize(Y) <= 13) { if (GetSize(A) > 12) continue; @@ -106,11 +106,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells) } auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) { - SigSpec A = lane->getPort(ID(A)); - SigSpec B = lane->getPort(ID(B)); - SigSpec Y = lane->getPort(ID(Y)); - A.extend_u0(12, lane->getParam(ID(A_SIGNED)).as_bool()); - B.extend_u0(12, lane->getParam(ID(B_SIGNED)).as_bool()); + SigSpec A = lane->getPort(ID::A); + SigSpec B = lane->getPort(ID::B); + SigSpec Y = lane->getPort(ID::Y); + A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool()); + B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool()); AB.append(A); C.append(B); if (GetSize(Y) < 13) @@ -174,10 +174,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells) log_assert(GetSize(C) == 48); log_assert(GetSize(P) == 48); log_assert(GetSize(CARRYOUT) == 4); - cell->setPort(ID(A), AB.extract(18, 30)); - cell->setPort(ID(B), AB.extract(0, 18)); - cell->setPort(ID(C), C); - cell->setPort(ID(P), P); + cell->setPort(ID::A, AB.extract(18, 30)); + cell->setPort(ID::B, AB.extract(0, 18)); + cell->setPort(ID::C, C); + cell->setPort(ID::P, P); cell->setPort(ID(CARRYOUT), CARRYOUT); if (lane1->type == ID($sub)) cell->setPort(ID(ALUMODE), Const::from_string("0011")); @@ -194,11 +194,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells) g12(simd12_sub); auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) { - SigSpec A = lane->getPort(ID(A)); - SigSpec B = lane->getPort(ID(B)); - SigSpec Y = lane->getPort(ID(Y)); - A.extend_u0(24, lane->getParam(ID(A_SIGNED)).as_bool()); - B.extend_u0(24, lane->getParam(ID(B_SIGNED)).as_bool()); + SigSpec A = lane->getPort(ID::A); + SigSpec B = lane->getPort(ID::B); + SigSpec Y = lane->getPort(ID::Y); + A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool()); + B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool()); C.append(A); AB.append(B); if (GetSize(Y) < 25) @@ -238,10 +238,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells) log_assert(GetSize(C) == 48); log_assert(GetSize(P) == 48); log_assert(GetSize(CARRYOUT) == 4); - cell->setPort(ID(A), AB.extract(18, 30)); - cell->setPort(ID(B), AB.extract(0, 18)); - cell->setPort(ID(C), C); - cell->setPort(ID(P), P); + cell->setPort(ID::A, AB.extract(18, 30)); + cell->setPort(ID::B, AB.extract(0, 18)); + cell->setPort(ID::C, C); + cell->setPort(ID::P, P); cell->setPort(ID(CARRYOUT), CARRYOUT); if (lane1->type == ID($sub)) cell->setPort(ID(ALUMODE), Const::from_string("0011")); @@ -280,19 +280,19 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (st.preAdd) { log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type)); - bool A_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool(); - bool D_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool(); - if (st.sigA == st.preAdd->getPort(ID(B))) + bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool(); + bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool(); + if (st.sigA == st.preAdd->getPort(ID::B)) std::swap(A_SIGNED, D_SIGNED); st.sigA.extend_u0(30, A_SIGNED); st.sigD.extend_u0(25, D_SIGNED); - cell->setPort(ID(A), st.sigA); - cell->setPort(ID(D), st.sigD); + cell->setPort(ID::A, st.sigA); + cell->setPort(ID::D, st.sigD); cell->setPort(ID(INMODE), Const::from_string("00100")); if (st.ffAD) { if (st.ffADcemux) { - SigSpec S = st.ffADcemux->getPort(ID(S)); + SigSpec S = st.ffADcemux->getPort(ID::S); cell->setPort(ID(CEAD), st.ffADcepol ? S : pm.module->Not(NEW_ID, S)); } else @@ -310,7 +310,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) SigSpec &opmode = cell->connections_.at(ID(OPMODE)); if (st.postAddMux) { log_assert(st.ffP); - opmode[4] = st.postAddMux->getPort(ID(S)); + opmode[4] = st.postAddMux->getPort(ID::S); pm.autoremove(st.postAddMux); } else if (st.ffP && st.sigC == st.sigP) @@ -321,11 +321,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) opmode[5] = State::S1; if (opmode[4] != State::S0) { - if (st.postAddMuxAB == ID(A)) - st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool()); + if (st.postAddMuxAB == ID::A) + st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool()); else - st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool()); - cell->setPort(ID(C), st.sigC); + st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool()); + cell->setPort(ID::C, st.sigC); } pm.autoremove(st.postAdd); @@ -337,7 +337,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(SEL_MASK), Const("MASK")); if (st.overflow->type == ID($ge)) { - Const B = st.overflow->getPort(ID(B)).as_const(); + Const B = st.overflow->getPort(ID::B).as_const(); log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1); // Since B is an exact power of 2, subtract 1 // by inverting all bits up until hitting @@ -352,7 +352,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(MASK), B); cell->setParam(ID(PATTERN), Const(0, 48)); - cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID(Y))); + cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y)); } else log_abort(); @@ -361,29 +361,29 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID(CLK), st.clock); + cell->setPort(ID::CLK, st.clock); auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) { - SigSpec D = ff->getPort(ID(D)); - SigSpec Q = pm.sigmap(ff->getPort(ID(Q))); + SigSpec D = ff->getPort(ID::D); + SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); if (rstmux) { - SigSpec Y = rstmux->getPort(ID(Y)); - SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B)); + SigSpec Y = rstmux->getPort(ID::Y); + SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B); if (!A.empty()) A.replace(Y, AB); if (rstport != IdString()) { - SigSpec S = rstmux->getPort(ID(S)); + SigSpec S = rstmux->getPort(ID::S); cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S)); } } else if (rstport != IdString()) cell->setPort(rstport, State::S0); if (cemux) { - SigSpec Y = cemux->getPort(ID(Y)); - SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A)); - SigSpec S = cemux->getPort(ID(S)); + SigSpec Y = cemux->getPort(ID::Y); + SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A); + SigSpec S = cemux->getPort(ID::S); if (!A.empty()) A.replace(Y, BA); cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S)); @@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setPort(ceport, State::S1); for (auto c : Q.chunks()) { - auto it = c.wire->attributes.find(ID(init)); + auto it = c.wire->attributes.find(ID::init); if (it == c.wire->attributes.end()) continue; for (int i = c.offset; i < c.offset+c.width; i++) { @@ -403,7 +403,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) }; if (st.ffA2) { - SigSpec A = cell->getPort(ID(A)); + SigSpec A = cell->getPort(ID::A); f(A, st.ffA2, st.ffA2cemux, st.ffA2cepol, ID(CEA2), st.ffA2rstmux, st.ffArstpol, ID(RSTA)); if (st.ffA1) { f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, ID(CEA1), st.ffA1rstmux, st.ffArstpol, IdString()); @@ -415,10 +415,10 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(ACASCREG), 1); } pm.add_siguser(A, cell); - cell->setPort(ID(A), A); + cell->setPort(ID::A, A); } if (st.ffB2) { - SigSpec B = cell->getPort(ID(B)); + SigSpec B = cell->getPort(ID::B); f(B, st.ffB2, st.ffB2cemux, st.ffB2cepol, ID(CEB2), st.ffB2rstmux, st.ffBrstpol, ID(RSTB)); if (st.ffB1) { f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, ID(CEB1), st.ffB1rstmux, st.ffBrstpol, IdString()); @@ -430,25 +430,25 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(BCASCREG), 1); } pm.add_siguser(B, cell); - cell->setPort(ID(B), B); + cell->setPort(ID::B, B); } if (st.ffD) { - SigSpec D = cell->getPort(ID(D)); + SigSpec D = cell->getPort(ID::D); f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD)); pm.add_siguser(D, cell); - cell->setPort(ID(D), D); + cell->setPort(ID::D, D); cell->setParam(ID(DREG), 1); } if (st.ffM) { SigSpec M; // unused f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM)); - st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); + st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); cell->setParam(ID(MREG), State::S1); } if (st.ffP) { SigSpec P; // unused f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP)); - st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); cell->setParam(ID(PREG), State::S1); } @@ -483,7 +483,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); - cell->setPort(ID(P), P); + cell->setPort(ID::P, P); pm.blacklist(cell); } @@ -511,12 +511,12 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (st.preAdd) { log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type)); - bool D_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool(); - bool B_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool(); + bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool(); + bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool(); st.sigB.extend_u0(18, B_SIGNED); st.sigD.extend_u0(18, D_SIGNED); - cell->setPort(ID(B), st.sigB); - cell->setPort(ID(D), st.sigD); + cell->setPort(ID::B, st.sigB); + cell->setPort(ID::D, st.sigD); opmode[4] = State::S1; if (st.preAdd->type == ID($add)) opmode[6] = State::S0; @@ -532,7 +532,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (st.postAddMux) { log_assert(st.ffP); - opmode[2] = st.postAddMux->getPort(ID(S)); + opmode[2] = st.postAddMux->getPort(ID::S); pm.autoremove(st.postAddMux); } else if (st.ffP && st.sigC == st.sigP) @@ -542,11 +542,11 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) opmode[3] = State::S1; if (opmode[2] != State::S0) { - if (st.postAddMuxAB == ID(A)) - st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool()); + if (st.postAddMuxAB == ID::A) + st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool()); else - st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool()); - cell->setPort(ID(C), st.sigC); + st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool()); + cell->setPort(ID::C, st.sigC); } pm.autoremove(st.postAdd); @@ -554,29 +554,29 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID(CLK), st.clock); + cell->setPort(ID::CLK, st.clock); auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) { - SigSpec D = ff->getPort(ID(D)); - SigSpec Q = pm.sigmap(ff->getPort(ID(Q))); + SigSpec D = ff->getPort(ID::D); + SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); if (rstmux) { - SigSpec Y = rstmux->getPort(ID(Y)); - SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B)); + SigSpec Y = rstmux->getPort(ID::Y); + SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B); if (!A.empty()) A.replace(Y, AB); if (rstport != IdString()) { - SigSpec S = rstmux->getPort(ID(S)); + SigSpec S = rstmux->getPort(ID::S); cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S)); } } else if (rstport != IdString()) cell->setPort(rstport, State::S0); if (cemux) { - SigSpec Y = cemux->getPort(ID(Y)); - SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A)); - SigSpec S = cemux->getPort(ID(S)); + SigSpec Y = cemux->getPort(ID::Y); + SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A); + SigSpec S = cemux->getPort(ID::S); if (!A.empty()) A.replace(Y, BA); cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S)); @@ -585,7 +585,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) cell->setPort(ceport, State::S1); for (auto c : Q.chunks()) { - auto it = c.wire->attributes.find(ID(init)); + auto it = c.wire->attributes.find(ID::init); if (it == c.wire->attributes.end()) continue; for (int i = c.offset; i < c.offset+c.width; i++) { @@ -596,7 +596,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) }; if (st.ffA0 || st.ffA1) { - SigSpec A = cell->getPort(ID(A)); + SigSpec A = cell->getPort(ID::A); if (st.ffA1) { f(A, st.ffA1, st.ffA1cemux, st.ffAcepol, ID(CEA), st.ffA1rstmux, st.ffArstpol, ID(RSTA)); cell->setParam(ID(A1REG), 1); @@ -606,10 +606,10 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) cell->setParam(ID(A0REG), 1); } pm.add_siguser(A, cell); - cell->setPort(ID(A), A); + cell->setPort(ID::A, A); } if (st.ffB0 || st.ffB1) { - SigSpec B = cell->getPort(ID(B)); + SigSpec B = cell->getPort(ID::B); if (st.ffB1) { f(B, st.ffB1, st.ffB1cemux, st.ffBcepol, ID(CEB), st.ffB1rstmux, st.ffBrstpol, ID(RSTB)); cell->setParam(ID(B1REG), 1); @@ -619,25 +619,25 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) cell->setParam(ID(B0REG), 1); } pm.add_siguser(B, cell); - cell->setPort(ID(B), B); + cell->setPort(ID::B, B); } if (st.ffD) { - SigSpec D = cell->getPort(ID(D)); + SigSpec D = cell->getPort(ID::D); f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD)); pm.add_siguser(D, cell); - cell->setPort(ID(D), D); + cell->setPort(ID::D, D); cell->setParam(ID(DREG), 1); } if (st.ffM) { SigSpec M; // unused f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM)); - st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); + st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); cell->setParam(ID(MREG), State::S1); } if (st.ffP) { SigSpec P; // unused f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP)); - st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); + st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); cell->setParam(ID(PREG), State::S1); } @@ -667,7 +667,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) SigSpec P = st.sigP; if (GetSize(P) < 48) P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); - cell->setPort(ID(P), P); + cell->setPort(ID::P, P); pm.blacklist(cell); } @@ -683,29 +683,29 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) if (st.clock != SigBit()) { - cell->setPort(ID(CLK), st.clock); + cell->setPort(ID::CLK, st.clock); auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) { - SigSpec D = ff->getPort(ID(D)); - SigSpec Q = pm.sigmap(ff->getPort(ID(Q))); + SigSpec D = ff->getPort(ID::D); + SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); if (rstmux) { - SigSpec Y = rstmux->getPort(ID(Y)); - SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B)); + SigSpec Y = rstmux->getPort(ID::Y); + SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B); if (!A.empty()) A.replace(Y, AB); if (rstport != IdString()) { - SigSpec S = rstmux->getPort(ID(S)); + SigSpec S = rstmux->getPort(ID::S); cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S)); } } else if (rstport != IdString()) cell->setPort(rstport, State::S0); if (cemux) { - SigSpec Y = cemux->getPort(ID(Y)); - SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A)); - SigSpec S = cemux->getPort(ID(S)); + SigSpec Y = cemux->getPort(ID::Y); + SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A); + SigSpec S = cemux->getPort(ID::S); if (!A.empty()) A.replace(Y, BA); cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S)); @@ -714,7 +714,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) cell->setPort(ceport, State::S1); for (auto c : Q.chunks()) { - auto it = c.wire->attributes.find(ID(init)); + auto it = c.wire->attributes.find(ID::init); if (it == c.wire->attributes.end()) continue; for (int i = c.offset; i < c.offset+c.width; i++) { @@ -725,10 +725,10 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) }; if (st.ffC) { - SigSpec C = cell->getPort(ID(C)); + SigSpec C = cell->getPort(ID::C); f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC)); pm.add_siguser(C, cell); - cell->setPort(ID(C), C); + cell->setPort(ID::C, C); cell->setParam(ID(CREG), 1); } diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 3d264e8d4..24b525b93 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -36,9 +36,9 @@ void run_fixed(xilinx_srl_pm &pm) for (auto cell : ud.longest_chain) { log_debug(" %s\n", log_id(cell)); if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { - SigBit Q = cell->getPort(ID(Q)); + SigBit Q = cell->getPort(ID::Q); log_assert(Q.wire); - auto it = Q.wire->attributes.find(ID(init)); + auto it = Q.wire->attributes.find(ID::init); if (it != Q.wire->attributes.end()) { auto &i = it->second[Q.offset]; initval.append(i); @@ -48,7 +48,7 @@ void run_fixed(xilinx_srl_pm &pm) initval.append(State::Sx); } else if (cell->type.in(ID(FDRE), ID(FDRE_1))) { - if (cell->parameters.at(ID(INIT), State::S0).as_bool()) + if (cell->parameters.at(ID::INIT, State::S0).as_bool()) initval.append(State::S1); else initval.append(State::S0); @@ -64,11 +64,11 @@ void run_fixed(xilinx_srl_pm &pm) pm.module->swap_names(c, first_cell); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { - c->setParam(ID(DEPTH), GetSize(ud.longest_chain)); - c->setParam(ID(INIT), initval.as_const()); + c->setParam(ID::DEPTH, GetSize(ud.longest_chain)); + c->setParam(ID::INIT, initval.as_const()); if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) c->setParam(ID(CLKPOL), 1); - else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) + else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) c->setParam(ID(CLKPOL), 0); else if (first_cell->type.in(ID(FDRE))) { if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool()) @@ -85,16 +85,16 @@ void run_fixed(xilinx_srl_pm &pm) else c->setParam(ID(ENPOL), 2); - c->setPort(ID(C), first_cell->getPort(ID(C))); - c->setPort(ID(D), first_cell->getPort(ID(D))); - c->setPort(ID(Q), last_cell->getPort(ID(Q))); - c->setPort(ID(L), GetSize(ud.longest_chain)-1); + c->setPort(ID::C, first_cell->getPort(ID::C)); + c->setPort(ID::D, first_cell->getPort(ID::D)); + c->setPort(ID::Q, last_cell->getPort(ID::Q)); + c->setPort(ID::L, GetSize(ud.longest_chain)-1); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) - c->setPort(ID(E), State::S1); + c->setPort(ID::E, State::S1); else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - c->setPort(ID(E), first_cell->getPort(ID(E))); + c->setPort(ID::E, first_cell->getPort(ID::E)); else if (first_cell->type.in(ID(FDRE), ID(FDRE_1))) - c->setPort(ID(E), first_cell->getPort(ID(CE))); + c->setPort(ID::E, first_cell->getPort(ID(CE))); else log_abort(); } @@ -117,9 +117,9 @@ void run_variable(xilinx_srl_pm &pm) auto slice = i.second; log_debug(" %s\n", log_id(cell)); if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { - SigBit Q = cell->getPort(ID(Q))[slice]; + SigBit Q = cell->getPort(ID::Q)[slice]; log_assert(Q.wire); - auto it = Q.wire->attributes.find(ID(init)); + auto it = Q.wire->attributes.find(ID::init); if (it != Q.wire->attributes.end()) { auto &i = it->second[Q.offset]; initval.append(i); @@ -140,15 +140,15 @@ void run_variable(xilinx_srl_pm &pm) pm.module->swap_names(c, first_cell); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { - c->setParam(ID(DEPTH), GetSize(ud.chain)); - c->setParam(ID(INIT), initval.as_const()); + c->setParam(ID::DEPTH, GetSize(ud.chain)); + c->setParam(ID::INIT, initval.as_const()); Const clkpol, enpol; if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) clkpol = 1; - else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_))) + else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_))) clkpol = 0; else if (first_cell->type.in(ID($dff), ID($dffe))) - clkpol = first_cell->getParam(ID(CLK_POLARITY)); + clkpol = first_cell->getParam(ID::CLK_POLARITY); else log_abort(); if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) @@ -156,27 +156,27 @@ void run_variable(xilinx_srl_pm &pm) else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) enpol = 0; else if (first_cell->type.in(ID($dffe))) - enpol = first_cell->getParam(ID(EN_POLARITY)); + enpol = first_cell->getParam(ID::EN_POLARITY); else enpol = 2; c->setParam(ID(CLKPOL), clkpol); c->setParam(ID(ENPOL), enpol); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - c->setPort(ID(C), first_cell->getPort(ID(C))); + c->setPort(ID::C, first_cell->getPort(ID::C)); else if (first_cell->type.in(ID($dff), ID($dffe))) - c->setPort(ID(C), first_cell->getPort(ID(CLK))); + c->setPort(ID::C, first_cell->getPort(ID::CLK)); else log_abort(); - c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]); - c->setPort(ID(Q), st.shiftx->getPort(ID(Y))); - c->setPort(ID(L), st.shiftx->getPort(ID(B))); + c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]); + c->setPort(ID::Q, st.shiftx->getPort(ID::Y)); + c->setPort(ID::L, st.shiftx->getPort(ID::B)); if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff))) - c->setPort(ID(E), State::S1); + c->setPort(ID::E, State::S1); else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - c->setPort(ID(E), first_cell->getPort(ID(E))); + c->setPort(ID::E, first_cell->getPort(ID::E)); else if (first_cell->type.in(ID($dffe))) - c->setPort(ID(E), first_cell->getPort(ID(EN))); + c->setPort(ID::E, first_cell->getPort(ID::EN)); else log_abort(); } diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index c606deb88..e400fcb72 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -39,45 +39,45 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, for (auto cell : mod->cells()) { - if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal) - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal) + return check_signal(mod, cell->getPort(ID::A), ref, polarity); - if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal) - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal) + return check_signal(mod, cell->getPort(ID::A), ref, polarity); - if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) { + if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) { polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } - if (cell->type == "$not" && cell->getPort("\\Y") == signal) { + if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) { polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } - if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) { - if (cell->getPort("\\A").is_fully_const()) { - if (!cell->getPort("\\A").as_bool()) + if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) { + if (cell->getPort(ID::A).is_fully_const()) { + if (!cell->getPort(ID::A).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\B"), ref, polarity); + return check_signal(mod, cell->getPort(ID::B), ref, polarity); } - if (cell->getPort("\\B").is_fully_const()) { - if (!cell->getPort("\\B").as_bool()) + if (cell->getPort(ID::B).is_fully_const()) { + if (!cell->getPort(ID::B).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } } - if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) { - if (cell->getPort("\\A").is_fully_const()) { - if (cell->getPort("\\A").as_bool()) + if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) { + if (cell->getPort(ID::A).is_fully_const()) { + if (cell->getPort(ID::A).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\B"), ref, polarity); + return check_signal(mod, cell->getPort(ID::B), ref, polarity); } - if (cell->getPort("\\B").is_fully_const()) { - if (cell->getPort("\\B").as_bool()) + if (cell->getPort(ID::B).is_fully_const()) { + if (cell->getPort(ID::B).as_bool()) polarity = !polarity; - return check_signal(mod, cell->getPort("\\A"), ref, polarity); + return check_signal(mod, cell->getPort(ID::A), ref, polarity); } } } @@ -261,8 +261,8 @@ struct ProcArstPass : public Pass { for (auto &act : sync->actions) { RTLIL::SigSpec arst_sig, arst_val; for (auto &chunk : act.first.chunks()) - if (chunk.wire && chunk.wire->attributes.count("\\init")) { - RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); + if (chunk.wire && chunk.wire->attributes.count(ID::init)) { + RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init); value.extend_u0(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); @@ -285,7 +285,7 @@ struct ProcArstPass : public Pass { } for (auto wire : delete_initattr_wires) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); } } ProcArstPass; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 519d35cd6..59cc5bd65 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -75,69 +75,69 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec log_abort(); if (sync_low_signals.size() > 1) { - RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); - cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); - cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", sync_low_signals); - cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID)); + RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or)); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size()); + cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); + cell->setPort(ID::A, sync_low_signals); + cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID)); } if (sync_low_signals.size() > 0) { - RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not"); - cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); - cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", sync_low_signals); - cell->setPort("\\Y", mod->addWire(NEW_ID)); - sync_high_signals.append(cell->getPort("\\Y")); + RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not)); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size()); + cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); + cell->setPort(ID::A, sync_low_signals); + cell->setPort(ID::Y, mod->addWire(NEW_ID)); + sync_high_signals.append(cell->getPort(ID::Y)); } if (sync_high_signals.size() > 1) { - RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); - cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); - cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", sync_high_signals); - cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID)); + RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or)); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size()); + cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); + cell->setPort(ID::A, sync_high_signals); + cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID)); } - RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); - inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->setPort("\\A", sync_value); - inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); - - RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); - mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->setPort("\\A", sig_sr_set); - mux_set_cell->setPort("\\B", sync_value); - mux_set_cell->setPort("\\S", sync_high_signals); - mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); - - RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); - mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->setPort("\\A", sig_sr_clr); - mux_clr_cell->setPort("\\B", sync_value_inv); - mux_clr_cell->setPort("\\S", sync_high_signals); - mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); + RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not)); + inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); + inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size()); + inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size()); + inv_cell->setPort(ID::A, sync_value); + inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); + + RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux)); + mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size()); + mux_set_cell->setPort(ID::A, sig_sr_set); + mux_set_cell->setPort(ID::B, sync_value); + mux_set_cell->setPort(ID::S, sync_high_signals); + mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); + + RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux)); + mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size()); + mux_clr_cell->setPort(ID::A, sig_sr_clr); + mux_clr_cell->setPort(ID::B, sync_value_inv); + mux_clr_cell->setPort(ID::S, sync_high_signals); + mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); } std::stringstream sstr; sstr << "$procdff$" << (autoidx++); - RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); + RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr)); cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); - cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); - cell->setPort("\\CLK", clk); - cell->setPort("\\SET", sig_sr_set); - cell->setPort("\\CLR", sig_sr_clr); + cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size()); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1); + cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1); + cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); + cell->setPort(ID::CLK, clk); + cell->setPort(ID::SET, sig_sr_set); + cell->setPort(ID::CLR, sig_sr_clr); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -153,38 +153,38 @@ void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); - RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not"); - inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->setPort("\\A", sig_set); - inv_set->setPort("\\Y", sig_set_inv); - - RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); - mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set); - mux_sr_set->setPort("\\Y", sig_sr_set); - mux_sr_set->setPort("\\S", set); - - RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); - mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv); - mux_sr_clr->setPort("\\Y", sig_sr_clr); - mux_sr_clr->setPort("\\S", set); - - RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); + RTLIL::Cell *inv_set = mod->addCell(NEW_ID, ID($not)); + inv_set->parameters[ID::A_SIGNED] = RTLIL::Const(0); + inv_set->parameters[ID::A_WIDTH] = RTLIL::Const(sig_in.size()); + inv_set->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_in.size()); + inv_set->setPort(ID::A, sig_set); + inv_set->setPort(ID::Y, sig_set_inv); + + RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, ID($mux)); + mux_sr_set->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); + mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size())); + mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set); + mux_sr_set->setPort(ID::Y, sig_sr_set); + mux_sr_set->setPort(ID::S, set); + + RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, ID($mux)); + mux_sr_clr->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); + mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size())); + mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv); + mux_sr_clr->setPort(ID::Y, sig_sr_clr); + mux_sr_clr->setPort(ID::S, set); + + RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr)); cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); - cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->setPort("\\D", sig_in); - cell->setPort("\\Q", sig_out); - cell->setPort("\\CLK", clk); - cell->setPort("\\SET", sig_sr_set); - cell->setPort("\\CLR", sig_sr_clr); + cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1); + cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1); + cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1); + cell->setPort(ID::D, sig_in); + cell->setPort(ID::Q, sig_out); + cell->setPort(ID::CLK, clk); + cell->setPort(ID::SET, sig_sr_set); + cell->setPort(ID::CLR, sig_sr_clr); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -196,24 +196,24 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT std::stringstream sstr; sstr << "$procdff$" << (autoidx++); - RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? "$ff" : arst ? "$adff" : "$dff"); + RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff)); cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); if (arst) { - cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); - cell->parameters["\\ARST_VALUE"] = val_rst; + cell->parameters[ID::ARST_POLARITY] = RTLIL::Const(arst_polarity, 1); + cell->parameters[ID::ARST_VALUE] = val_rst; } if (!clk.empty()) { - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); + cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1); } - cell->setPort("\\D", sig_in); - cell->setPort("\\Q", sig_out); + cell->setPort(ID::D, sig_in); + cell->setPort(ID::Q, sig_out); if (arst) - cell->setPort("\\ARST", *arst); + cell->setPort(ID::ARST, *arst); if (!clk.empty()) - cell->setPort("\\CLK", clk); + cell->setPort(ID::CLK, clk); if (!clk.empty()) log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -303,15 +303,15 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } log_assert(inputs.size() == compare.size()); - RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne"); - cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); - cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->setPort("\\A", inputs); - cell->setPort("\\B", compare); - cell->setPort("\\Y", sync_level->signal); + RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne)); + cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1); + cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1); + cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size()); + cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size()); + cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); + cell->setPort(ID::A, inputs); + cell->setPort(ID::B, compare); + cell->setPort(ID::Y, sync_level->signal); many_async_rules.clear(); } diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index a0c8351b6..c9da1d1e3 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -42,16 +42,16 @@ struct proc_dlatch_db_t { for (auto cell : module->cells()) { - if (cell->type.in("$mux", "$pmux")) + if (cell->type.in(ID($mux), ID($pmux))) { - auto sig_y = sigmap(cell->getPort("\\Y")); + auto sig_y = sigmap(cell->getPort(ID::Y)); for (int i = 0; i < GetSize(sig_y); i++) mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i); pool<SigBit> mux_srcbits_pool; - for (auto bit : sigmap(cell->getPort("\\A"))) + for (auto bit : sigmap(cell->getPort(ID::A))) mux_srcbits_pool.insert(bit); - for (auto bit : sigmap(cell->getPort("\\B"))) + for (auto bit : sigmap(cell->getPort(ID::B))) mux_srcbits_pool.insert(bit); vector<SigBit> mux_srcbits_vec; @@ -180,9 +180,9 @@ struct proc_dlatch_db_t Cell *cell = it->second.first; int index = it->second.second; - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); int width = GetSize(sig_a); pool<int> children; @@ -190,9 +190,9 @@ struct proc_dlatch_db_t int n = find_mux_feedback(sig_a[index], needle, set_undef); if (n != false_node) { if (set_undef && sig_a[index] == needle) { - SigSpec sig = cell->getPort("\\A"); + SigSpec sig = cell->getPort(ID::A); sig[index] = State::Sx; - cell->setPort("\\A", sig); + cell->setPort(ID::A, sig); } for (int i = 0; i < GetSize(sig_s); i++) n = make_inner(sig_s[i], State::S0, n); @@ -203,9 +203,9 @@ struct proc_dlatch_db_t n = find_mux_feedback(sig_b[i*width + index], needle, set_undef); if (n != false_node) { if (set_undef && sig_b[i*width + index] == needle) { - SigSpec sig = cell->getPort("\\B"); + SigSpec sig = cell->getPort(ID::B); sig[i*width + index] = State::Sx; - cell->setPort("\\B", sig); + cell->setPort(ID::B, sig); } children.insert(make_inner(sig_s[i], State::S1, n)); } @@ -257,9 +257,9 @@ struct proc_dlatch_db_t void fixup_mux(Cell *cell) { - SigSpec sig_a = cell->getPort("\\A"); - SigSpec sig_b = cell->getPort("\\B"); - SigSpec sig_s = cell->getPort("\\S"); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_b = cell->getPort(ID::B); + SigSpec sig_s = cell->getPort(ID::S); SigSpec sig_any_valid_b; SigSpec sig_new_b, sig_new_s; @@ -278,18 +278,18 @@ struct proc_dlatch_db_t } if (sig_a.is_fully_undef() && !sig_any_valid_b.empty()) - cell->setPort("\\A", sig_any_valid_b); + cell->setPort(ID::A, sig_any_valid_b); if (GetSize(sig_new_s) == 1) { - cell->type = "$mux"; - cell->unsetParam("\\S_WIDTH"); + cell->type = ID($mux); + cell->unsetParam(ID::S_WIDTH); } else { - cell->type = "$pmux"; - cell->setParam("\\S_WIDTH", GetSize(sig_new_s)); + cell->type = ID($pmux); + cell->setParam(ID::S_WIDTH, GetSize(sig_new_s)); } - cell->setPort("\\B", sig_new_b); - cell->setPort("\\S", sig_new_s); + cell->setPort(ID::B, sig_new_b); + cell->setPort(ID::S, sig_new_s); } void fixup_muxes() @@ -317,7 +317,7 @@ struct proc_dlatch_db_t pool<Cell*> next_queue; for (auto cell : queue) { - if (cell->type.in("$mux", "$pmux")) + if (cell->type.in(ID($mux), ID($pmux))) fixup_mux(cell); for (auto bit : upstream_cell2net[cell]) for (auto cell : upstream_net2cell[bit]) @@ -349,7 +349,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) continue; } - if (proc->get_bool_attribute(ID(always_ff))) + if (proc->get_bool_attribute(ID::always_ff)) log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n", db.module->name.c_str(), proc->name.c_str()); @@ -387,7 +387,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) int offset = 0; for (auto chunk : nolatches_bits.first.chunks()) { SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width); - if (proc->get_bool_attribute(ID(always_latch))) + if (proc->get_bool_attribute(ID::always_latch)) log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); else @@ -418,7 +418,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) cell->set_src_attribute(src); db.generated_dlatches.insert(cell); - if (proc->get_bool_attribute(ID(always_comb))) + if (proc->get_bool_attribute(ID::always_comb)) log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); else diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 462a384b7..dc00019aa 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -54,7 +54,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig)); Const value = valuesig.as_const(); - Const &wireinit = lhs_c.wire->attributes["\\init"]; + Const &wireinit = lhs_c.wire->attributes[ID::init]; while (GetSize(wireinit.bits) < lhs_c.wire->width) wireinit.bits.push_back(State::Sx); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index d029282fd..867ba1698 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -147,7 +147,7 @@ struct SnippetSwCache void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs) { cell->attributes = sw->attributes; - cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src")); + cell->add_strpool_attribute(ID::src, cs->get_strpool_attribute(ID::src)); } RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) @@ -178,19 +178,19 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s else { // create compare cell - RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq"); + RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq)); apply_attrs(eq_cell, sw, cs); - eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); + eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); + eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); - eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size()); + eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size()); + eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - eq_cell->setPort("\\A", sig); - eq_cell->setPort("\\B", comp); - eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); + eq_cell->setPort(ID::A, sig); + eq_cell->setPort(ID::B, comp); + eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); } } @@ -204,15 +204,15 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s ctrl_wire = mod->addWire(sstr.str() + "_CTRL"); // reduce cmp vector to one logic signal - RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or"); + RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or)); apply_attrs(any_cell, sw, cs); - any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); - any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); + any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width); + any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - any_cell->setPort("\\A", cmp_wire); - any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire)); + any_cell->setPort(ID::A, cmp_wire); + any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire)); } return RTLIL::SigSpec(ctrl_wire); @@ -239,14 +239,14 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size()); // create the multiplexer itself - RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux"); + RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux)); apply_attrs(mux_cell, sw, cs); - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->setPort("\\A", else_signal); - mux_cell->setPort("\\B", when_signal); - mux_cell->setPort("\\S", ctrl_sig); - mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire)); + mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size()); + mux_cell->setPort(ID::A, else_signal); + mux_cell->setPort(ID::B, when_signal); + mux_cell->setPort(ID::S, ctrl_sig); + mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire)); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -255,24 +255,24 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) { log_assert(last_mux_cell != NULL); - log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size()); + log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size()); - if (when_signal == last_mux_cell->getPort("\\A")) + if (when_signal == last_mux_cell->getPort(ID::A)) return; RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode); log_assert(ctrl_sig.size() == 1); - last_mux_cell->type = "$pmux"; + last_mux_cell->type = ID($pmux); - RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S"); + RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S); new_s.append(ctrl_sig); - last_mux_cell->setPort("\\S", new_s); + last_mux_cell->setPort(ID::S, new_s); - RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B"); + RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B); new_b.append(when_signal); - last_mux_cell->setPort("\\B", new_b); + last_mux_cell->setPort(ID::B, new_b); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size(); + last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size(); } const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw) @@ -281,7 +281,7 @@ const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRul { pool<SigBit> bits; - if (sw->get_bool_attribute("\\full_case")) + if (sw->get_bool_attribute(ID::full_case)) { bool first_case = true; @@ -337,7 +337,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d std::vector<int> pgroups(sw->cases.size()); bool is_simple_parallel_case = true; - if (!sw->get_bool_attribute("\\parallel_case")) { + if (!sw->get_bool_attribute(ID::parallel_case)) { if (!swpara.count(sw)) { pool<Const> case_values; for (size_t i = 0; i < sw->cases.size(); i++) { diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index d4aee9df0..8d11447f6 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -38,7 +38,7 @@ struct PruneWorker pool<RTLIL::SigBit> do_switch(RTLIL::SwitchRule *sw, pool<RTLIL::SigBit> assigned, pool<RTLIL::SigBit> &affected) { pool<RTLIL::SigBit> all_assigned; - bool full_case = sw->get_bool_attribute("\\full_case"); + bool full_case = sw->get_bool_attribute(ID::full_case); bool first = true; for (auto it : sw->cases) { if (it->compare.empty()) @@ -93,7 +93,7 @@ struct PruneWorker for (int i = 0; i < GetSize(lhs); i++) { RTLIL::SigBit lhs_bit = lhs[i]; if (lhs_bit.wire && !assigned[lhs_bit]) { - conn.first.append_bit(lhs_bit); + conn.first.append(lhs_bit); conn.second.append(rhs.extract(i)); } } diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 4f40be446..6afaf25d1 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -62,8 +62,8 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter) pool.take_all(); } - if (pool.empty() && !sw->get_bool_attribute("\\full_case")) { - sw->set_bool_attribute("\\full_case"); + if (pool.empty() && !sw->get_bool_attribute(ID::full_case)) { + sw->set_bool_attribute(ID::full_case); full_case_counter++; } } diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 3b432c461..5bf2296ab 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -52,14 +52,14 @@ struct AssertpmuxWorker for (auto cell : module->cells()) { - if (cell->type.in("$mux", "$pmux")) + if (cell->type.in(ID($mux), ID($pmux))) { - int width = cell->getParam("\\WIDTH").as_int(); - int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1; + int width = cell->getParam(ID::WIDTH).as_int(); + int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1; - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); for (int i = 0; i < numports; i++) { SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width); @@ -98,12 +98,12 @@ struct AssertpmuxWorker if (muxport_actsignal.count(muxport) == 0) { if (portidx == 0) - muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort("\\S")); + muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S)); else - muxport_actsignal[muxport] = cell->getPort("\\S")[portidx-1]; + muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1]; } - output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort("\\Y")[bitidx]))); + output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx]))); } output.sort_and_unify(); @@ -148,10 +148,10 @@ struct AssertpmuxWorker { log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux)); - int swidth = pmux->getParam("\\S_WIDTH").as_int(); + int swidth = pmux->getParam(ID::S_WIDTH).as_int(); int cntbits = ceil_log2(swidth+1); - SigSpec sel = pmux->getPort("\\S"); + SigSpec sel = pmux->getPort(ID::S); SigSpec cnt(State::S0, cntbits); for (int i = 0; i < swidth; i++) @@ -164,7 +164,7 @@ struct AssertpmuxWorker assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID))); if (!flag_always) - assert_en.append(get_activation(pmux->getPort("\\Y"))); + assert_en.append(get_activation(pmux->getPort(ID::Y))); if (GetSize(assert_en) == 0) assert_en = State::S1; @@ -174,8 +174,8 @@ struct AssertpmuxWorker Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en); - if (pmux->attributes.count("\\src") != 0) - assert_cell->attributes["\\src"] = pmux->attributes.at("\\src"); + if (pmux->attributes.count(ID::src) != 0) + assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src); } }; @@ -227,7 +227,7 @@ struct AssertpmuxPass : public Pass { vector<Cell*> pmux_cells; for (auto cell : module->selected_cells()) - if (cell->type == "$pmux") + if (cell->type == ID($pmux)) pmux_cells.push_back(cell); for (auto cell : pmux_cells) diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index 740248545..e344e2b5b 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -66,9 +66,9 @@ struct Async2syncPass : public Pass { pool<SigBit> del_initbits; for (auto wire : module->wires()) - if (wire->attributes.count("\\init") > 0) + if (wire->attributes.count(ID::init) > 0) { - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); SigSpec initsig = sigmap(wire); for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) @@ -78,16 +78,16 @@ struct Async2syncPass : public Pass { for (auto cell : vector<Cell*>(module->selected_cells())) { - if (cell->type.in("$adff")) + if (cell->type.in(ID($adff))) { - // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool(); - bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool(); - Const arst_val = cell->parameters["\\ARST_VALUE"]; + // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool(); + bool arst_pol = cell->parameters[ID::ARST_POLARITY].as_bool(); + Const arst_val = cell->parameters[ID::ARST_VALUE]; - // SigSpec sig_clk = cell->getPort("\\CLK"); - SigSpec sig_arst = cell->getPort("\\ARST"); - SigSpec sig_d = cell->getPort("\\D"); - SigSpec sig_q = cell->getPort("\\Q"); + // SigSpec sig_clk = cell->getPort(ID::CLK); + SigSpec sig_arst = cell->getPort(ID::ARST); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n", log_id(module), log_id(cell), log_id(cell->type), @@ -102,7 +102,7 @@ struct Async2syncPass : public Pass { Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); - new_q->attributes["\\init"] = init_val; + new_q->attributes[ID::init] = init_val; if (arst_pol) { module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d); @@ -112,26 +112,26 @@ struct Async2syncPass : public Pass { module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q); } - cell->setPort("\\D", new_d); - cell->setPort("\\Q", new_q); - cell->unsetPort("\\ARST"); - cell->unsetParam("\\ARST_POLARITY"); - cell->unsetParam("\\ARST_VALUE"); - cell->type = "$dff"; + cell->setPort(ID::D, new_d); + cell->setPort(ID::Q, new_q); + cell->unsetPort(ID::ARST); + cell->unsetParam(ID::ARST_POLARITY); + cell->unsetParam(ID::ARST_VALUE); + cell->type = ID($dff); continue; } - if (cell->type.in("$dffsr")) + if (cell->type.in(ID($dffsr))) { - // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool(); - bool set_pol = cell->parameters["\\SET_POLARITY"].as_bool(); - bool clr_pol = cell->parameters["\\CLR_POLARITY"].as_bool(); + // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool(); + bool set_pol = cell->parameters[ID::SET_POLARITY].as_bool(); + bool clr_pol = cell->parameters[ID::CLR_POLARITY].as_bool(); - // SigSpec sig_clk = cell->getPort("\\CLK"); - SigSpec sig_set = cell->getPort("\\SET"); - SigSpec sig_clr = cell->getPort("\\CLR"); - SigSpec sig_d = cell->getPort("\\D"); - SigSpec sig_q = cell->getPort("\\Q"); + // SigSpec sig_clk = cell->getPort(ID::CLK); + SigSpec sig_set = cell->getPort(ID::SET); + SigSpec sig_clr = cell->getPort(ID::CLR); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n", log_id(module), log_id(cell), log_id(cell->type), @@ -146,7 +146,7 @@ struct Async2syncPass : public Pass { Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); - new_q->attributes["\\init"] = init_val; + new_q->attributes[ID::init] = init_val; if (!set_pol) sig_set = module->Not(NEW_ID, sig_set); @@ -160,23 +160,23 @@ struct Async2syncPass : public Pass { tmp = module->Or(NEW_ID, new_q, sig_set); module->addAnd(NEW_ID, tmp, sig_clr, sig_q); - cell->setPort("\\D", new_d); - cell->setPort("\\Q", new_q); - cell->unsetPort("\\SET"); - cell->unsetPort("\\CLR"); - cell->unsetParam("\\SET_POLARITY"); - cell->unsetParam("\\CLR_POLARITY"); - cell->type = "$dff"; + cell->setPort(ID::D, new_d); + cell->setPort(ID::Q, new_q); + cell->unsetPort(ID::SET); + cell->unsetPort(ID::CLR); + cell->unsetParam(ID::SET_POLARITY); + cell->unsetParam(ID::CLR_POLARITY); + cell->type = ID($dff); continue; } - if (cell->type.in("$dlatch")) + if (cell->type.in(ID($dlatch))) { - bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool(); + bool en_pol = cell->parameters[ID::EN_POLARITY].as_bool(); - SigSpec sig_en = cell->getPort("\\EN"); - SigSpec sig_d = cell->getPort("\\D"); - SigSpec sig_q = cell->getPort("\\Q"); + SigSpec sig_en = cell->getPort(ID::EN); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n", log_id(module), log_id(cell), log_id(cell->type), @@ -190,7 +190,7 @@ struct Async2syncPass : public Pass { } Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); - new_q->attributes["\\init"] = init_val; + new_q->attributes[ID::init] = init_val; if (en_pol) { module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q); @@ -198,20 +198,20 @@ struct Async2syncPass : public Pass { module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q); } - cell->setPort("\\D", sig_q); - cell->setPort("\\Q", new_q); - cell->unsetPort("\\EN"); - cell->unsetParam("\\EN_POLARITY"); - cell->type = "$ff"; + cell->setPort(ID::D, sig_q); + cell->setPort(ID::Q, new_q); + cell->unsetPort(ID::EN); + cell->unsetParam(ID::EN_POLARITY); + cell->type = ID($ff); continue; } } for (auto wire : module->wires()) - if (wire->attributes.count("\\init") > 0) + if (wire->attributes.count(ID::init) > 0) { bool delete_initattr = true; - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); SigSpec initsig = sigmap(wire); for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) @@ -221,9 +221,9 @@ struct Async2syncPass : public Pass { delete_initattr = false; if (delete_initattr) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); else - wire->attributes.at("\\init") = initval; + wire->attributes.at(ID::init) = initval; } } } diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index f9e7783a9..1e155e52c 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -60,9 +60,9 @@ struct Clk2fflogicPass : public Pass { pool<SigBit> del_initbits; for (auto wire : module->wires()) - if (wire->attributes.count("\\init") > 0) + if (wire->attributes.count(ID::init) > 0) { - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); SigSpec initsig = sigmap(wire); for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) @@ -72,26 +72,26 @@ struct Clk2fflogicPass : public Pass { for (auto cell : vector<Cell*>(module->selected_cells())) { - if (cell->type.in("$mem")) + if (cell->type.in(ID($mem))) { - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); - int rd_ports = cell->getParam("\\RD_PORTS").as_int(); - int wr_ports = cell->getParam("\\WR_PORTS").as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int rd_ports = cell->getParam(ID::RD_PORTS).as_int(); + int wr_ports = cell->getParam(ID::WR_PORTS).as_int(); for (int i = 0; i < rd_ports; i++) { - if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool()) + if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool()) log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! " "Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module)); } - Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE"); - Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY"); + Const wr_clk_en_param = cell->getParam(ID::WR_CLK_ENABLE); + Const wr_clk_pol_param = cell->getParam(ID::WR_CLK_POLARITY); - SigSpec wr_clk_port = cell->getPort("\\WR_CLK"); - SigSpec wr_en_port = cell->getPort("\\WR_EN"); - SigSpec wr_addr_port = cell->getPort("\\WR_ADDR"); - SigSpec wr_data_port = cell->getPort("\\WR_DATA"); + SigSpec wr_clk_port = cell->getPort(ID::WR_CLK); + SigSpec wr_en_port = cell->getPort(ID::WR_EN); + SigSpec wr_addr_port = cell->getPort(ID::WR_ADDR); + SigSpec wr_data_port = cell->getPort(ID::WR_DATA); for (int wport = 0; wport < wr_ports; wport++) { @@ -111,17 +111,17 @@ struct Clk2fflogicPass : public Pass { log_signal(addr), log_signal(data)); Wire *past_clk = module->addWire(NEW_ID); - past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0; + past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0; module->addFf(NEW_ID, clk, past_clk); SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); @@ -144,22 +144,22 @@ struct Clk2fflogicPass : public Pass { wr_clk_pol_param[wport] = State::S0; } - cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param); - cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param); + cell->setParam(ID::WR_CLK_ENABLE, wr_clk_en_param); + cell->setParam(ID::WR_CLK_POLARITY, wr_clk_pol_param); - cell->setPort("\\WR_CLK", wr_clk_port); - cell->setPort("\\WR_EN", wr_en_port); - cell->setPort("\\WR_ADDR", wr_addr_port); - cell->setPort("\\WR_DATA", wr_data_port); + cell->setPort(ID::WR_CLK, wr_clk_port); + cell->setPort(ID::WR_EN, wr_en_port); + cell->setPort(ID::WR_ADDR, wr_addr_port); + cell->setPort(ID::WR_DATA, wr_data_port); } - if (cell->type.in("$dlatch", "$dlatchsr")) + if (cell->type.in(ID($dlatch), ID($dlatchsr))) { - bool enpol = cell->parameters["\\EN_POLARITY"].as_bool(); + bool enpol = cell->parameters[ID::EN_POLARITY].as_bool(); - SigSpec sig_en = cell->getPort("\\EN"); - SigSpec sig_d = cell->getPort("\\D"); - SigSpec sig_q = cell->getPort("\\Q"); + SigSpec sig_en = cell->getPort(ID::EN); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n", log_id(module), log_id(cell), log_id(cell->type), @@ -168,7 +168,7 @@ struct Clk2fflogicPass : public Pass { Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q)); module->addFf(NEW_ID, sig_q, past_q); - if (cell->type == "$dlatch") + if (cell->type == ID($dlatch)) { if (enpol) module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q); @@ -183,13 +183,13 @@ struct Clk2fflogicPass : public Pass { else t = module->Mux(NEW_ID, sig_d, past_q, sig_en); - SigSpec s = cell->getPort("\\SET"); - if (!cell->parameters["\\SET_POLARITY"].as_bool()) + SigSpec s = cell->getPort(ID::SET); + if (!cell->parameters[ID::SET_POLARITY].as_bool()) s = module->Not(NEW_ID, s); t = module->Or(NEW_ID, t, s); - SigSpec c = cell->getPort("\\CLR"); - if (cell->parameters["\\CLR_POLARITY"].as_bool()) + SigSpec c = cell->getPort(ID::CLR); + if (cell->parameters[ID::CLR_POLARITY].as_bool()) c = module->Not(NEW_ID, c); module->addAnd(NEW_ID, t, c, sig_q); } @@ -208,13 +208,13 @@ struct Clk2fflogicPass : public Pass { } if (assign_initval) - past_q->attributes["\\init"] = initval; + past_q->attributes[ID::init] = initval; module->remove(cell); continue; } - bool word_dff = cell->type.in("$dff", "$adff", "$dffsr"); + bool word_dff = cell->type.in(ID($dff), ID($adff), ID($dffsr)); if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_), @@ -224,8 +224,8 @@ struct Clk2fflogicPass : public Pass { bool clkpol; SigSpec clk; if (word_dff) { - clkpol = cell->parameters["\\CLK_POLARITY"].as_bool(); - clk = cell->getPort("\\CLK"); + clkpol = cell->parameters[ID::CLK_POLARITY].as_bool(); + clk = cell->getPort(ID::CLK); } else { if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_), @@ -236,19 +236,19 @@ struct Clk2fflogicPass : public Pass { ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_))) clkpol = cell->type[8] == 'P'; else log_abort(); - clk = cell->getPort("\\C"); + clk = cell->getPort(ID::C); } Wire *past_clk = module->addWire(NEW_ID); - past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0; + past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0; if (word_dff) module->addFf(NEW_ID, clk, past_clk); else module->addFfGate(NEW_ID, clk, past_clk); - SigSpec sig_d = cell->getPort("\\D"); - SigSpec sig_q = cell->getPort("\\Q"); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n", log_id(module), log_id(cell), log_id(cell->type), @@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); @@ -277,20 +277,20 @@ struct Clk2fflogicPass : public Pass { module->addFfGate(NEW_ID, sig_q, past_q); } - if (cell->type == "$adff") + if (cell->type == ID($adff)) { - SigSpec arst = cell->getPort("\\ARST"); + SigSpec arst = cell->getPort(ID::ARST); SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); - Const rstval = cell->parameters["\\ARST_VALUE"]; + Const rstval = cell->parameters[ID::ARST_VALUE]; Wire *past_arst = module->addWire(NEW_ID); module->addFf(NEW_ID, arst, past_arst); - if (cell->parameters["\\ARST_POLARITY"].as_bool()) + if (cell->parameters[ID::ARST_POLARITY].as_bool()) arst = module->LogicOr(NEW_ID, arst, past_arst); else arst = module->LogicAnd(NEW_ID, arst, past_arst); - if (cell->parameters["\\ARST_POLARITY"].as_bool()) + if (cell->parameters[ID::ARST_POLARITY].as_bool()) module->addMux(NEW_ID, qval, rstval, arst, sig_q); else module->addMux(NEW_ID, rstval, qval, arst, sig_q); @@ -299,7 +299,7 @@ struct Clk2fflogicPass : public Pass { if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_))) { - SigSpec arst = cell->getPort("\\R"); + SigSpec arst = cell->getPort(ID::R); SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge); SigBit rstval = (cell->type[8] == '1'); @@ -316,16 +316,16 @@ struct Clk2fflogicPass : public Pass { module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q); } else - if (cell->type == "$dffsr") + if (cell->type == ID($dffsr)) { SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); - SigSpec setval = cell->getPort("\\SET"); - SigSpec clrval = cell->getPort("\\CLR"); + SigSpec setval = cell->getPort(ID::SET); + SigSpec clrval = cell->getPort(ID::CLR); - if (!cell->parameters["\\SET_POLARITY"].as_bool()) + if (!cell->parameters[ID::SET_POLARITY].as_bool()) setval = module->Not(NEW_ID, setval); - if (cell->parameters["\\CLR_POLARITY"].as_bool()) + if (cell->parameters[ID::CLR_POLARITY].as_bool()) clrval = module->Not(NEW_ID, clrval); qval = module->Or(NEW_ID, qval, setval); @@ -336,8 +336,8 @@ struct Clk2fflogicPass : public Pass { ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_))) { SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge); - SigSpec setval = cell->getPort("\\S"); - SigSpec clrval = cell->getPort("\\R"); + SigSpec setval = cell->getPort(ID::S); + SigSpec clrval = cell->getPort(ID::R); if (cell->type[9] != 'P') setval = module->Not(NEW_ID, setval); @@ -348,7 +348,7 @@ struct Clk2fflogicPass : public Pass { qval = module->OrGate(NEW_ID, qval, setval); module->addAndGate(NEW_ID, qval, clrval, sig_q); } - else if (cell->type == "$dff") + else if (cell->type == ID($dff)) { module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q); } @@ -371,8 +371,8 @@ struct Clk2fflogicPass : public Pass { } if (assign_initval) { - past_d->attributes["\\init"] = initval; - past_q->attributes["\\init"] = initval; + past_d->attributes[ID::init] = initval; + past_q->attributes[ID::init] = initval; } module->remove(cell); @@ -381,10 +381,10 @@ struct Clk2fflogicPass : public Pass { } for (auto wire : module->wires()) - if (wire->attributes.count("\\init") > 0) + if (wire->attributes.count(ID::init) > 0) { bool delete_initattr = true; - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); SigSpec initsig = sigmap(wire); for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) @@ -394,9 +394,9 @@ struct Clk2fflogicPass : public Pass { delete_initattr = false; if (delete_initattr) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); else - wire->attributes.at("\\init") = initval; + wire->attributes.at(ID::init) = initval; } } diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index b4549bc39..26cc69211 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -75,7 +75,7 @@ struct CutpointPass : public Pass { pool<SigBit> cutpoint_bits; for (auto cell : module->selected_cells()) { - if (cell->type == "$anyseq") + if (cell->type == ID($anyseq)) continue; log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell)); for (auto &conn : cell->connections()) { diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index e0bb439f4..f910ea80d 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -88,25 +88,24 @@ struct BruteForceEquivChecker mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1) { log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str()); - for (auto &w : mod1->wires_) + for (auto w : mod1->wires()) { - RTLIL::Wire *wire1 = w.second; - if (wire1->port_id == 0) + if (w->port_id == 0) continue; - if (mod2->wires_.count(wire1->name) == 0) - log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str()); + if (mod2->wire(w->name) == nullptr) + log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str()); - RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name); - if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output) - log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str()); + RTLIL::Wire *w2 = mod2->wire(w->name); + if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output) + log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str()); - if (wire1->port_input) { - mod1_inputs.append(wire1); - mod2_inputs.append(wire2); + if (w->port_input) { + mod1_inputs.append(w); + mod2_inputs.append(w2); } else { - mod1_outputs.append(wire1); - mod2_outputs.append(wire2); + mod1_outputs.append(w); + mod2_outputs.append(w2); } } @@ -148,17 +147,17 @@ struct VlogHammerReporter SatGen satgen(ez.get(), &sigmap); satgen.model_undef = model_undef; - for (auto &c : module->cells_) - if (!satgen.importCell(c.second)) - log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); + for (auto c : module->cells()) + if (!satgen.importCell(c)) + log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type)); ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals)); - std::vector<int> y_vec = satgen.importDefSigSpec(module->wires_.at("\\y")); + std::vector<int> y_vec = satgen.importDefSigSpec(module->wire(ID(y))); std::vector<bool> y_values; if (model_undef) { - std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y")); + std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire(ID(y))); y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end()); } @@ -253,7 +252,7 @@ struct VlogHammerReporter std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width); for (int i = 0; i < int(inputs.size()); i++) { - RTLIL::Wire *wire = module->wires_.at(inputs[i]); + RTLIL::Wire *wire = module->wire(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { ce.set(RTLIL::SigSpec(wire, j), bits.back()); recorded_set_vars.append(RTLIL::SigSpec(wire, j)); @@ -263,21 +262,21 @@ struct VlogHammerReporter if (module == modules.front()) { RTLIL::SigSpec sig(wire); if (!ce.eval(sig)) - log_error("Can't read back value for port %s!\n", RTLIL::id2cstr(inputs[i])); + log_error("Can't read back value for port %s!\n", log_id(inputs[i])); input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str()); - log("++PAT++ %d %s %s #\n", idx, RTLIL::id2cstr(inputs[i]), sig.as_const().as_string().c_str()); + log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str()); } } - if (module->wires_.count("\\y") == 0) - log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name)); + if (module->wire(ID(y)) == nullptr) + log_error("No output wire (y) found in module %s!\n", log_id(module->name)); - RTLIL::SigSpec sig(module->wires_.at("\\y")); + RTLIL::SigSpec sig(module->wire(ID(y))); RTLIL::SigSpec undef; while (!ce.eval(sig, undef)) { - // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); - log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); + // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef)); + log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name)); ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); } @@ -289,7 +288,7 @@ struct VlogHammerReporter sat_check(module, recorded_set_vars, recorded_set_vals, sig, true); } else if (rtl_sig.size() > 0) { if (rtl_sig.size() != sig.size()) - log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); + log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name)); for (int i = 0; i < GetSize(sig); i++) if (rtl_sig[i] == RTLIL::State::Sx) sig[i] = RTLIL::State::Sx; @@ -307,10 +306,10 @@ struct VlogHammerReporter { for (auto name : split(module_list, ",")) { RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name); - if (design->modules_.count(esc_name) == 0) + if (design->module(esc_name) == nullptr) log_error("Can't find module %s in current design!\n", name.c_str()); log("Using module %s (%s).\n", esc_name.c_str(), name.c_str()); - modules.push_back(design->modules_.at(esc_name)); + modules.push_back(design->module(esc_name)); module_names.push_back(name); } @@ -319,11 +318,11 @@ struct VlogHammerReporter int width = -1; RTLIL::IdString esc_name = RTLIL::escape_id(name); for (auto mod : modules) { - if (mod->wires_.count(esc_name) == 0) - log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name)); - RTLIL::Wire *port = mod->wires_.at(esc_name); + if (mod->wire(esc_name) == nullptr) + log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name)); + RTLIL::Wire *port = mod->wire(esc_name); if (!port->port_input || port->port_output) - log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name)); + log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name)); if (width >= 0 && width != port->width) log_error("Port %s has different sizes in the different modules!\n", name.c_str()); width = port->width; @@ -415,11 +414,11 @@ struct EvalPass : public Pass { /* this should only be used for regression testing of ConstEval -- see vloghammer */ std::string mod1_name = RTLIL::escape_id(args[++argidx]); std::string mod2_name = RTLIL::escape_id(args[++argidx]); - if (design->modules_.count(mod1_name) == 0) + if (design->module(mod1_name) == nullptr) log_error("Can't find module `%s'!\n", mod1_name.c_str()); - if (design->modules_.count(mod2_name) == 0) + if (design->module(mod2_name) == nullptr) log_error("Can't find module `%s'!\n", mod2_name.c_str()); - BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); + BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); if (checker.errors > 0) log_cmd_error("Modules are not equivalent!\n"); log("Verified %s = %s (using brute-force check on %d cases).\n", @@ -441,13 +440,12 @@ struct EvalPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) { - if (module) - log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n", - RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first)); - module = mod_it.second; - } + for (auto mod : design->selected_modules()) { + if (module) + log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n", + log_id(module->name), log_id(mod->name)); + module = mod; + } if (module == NULL) log_cmd_error("Can't perform EVAL on an empty selection!\n"); @@ -468,9 +466,9 @@ struct EvalPass : public Pass { } if (shows.size() == 0) { - for (auto &it : module->wires_) - if (it.second->port_output) - shows.push_back(it.second->name.str()); + for (auto w : module->wires()) + if (w->port_output) + shows.push_back(w->name.str()); } if (tables.empty()) diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 29dfc7b19..80ab82cd5 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -53,7 +53,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells, { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; - if (cell->type[0] == '\\' && !design->modules_.count(cell->type)) + if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr)) return false; return true; } @@ -85,27 +85,24 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module) SigMap sigmap(module); SigPool dffsignals; - for (auto &it : module->cells_) { - if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q")) - dffsignals.add(sigmap(it.second->getPort("\\Q"))); + for (auto cell : module->cells()) { + if (ct.cell_known(cell->type) && cell->hasPort(ID::Q)) + dffsignals.add(sigmap(cell->getPort(ID::Q))); } - for (auto &it : module->wires_) { - if (dffsignals.check_any(it.second)) - dff_wires.insert(it.first); + for (auto w : module->wires()) { + if (dffsignals.check_any(w)) + dff_wires.insert(w->name); } } -void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module) +void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Module *module) { std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info; SigMap sigmap(module); - for (auto &it : module->cells_) + for (auto cell : module->selected_cells()) { - if (!design->selected(module, it.second)) - continue; - dff_map_bit_info_t info; info.bit_d = RTLIL::State::Sm; info.bit_clk = RTLIL::State::Sm; @@ -113,13 +110,13 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De info.clk_polarity = false; info.arst_polarity = false; info.arst_value = RTLIL::State::Sm; - info.cell = it.second; + info.cell = cell; - if (info.cell->type == "$dff") { - info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit(); - info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); - std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector(); - std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector(); + if (info.cell->type == ID($dff)) { + info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit(); + info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool(); + std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); bit_info[sig_q.at(i)] = info; @@ -127,14 +124,14 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De continue; } - if (info.cell->type == "$adff") { - info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit(); - info.bit_arst = sigmap(info.cell->getPort("\\ARST")).as_bit(); - info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); - info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool(); - std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector(); - std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector(); - std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits; + if (info.cell->type == ID($adff)) { + info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit(); + info.bit_arst = sigmap(info.cell->getPort(ID::ARST)).as_bit(); + info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool(); + info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool(); + std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector(); + std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits; for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); info.arst_value = arst_value.at(i); @@ -143,33 +140,33 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De continue; } - if (info.cell->type.in("$_DFF_N_", "$_DFF_P_")) { - info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit(); - info.clk_polarity = info.cell->type == "$_DFF_P_"; - info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit(); - bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info; + if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { + info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit(); + info.clk_polarity = info.cell->type == ID($_DFF_P_); + info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit(); + bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info; continue; } if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) { - info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit(); - info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit(); + info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit(); + info.bit_arst = sigmap(info.cell->getPort(ID::R)).as_bit(); info.clk_polarity = info.cell->type[6] == 'P'; info.arst_polarity = info.cell->type[7] == 'P'; info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0; - info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit(); - bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info; + info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit(); + bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info; continue; } } std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map; - for (auto &it : module->wires_) + for (auto w : module->wires()) { - if (!consider_wire(it.second, empty_dq_map)) + if (!consider_wire(w, empty_dq_map)) continue; - std::vector<RTLIL::SigBit> bits_q = sigmap(it.second).to_sigbit_vector(); + std::vector<RTLIL::SigBit> bits_q = sigmap(w).to_sigbit_vector(); std::vector<RTLIL::SigBit> bits_d; std::vector<RTLIL::State> arst_value; std::set<RTLIL::Cell*> cells; @@ -207,7 +204,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De info.arst_value = arst_value; for (auto it : cells) info.cells.push_back(it->name); - map[it.first] = info; + map[w->name] = info; } } @@ -314,26 +311,23 @@ struct ExposePass : public Pass { RTLIL::Module *first_module = NULL; std::set<RTLIL::IdString> shared_dff_wires; - for (auto &mod_it : design->modules_) + for (auto mod : design->selected_modules()) { - if (!design->selected(mod_it.second)) - continue; - - create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second); + create_dff_dq_map(dff_dq_maps[mod], mod); if (!flag_shared) continue; if (first_module == NULL) { - for (auto &it : dff_dq_maps[mod_it.second]) + for (auto &it : dff_dq_maps[mod]) shared_dff_wires.insert(it.first); - first_module = mod_it.second; + first_module = mod; } else { std::set<RTLIL::IdString> new_shared_dff_wires; for (auto &it : shared_dff_wires) { - if (!dff_dq_maps[mod_it.second].count(it)) + if (!dff_dq_maps[mod].count(it)) continue; - if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it))) + if (!compare_wires(first_module->wire(it), mod->wire(it))) continue; new_shared_dff_wires.insert(it); } @@ -364,28 +358,23 @@ struct ExposePass : public Pass { { RTLIL::Module *first_module = NULL; - for (auto &mod_it : design->modules_) + for (auto module : design->selected_modules()) { - RTLIL::Module *module = mod_it.second; - - if (!design->selected(module)) - continue; - std::set<RTLIL::IdString> dff_wires; if (flag_dff) find_dff_wires(dff_wires, module); if (first_module == NULL) { - for (auto &it : module->wires_) - if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module])) - if (!flag_dff || dff_wires.count(it.first)) - shared_wires.insert(it.first); + for (auto w : module->wires()) + if (design->selected(module, w) && consider_wire(w, dff_dq_maps[module])) + if (!flag_dff || dff_wires.count(w->name)) + shared_wires.insert(w->name); if (flag_evert) - for (auto &it : module->cells_) - if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second)) - shared_cells.insert(it.first); + for (auto cell : module->cells()) + if (design->selected(module, cell) && consider_cell(design, dff_cells[module], cell)) + shared_cells.insert(cell->name); first_module = module; } @@ -397,16 +386,16 @@ struct ExposePass : public Pass { { RTLIL::Wire *wire; - if (module->wires_.count(it) == 0) + if (module->wire(it) == nullptr) goto delete_shared_wire; - wire = module->wires_.at(it); + wire = module->wire(it); if (!design->selected(module, wire)) goto delete_shared_wire; if (!consider_wire(wire, dff_dq_maps[module])) goto delete_shared_wire; - if (!compare_wires(first_module->wires_.at(it), wire)) + if (!compare_wires(first_module->wire(it), wire)) goto delete_shared_wire; if (flag_dff && !dff_wires.count(it)) goto delete_shared_wire; @@ -421,16 +410,16 @@ struct ExposePass : public Pass { { RTLIL::Cell *cell; - if (module->cells_.count(it) == 0) + if (module->cell(it) == nullptr) goto delete_shared_cell; - cell = module->cells_.at(it); + cell = module->cell(it); if (!design->selected(module, cell)) goto delete_shared_cell; if (!consider_cell(design, dff_cells[module], cell)) goto delete_shared_cell; - if (!compare_cells(first_module->cells_.at(it), cell)) + if (!compare_cells(first_module->cell(it), cell)) goto delete_shared_cell; if (0) @@ -446,13 +435,8 @@ struct ExposePass : public Pass { } } - for (auto &mod_it : design->modules_) + for (auto module : design->selected_modules()) { - RTLIL::Module *module = mod_it.second; - - if (!design->selected(module)) - continue; - std::set<RTLIL::IdString> dff_wires; if (flag_dff && !flag_shared) find_dff_wires(dff_wires, module); @@ -461,49 +445,49 @@ struct ExposePass : public Pass { SigMap out_to_in_map; - for (auto &it : module->wires_) + for (auto w : module->wires()) { if (flag_shared) { - if (shared_wires.count(it.first) == 0) + if (shared_wires.count(w->name) == 0) continue; } else { - if (!design->selected(module, it.second) || !consider_wire(it.second, dff_dq_maps[module])) + if (!design->selected(module, w) || !consider_wire(w, dff_dq_maps[module])) continue; - if (flag_dff && !dff_wires.count(it.first)) + if (flag_dff && !dff_wires.count(w->name)) continue; } if (flag_input) { - if (!it.second->port_input) { - it.second->port_input = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); - RTLIL::Wire *w = module->addWire(NEW_ID, GetSize(it.second)); - out_to_in_map.add(it.second, w); + if (!w->port_input) { + w->port_input = true; + log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w)); + out_to_in_map.add(w, in_wire); } } else { - if (!it.second->port_output) { - it.second->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); + if (!w->port_output) { + w->port_output = true; + log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); } if (flag_cut) { - RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width); + RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width); in_wire->port_input = true; - out_to_in_map.add(sigmap(it.second), in_wire); + out_to_in_map.add(sigmap(w), in_wire); } } } if (flag_input) { - for (auto &it : module->cells_) { - if (!ct.cell_known(it.second->type)) + for (auto cell : module->cells()) { + if (!ct.cell_known(cell->type)) continue; - for (auto &conn : it.second->connections_) - if (ct.cell_output(it.second->type, conn.first)) + for (auto &conn : cell->connections_) + if (ct.cell_output(cell->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); } @@ -513,11 +497,11 @@ struct ExposePass : public Pass { if (flag_cut) { - for (auto &it : module->cells_) { - if (!ct.cell_known(it.second->type)) + for (auto cell : module->cells()) { + if (!ct.cell_known(cell->type)) continue; - for (auto &conn : it.second->connections_) - if (ct.cell_input(it.second->type, conn.first)) + for (auto &conn : cell->connections_) + if (ct.cell_input(cell->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); } @@ -529,10 +513,10 @@ struct ExposePass : public Pass { for (auto &dq : dff_dq_maps[module]) { - if (!module->wires_.count(dq.first)) + if (module->wire(dq.first) == nullptr) continue; - RTLIL::Wire *wire = module->wires_.at(dq.first); + RTLIL::Wire *wire = module->wire(dq.first); std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set(); std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector(); @@ -541,12 +525,12 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0); for (auto &cell_name : info.cells) { - RTLIL::Cell *cell = module->cells_.at(cell_name); - std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector(); + RTLIL::Cell *cell = module->cell(cell_name); + std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort(ID::Q)).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->setPort("\\Q", cell_q_bits); + cell->setPort(ID::Q, cell_q_bits); } RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width); @@ -574,12 +558,12 @@ struct ExposePass : public Pass { if (info.clk_polarity) { module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { - RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); - c->parameters["\\A_SIGNED"] = 0; - c->parameters["\\A_WIDTH"] = 1; - c->parameters["\\Y_WIDTH"] = 1; - c->setPort("\\A", info.sig_clk); - c->setPort("\\Y", wire_c); + RTLIL::Cell *c = module->addCell(NEW_ID, ID($not)); + c->parameters[ID::A_SIGNED] = 0; + c->parameters[ID::A_WIDTH] = 1; + c->parameters[ID::Y_WIDTH] = 1; + c->setPort(ID::A, info.sig_clk); + c->setPort(ID::Y, wire_c); } if (info.sig_arst != RTLIL::State::Sm) @@ -590,12 +574,12 @@ struct ExposePass : public Pass { if (info.arst_polarity) { module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { - RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); - c->parameters["\\A_SIGNED"] = 0; - c->parameters["\\A_WIDTH"] = 1; - c->parameters["\\Y_WIDTH"] = 1; - c->setPort("\\A", info.sig_arst); - c->setPort("\\Y", wire_r); + RTLIL::Cell *c = module->addCell(NEW_ID, ID($not)); + c->parameters[ID::A_SIGNED] = 0; + c->parameters[ID::A_WIDTH] = 1; + c->parameters[ID::Y_WIDTH] = 1; + c->setPort(ID::A, info.sig_arst); + c->setPort(ID::Y, wire_r); } RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); @@ -609,25 +593,22 @@ struct ExposePass : public Pass { { std::vector<RTLIL::Cell*> delete_cells; - for (auto &it : module->cells_) + for (auto cell : module->cells()) { if (flag_shared) { - if (shared_cells.count(it.first) == 0) + if (shared_cells.count(cell->name) == 0) continue; } else { - if (!design->selected(module, it.second) || !consider_cell(design, dff_cells[module], it.second)) + if (!design->selected(module, cell) || !consider_cell(design, dff_cells[module], cell)) continue; } - RTLIL::Cell *cell = it.second; - - if (design->modules_.count(cell->type)) + if (design->module(cell->type) != nullptr) { - RTLIL::Module *mod = design->modules_.at(cell->type); + RTLIL::Module *mod = design->module(cell->type); - for (auto &it : mod->wires_) + for (auto p : mod->wires()) { - RTLIL::Wire *p = it.second; if (!p->port_input && !p->port_output) continue; diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 00c098542..5066485aa 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -43,7 +43,7 @@ struct FmcombineWorker FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) : opts(opts), design(design), original(design->module(orig_type)), - orig_type(orig_type), combined_type("$fmcombine" + orig_type.str()) + orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type.c_str())) { } @@ -106,7 +106,7 @@ struct FmcombineWorker for (auto cell : original->cells()) { if (design->module(cell->type) == nullptr) { - if (opts.anyeq && cell->type.in("$anyseq", "$anyconst")) { + if (opts.anyeq && cell->type.in(ID($anyseq), ID($anyconst))) { Cell *gold = import_prim_cell(cell, "_gold"); for (auto &conn : cell->connections()) module->connect(import_sig(conn.second, "_gate"), gold->getPort(conn.first)); @@ -114,10 +114,10 @@ struct FmcombineWorker Cell *gold = import_prim_cell(cell, "_gold"); Cell *gate = import_prim_cell(cell, "_gate"); if (opts.initeq) { - if (cell->type.in("$ff", "$dff", "$dffe", - "$dffsr", "$adff", "$dlatch", "$dlatchsr")) { - SigSpec gold_q = gold->getPort("\\Q"); - SigSpec gate_q = gate->getPort("\\Q"); + if (cell->type.in(ID($ff), ID($dff), ID($dffe), + ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr))) { + SigSpec gold_q = gold->getPort(ID::Q); + SigSpec gate_q = gate->getPort(ID::Q); SigSpec en = module->Initstate(NEW_ID); SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q); module->addAssume(NEW_ID, eq, en); @@ -359,7 +359,7 @@ struct FmcombinePass : public Pass { Cell *cell = module->addCell(combined_cell_name, worker.combined_type); cell->attributes = gold_cell->attributes; - cell->add_strpool_attribute("\\src", gate_cell->get_strpool_attribute("\\src")); + cell->add_strpool_attribute(ID::src, gate_cell->get_strpool_attribute(ID::src)); log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell)); diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index f3f00b382..555a28dc6 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -147,7 +147,7 @@ struct FminitPass : public Pass { SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0; Wire *outwire = module->addWire(NEW_ID); - outwire->attributes[ID(init)] = i > 0 ? State::S0 : State::S1; + outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1; if (clksig.empty()) module->addFf(NEW_ID, insig, outwire); @@ -161,7 +161,7 @@ struct FminitPass : public Pass { if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty()) { Wire *ffwire = module->addWire(NEW_ID); - ffwire->attributes[ID(init)] = State::S0; + ffwire->attributes[ID::init] = State::S0; SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]); if (clksig.empty()) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index f29631639..5dfd7bd3f 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -614,29 +614,29 @@ struct FreduceWorker int bits_full_total = 0; std::vector<std::set<RTLIL::SigBit>> batches; - for (auto &it : module->wires_) - if (it.second->port_input) { - batches.push_back(sigmap(it.second).to_sigbit_set()); - bits_full_total += it.second->width; + for (auto w : module->wires()) + if (w->port_input) { + batches.push_back(sigmap(w).to_sigbit_set()); + bits_full_total += w->width; } - for (auto &it : module->cells_) { - if (ct.cell_known(it.second->type)) { + for (auto cell : module->cells()) { + if (ct.cell_known(cell->type)) { std::set<RTLIL::SigBit> inputs, outputs; - for (auto &port : it.second->connections()) { + for (auto &port : cell->connections()) { std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector(); - if (ct.cell_output(it.second->type, port.first)) + if (ct.cell_output(cell->type, port.first)) outputs.insert(bits.begin(), bits.end()); else inputs.insert(bits.begin(), bits.end()); } - std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs); + std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs); for (auto &bit : outputs) drivers[bit] = drv; batches.push_back(outputs); bits_full_total += outputs.size(); } - if (inv_mode && it.second->type == "$_NOT_") - inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y")))); + if (inv_mode && cell->type == ID($_NOT_)) + inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y)))); } int bits_count = 0; @@ -731,9 +731,9 @@ struct FreduceWorker { inv_sig = module->addWire(NEW_ID); - RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_"); - inv_cell->setPort("\\A", grp[0].bit); - inv_cell->setPort("\\Y", inv_sig); + RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_)); + inv_cell->setPort(ID::A, grp[0].bit); + inv_cell->setPort(ID::Y, inv_sig); } module->connect(RTLIL::SigSig(grp[i].bit, inv_sig)); @@ -828,10 +828,8 @@ struct FreducePass : public Pass { extra_args(args, argidx, design); int bitcount = 0; - for (auto &mod_it : design->modules_) { - RTLIL::Module *module = mod_it.second; - if (design->selected(module)) - bitcount += FreduceWorker(design, module).run(); + for (auto module : design->selected_modules()) { + bitcount += FreduceWorker(design, module).run(); } log("Rewired a total of %d signal bits.\n", bitcount); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 49ef40061..aeece9b94 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -66,50 +66,48 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]); RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]); - if (design->modules_.count(gold_name) == 0) + if (design->module(gold_name) == nullptr) log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); - if (design->modules_.count(gate_name) == 0) + if (design->module(gate_name) == nullptr) log_cmd_error("Can't find gate module %s!\n", gate_name.c_str()); - if (design->modules_.count(miter_name) != 0) + if (design->module(miter_name) != nullptr) log_cmd_error("There is already a module %s!\n", miter_name.c_str()); - RTLIL::Module *gold_module = design->modules_.at(gold_name); - RTLIL::Module *gate_module = design->modules_.at(gate_name); + RTLIL::Module *gold_module = design->module(gold_name); + RTLIL::Module *gate_module = design->module(gate_name); - for (auto &it : gold_module->wires_) { - RTLIL::Wire *w1 = it.second, *w2; - if (w1->port_id == 0) + for (auto gold_wire : gold_module->wires()) { + if (gold_wire->port_id == 0) continue; - if (gate_module->wires_.count(it.second->name) == 0) + RTLIL::Wire *gate_wire = gate_module->wire(gold_wire->name); + if (gate_wire == nullptr) goto match_gold_port_error; - w2 = gate_module->wires_.at(it.second->name); - if (w1->port_input != w2->port_input) + if (gold_wire->port_input != gate_wire->port_input) goto match_gold_port_error; - if (w1->port_output != w2->port_output) + if (gold_wire->port_output != gate_wire->port_output) goto match_gold_port_error; - if (w1->width != w2->width) + if (gold_wire->width != gate_wire->width) goto match_gold_port_error; continue; match_gold_port_error: - log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str()); + log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str()); } - for (auto &it : gate_module->wires_) { - RTLIL::Wire *w1 = it.second, *w2; - if (w1->port_id == 0) + for (auto gate_wire : gate_module->wires()) { + if (gate_wire->port_id == 0) continue; - if (gold_module->wires_.count(it.second->name) == 0) + RTLIL::Wire *gold_wire = gold_module->wire(gate_wire->name); + if (gold_wire == nullptr) goto match_gate_port_error; - w2 = gold_module->wires_.at(it.second->name); - if (w1->port_input != w2->port_input) + if (gate_wire->port_input != gold_wire->port_input) goto match_gate_port_error; - if (w1->port_output != w2->port_output) + if (gate_wire->port_output != gold_wire->port_output) goto match_gate_port_error; - if (w1->width != w2->width) + if (gate_wire->width != gold_wire->width) goto match_gate_port_error; continue; match_gate_port_error: - log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str()); + log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str()); } log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); @@ -118,103 +116,101 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: miter_module->name = miter_name; design->add(miter_module); - RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name); - RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name); + RTLIL::Cell *gold_cell = miter_module->addCell(ID(gold), gold_name); + RTLIL::Cell *gate_cell = miter_module->addCell(ID(gate), gate_name); RTLIL::SigSpec all_conditions; - for (auto &it : gold_module->wires_) + for (auto gold_wire : gold_module->wires()) { - RTLIL::Wire *w1 = it.second; - - if (w1->port_input) + if (gold_wire->port_input) { - RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width); - w2->port_input = true; + RTLIL::Wire *w = miter_module->addWire("\\in_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + w->port_input = true; - gold_cell->setPort(w1->name, w2); - gate_cell->setPort(w1->name, w2); + gold_cell->setPort(gold_wire->name, w); + gate_cell->setPort(gold_wire->name, w); } - if (w1->port_output) + if (gold_wire->port_output) { - RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width); - w2_gold->port_output = flag_make_outputs; + RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + w_gold->port_output = flag_make_outputs; - RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width); - w2_gate->port_output = flag_make_outputs; + RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + w_gate->port_output = flag_make_outputs; - gold_cell->setPort(w1->name, w2_gold); - gate_cell->setPort(w1->name, w2_gate); + gold_cell->setPort(gold_wire->name, w_gold); + gate_cell->setPort(gold_wire->name, w_gate); RTLIL::SigSpec this_condition; if (flag_ignore_gold_x) { - RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width); - for (int i = 0; i < w2_gold->width; i++) { - RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx"); - eqx_cell->parameters["\\A_WIDTH"] = 1; - eqx_cell->parameters["\\B_WIDTH"] = 1; - eqx_cell->parameters["\\Y_WIDTH"] = 1; - eqx_cell->parameters["\\A_SIGNED"] = 0; - eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i)); - eqx_cell->setPort("\\B", RTLIL::State::Sx); - eqx_cell->setPort("\\Y", gold_x.extract(i, 1)); + RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width); + for (int i = 0; i < w_gold->width; i++) { + RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx)); + eqx_cell->parameters[ID::A_WIDTH] = 1; + eqx_cell->parameters[ID::B_WIDTH] = 1; + eqx_cell->parameters[ID::Y_WIDTH] = 1; + eqx_cell->parameters[ID::A_SIGNED] = 0; + eqx_cell->parameters[ID::B_SIGNED] = 0; + eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i)); + eqx_cell->setPort(ID::B, RTLIL::State::Sx); + eqx_cell->setPort(ID::Y, gold_x.extract(i, 1)); } - RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); - RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width); - - RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or"); - or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width; - or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width; - or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width; - or_gold_cell->parameters["\\A_SIGNED"] = 0; - or_gold_cell->parameters["\\B_SIGNED"] = 0; - or_gold_cell->setPort("\\A", w2_gold); - or_gold_cell->setPort("\\B", gold_x); - or_gold_cell->setPort("\\Y", gold_masked); - - RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); - or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width; - or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width; - or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width; - or_gate_cell->parameters["\\A_SIGNED"] = 0; - or_gate_cell->parameters["\\B_SIGNED"] = 0; - or_gate_cell->setPort("\\A", w2_gate); - or_gate_cell->setPort("\\B", gold_x); - or_gate_cell->setPort("\\Y", gate_masked); - - RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); - eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; - eq_cell->parameters["\\B_WIDTH"] = w2_gate->width; - eq_cell->parameters["\\Y_WIDTH"] = 1; - eq_cell->parameters["\\A_SIGNED"] = 0; - eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->setPort("\\A", gold_masked); - eq_cell->setPort("\\B", gate_masked); - eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); - this_condition = eq_cell->getPort("\\Y"); + RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width); + RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width); + + RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or)); + or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width; + or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width; + or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width; + or_gold_cell->parameters[ID::A_SIGNED] = 0; + or_gold_cell->parameters[ID::B_SIGNED] = 0; + or_gold_cell->setPort(ID::A, w_gold); + or_gold_cell->setPort(ID::B, gold_x); + or_gold_cell->setPort(ID::Y, gold_masked); + + RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or)); + or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width; + or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width; + or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width; + or_gate_cell->parameters[ID::A_SIGNED] = 0; + or_gate_cell->parameters[ID::B_SIGNED] = 0; + or_gate_cell->setPort(ID::A, w_gate); + or_gate_cell->setPort(ID::B, gold_x); + or_gate_cell->setPort(ID::Y, gate_masked); + + RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx)); + eq_cell->parameters[ID::A_WIDTH] = w_gold->width; + eq_cell->parameters[ID::B_WIDTH] = w_gate->width; + eq_cell->parameters[ID::Y_WIDTH] = 1; + eq_cell->parameters[ID::A_SIGNED] = 0; + eq_cell->parameters[ID::B_SIGNED] = 0; + eq_cell->setPort(ID::A, gold_masked); + eq_cell->setPort(ID::B, gate_masked); + eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + this_condition = eq_cell->getPort(ID::Y); } else { - RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); - eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; - eq_cell->parameters["\\B_WIDTH"] = w2_gate->width; - eq_cell->parameters["\\Y_WIDTH"] = 1; - eq_cell->parameters["\\A_SIGNED"] = 0; - eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->setPort("\\A", w2_gold); - eq_cell->setPort("\\B", w2_gate); - eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); - this_condition = eq_cell->getPort("\\Y"); + RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx)); + eq_cell->parameters[ID::A_WIDTH] = w_gold->width; + eq_cell->parameters[ID::B_WIDTH] = w_gate->width; + eq_cell->parameters[ID::Y_WIDTH] = 1; + eq_cell->parameters[ID::A_SIGNED] = 0; + eq_cell->parameters[ID::B_SIGNED] = 0; + eq_cell->setPort(ID::A, w_gold); + eq_cell->setPort(ID::B, w_gate); + eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + this_condition = eq_cell->getPort(ID::Y); } if (flag_make_outcmp) { - RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name)); + RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(gold_wire->name)); w_cmp->port_output = true; miter_module->connect(RTLIL::SigSig(w_cmp, this_condition)); } @@ -224,31 +220,31 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: } if (all_conditions.size() != 1) { - RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and"); - reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); - reduce_cell->parameters["\\Y_WIDTH"] = 1; - reduce_cell->parameters["\\A_SIGNED"] = 0; - reduce_cell->setPort("\\A", all_conditions); - reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); - all_conditions = reduce_cell->getPort("\\Y"); + RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and)); + reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size(); + reduce_cell->parameters[ID::Y_WIDTH] = 1; + reduce_cell->parameters[ID::A_SIGNED] = 0; + reduce_cell->setPort(ID::A, all_conditions); + reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID)); + all_conditions = reduce_cell->getPort(ID::Y); } if (flag_make_assert) { - RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); - assert_cell->setPort("\\A", all_conditions); - assert_cell->setPort("\\EN", State::S1); + RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert)); + assert_cell->setPort(ID::A, all_conditions); + assert_cell->setPort(ID::EN, State::S1); } - RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger"); + RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger)); w_trigger->port_output = true; - RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not"); - not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); - not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); - not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; - not_cell->parameters["\\A_SIGNED"] = 0; - not_cell->setPort("\\A", all_conditions); - not_cell->setPort("\\Y", w_trigger); + RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not)); + not_cell->parameters[ID::A_WIDTH] = all_conditions.size(); + not_cell->parameters[ID::A_WIDTH] = all_conditions.size(); + not_cell->parameters[ID::Y_WIDTH] = w_trigger->width; + not_cell->parameters[ID::A_SIGNED] = 0; + not_cell->setPort(ID::A, all_conditions); + not_cell->setPort(ID::Y, w_trigger); miter_module->fixup_ports(); @@ -285,9 +281,9 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL IdString module_name = RTLIL::escape_id(args[argidx++]); IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : ""; - if (design->modules_.count(module_name) == 0) + if (design->module(module_name) == nullptr) log_cmd_error("Can't find module %s!\n", module_name.c_str()); - if (!miter_name.empty() && design->modules_.count(miter_name) != 0) + if (!miter_name.empty() && design->module(miter_name) != nullptr) log_cmd_error("There is already a module %s!\n", miter_name.c_str()); Module *module = design->module(module_name); @@ -302,7 +298,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL for (auto wire : module->wires()) wire->port_output = false; - Wire *trigger = module->addWire("\\trigger"); + Wire *trigger = module->addWire(ID(trigger)); trigger->port_output = true; module->fixup_ports(); @@ -316,13 +312,13 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL vector<Cell*> cell_list = module->cells(); for (auto cell : cell_list) { - if (!cell->type.in("$assert", "$assume")) + if (!cell->type.in(ID($assert), ID($assume))) continue; - SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1); - SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1); + SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1); + SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1); - if (cell->type == "$assert") { + if (cell->type == ID($assert)) { assert_signals.append(module->And(NEW_ID, is_active, is_enabled)); } else { assume_signals.append(module->And(NEW_ID, is_active, is_enabled)); @@ -338,7 +334,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL else { Wire *assume_q = module->addWire(NEW_ID); - assume_q->attributes["\\init"] = State::S0; + assume_q->attributes[ID::init] = State::S0; assume_signals.append(assume_q); SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals); diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index b53bbfeb2..af8ffca9e 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -439,7 +439,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena dict<SigBit, int> bit_user_cnt; for (auto wire : module->wires()) { - if (wire->name[0] == '\\' && wire->attributes.count("\\src")) + if (wire->name[0] == '\\' && wire->attributes.count(ID::src)) sigmap.add(wire); } @@ -489,12 +489,12 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena entry.port = conn.first; entry.portbit = i; - for (auto &s : cell->get_strpool_attribute("\\src")) + for (auto &s : cell->get_strpool_attribute(ID::src)) entry.src.insert(s); SigBit bit = sigmap(conn.second[i]); if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) { - for (auto &s : bit.wire->get_strpool_attribute("\\src")) + for (auto &s : bit.wire->get_strpool_attribute(ID::src)) entry.src.insert(s); entry.wire = bit.wire->name; entry.wirebit = bit.offset; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 436ac1b01..6acdbc800 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -258,11 +258,11 @@ struct SatHelper for (auto &it : module->wires_) { - if (it.second->attributes.count("\\init") == 0) + if (it.second->attributes.count(ID::init) == 0) continue; RTLIL::SigSpec lhs = sigmap(it.second); - RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); + RTLIL::SigSpec rhs = it.second->attributes.at(ID::init); log_assert(lhs.size() == rhs.size()); RTLIL::SigSpec removed_bits; @@ -518,9 +518,9 @@ struct SatHelper } else { for (auto &d : drivers) for (auto &p : d->connections()) { - if (d->type == "$dff" && p.first == "\\CLK") + if (d->type == ID($dff) && p.first == ID::CLK) continue; - if (d->type.begins_with("$_DFF_") && p.first == "\\C") + if (d->type.begins_with("$_DFF_") && p.first == ID::C) continue; queued_signals.add(handled_signals.remove(sigmap(p.second))); } @@ -675,9 +675,9 @@ struct SatHelper strftime(stime, sizeof(stime), "%c", now); std::string module_fname = "unknown"; - auto apos = module->attributes.find("\\src"); + auto apos = module->attributes.find(ID::src); if(apos != module->attributes.end()) - module_fname = module->attributes["\\src"].decode_string(); + module_fname = module->attributes[ID::src].decode_string(); fprintf(f, "$date\n"); fprintf(f, " %s\n", stime); @@ -1354,8 +1354,8 @@ struct SatPass : public Pass { if (show_regs) { pool<Wire*> reg_wires; for (auto cell : module->cells()) { - if (cell->type == "$dff" || cell->type.begins_with("$_DFF_")) - for (auto bit : cell->getPort("\\Q")) + if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_")) + for (auto bit : cell->getPort(ID::Q)) if (bit.wire) reg_wires.insert(bit.wire); } diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index d5634b26d..59bf5a712 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -108,8 +108,8 @@ struct SimInstance } } - if (wire->attributes.count("\\init")) { - Const initval = wire->attributes.at("\\init"); + if (wire->attributes.count(ID::init)) { + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++) if (initval[i] == State::S0 || initval[i] == State::S1) { state_nets[sig[i]] = initval[i]; @@ -132,24 +132,24 @@ struct SimInstance upd_cells[bit].insert(cell); } - if (cell->type.in("$dff")) { + if (cell->type.in(ID($dff))) { ff_state_t ff; ff.past_clock = State::Sx; - ff.past_d = Const(State::Sx, cell->getParam("\\WIDTH").as_int()); + ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int()); ff_database[cell] = ff; } - if (cell->type == "$mem") + if (cell->type == ID($mem)) { mem_state_t mem; - mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort("\\WR_CLK"))); - mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort("\\WR_EN"))); - mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort("\\WR_ADDR"))); - mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort("\\WR_DATA"))); + mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort(ID::WR_CLK))); + mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort(ID::WR_EN))); + mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort(ID::WR_ADDR))); + mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort(ID::WR_DATA))); - mem.data = cell->getParam("\\INIT"); - int sz = cell->getParam("\\SIZE").as_int() * cell->getParam("\\WIDTH").as_int(); + mem.data = cell->getParam(ID::INIT); + int sz = cell->getParam(ID::SIZE).as_int() * cell->getParam(ID::WIDTH).as_int(); if (GetSize(mem.data) > sz) mem.data.bits.resize(sz); @@ -160,7 +160,7 @@ struct SimInstance mem_database[cell] = mem; } - if (cell->type.in("$assert", "$cover", "$assume")) { + if (cell->type.in(ID($assert), ID($cover), ID($assume))) { formal_database.insert(cell); } } @@ -173,7 +173,7 @@ struct SimInstance ff_state_t &ff = it.second; zinit(ff.past_d); - SigSpec qsig = cell->getPort("\\Q"); + SigSpec qsig = cell->getPort(ID::Q); Const qdata = get_state(qsig); zinit(qdata); set_state(qsig, qdata); @@ -256,18 +256,18 @@ struct SimInstance { mem_state_t &mem = mem_database.at(cell); - int num_rd_ports = cell->getParam("\\RD_PORTS").as_int(); + int num_rd_ports = cell->getParam(ID::RD_PORTS).as_int(); - int size = cell->getParam("\\SIZE").as_int(); - int offset = cell->getParam("\\OFFSET").as_int(); - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); + int size = cell->getParam(ID::SIZE).as_int(); + int offset = cell->getParam(ID::OFFSET).as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); - if (cell->getParam("\\RD_CLK_ENABLE").as_bool()) + if (cell->getParam(ID::RD_CLK_ENABLE).as_bool()) log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(cell)); - SigSpec rd_addr_sig = cell->getPort("\\RD_ADDR"); - SigSpec rd_data_sig = cell->getPort("\\RD_DATA"); + SigSpec rd_addr_sig = cell->getPort(ID::RD_ADDR); + SigSpec rd_data_sig = cell->getPort(ID::RD_DATA); for (int port_idx = 0; port_idx < num_rd_ports; port_idx++) { @@ -303,19 +303,19 @@ struct SimInstance RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y; bool has_a, has_b, has_c, has_d, has_s, has_y; - has_a = cell->hasPort("\\A"); - has_b = cell->hasPort("\\B"); - has_c = cell->hasPort("\\C"); - has_d = cell->hasPort("\\D"); - has_s = cell->hasPort("\\S"); - has_y = cell->hasPort("\\Y"); + has_a = cell->hasPort(ID::A); + has_b = cell->hasPort(ID::B); + has_c = cell->hasPort(ID::C); + has_d = cell->hasPort(ID::D); + has_s = cell->hasPort(ID::S); + has_y = cell->hasPort(ID::Y); - if (has_a) sig_a = cell->getPort("\\A"); - if (has_b) sig_b = cell->getPort("\\B"); - if (has_c) sig_c = cell->getPort("\\C"); - if (has_d) sig_d = cell->getPort("\\D"); - if (has_s) sig_s = cell->getPort("\\S"); - if (has_y) sig_y = cell->getPort("\\Y"); + if (has_a) sig_a = cell->getPort(ID::A); + if (has_b) sig_b = cell->getPort(ID::B); + if (has_c) sig_c = cell->getPort(ID::C); + if (has_d) sig_d = cell->getPort(ID::D); + if (has_s) sig_s = cell->getPort(ID::S); + if (has_y) sig_y = cell->getPort(ID::Y); if (shared->debug) log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type)); @@ -403,16 +403,16 @@ struct SimInstance Cell *cell = it.first; ff_state_t &ff = it.second; - if (cell->type.in("$dff")) + if (cell->type.in(ID($dff))) { - bool clkpol = cell->getParam("\\CLK_POLARITY").as_bool(); - State current_clock = get_state(cell->getPort("\\CLK"))[0]; + bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool(); + State current_clock = get_state(cell->getPort(ID::CLK))[0]; if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) : (ff.past_clock == State::S0 || current_clock != State::S0)) continue; - if (set_state(cell->getPort("\\Q"), ff.past_d)) + if (set_state(cell->getPort(ID::Q), ff.past_d)) did_something = true; } } @@ -422,16 +422,16 @@ struct SimInstance Cell *cell = it.first; mem_state_t &mem = it.second; - int num_wr_ports = cell->getParam("\\WR_PORTS").as_int(); + int num_wr_ports = cell->getParam(ID::WR_PORTS).as_int(); - int size = cell->getParam("\\SIZE").as_int(); - int offset = cell->getParam("\\OFFSET").as_int(); - int abits = cell->getParam("\\ABITS").as_int(); - int width = cell->getParam("\\WIDTH").as_int(); + int size = cell->getParam(ID::SIZE).as_int(); + int offset = cell->getParam(ID::OFFSET).as_int(); + int abits = cell->getParam(ID::ABITS).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); - Const wr_clk_enable = cell->getParam("\\WR_CLK_ENABLE"); - Const wr_clk_polarity = cell->getParam("\\WR_CLK_POLARITY"); - Const current_wr_clk = get_state(cell->getPort("\\WR_CLK")); + Const wr_clk_enable = cell->getParam(ID::WR_CLK_ENABLE); + Const wr_clk_polarity = cell->getParam(ID::WR_CLK_POLARITY); + Const current_wr_clk = get_state(cell->getPort(ID::WR_CLK)); for (int port_idx = 0; port_idx < num_wr_ports; port_idx++) { @@ -439,9 +439,9 @@ struct SimInstance if (wr_clk_enable[port_idx] == State::S0) { - addr = get_state(cell->getPort("\\WR_ADDR").extract(port_idx*abits, abits)); - data = get_state(cell->getPort("\\WR_DATA").extract(port_idx*width, width)); - enable = get_state(cell->getPort("\\WR_EN").extract(port_idx*width, width)); + addr = get_state(cell->getPort(ID::WR_ADDR).extract(port_idx*abits, abits)); + data = get_state(cell->getPort(ID::WR_DATA).extract(port_idx*width, width)); + enable = get_state(cell->getPort(ID::WR_EN).extract(port_idx*width, width)); } else { @@ -485,9 +485,9 @@ struct SimInstance Cell *cell = it.first; ff_state_t &ff = it.second; - if (cell->type.in("$dff")) { - ff.past_clock = get_state(cell->getPort("\\CLK"))[0]; - ff.past_d = get_state(cell->getPort("\\D")); + if (cell->type.in(ID($dff))) { + ff.past_clock = get_state(cell->getPort(ID::CLK))[0]; + ff.past_d = get_state(cell->getPort(ID::D)); } } @@ -496,28 +496,28 @@ struct SimInstance Cell *cell = it.first; mem_state_t &mem = it.second; - mem.past_wr_clk = get_state(cell->getPort("\\WR_CLK")); - mem.past_wr_en = get_state(cell->getPort("\\WR_EN")); - mem.past_wr_addr = get_state(cell->getPort("\\WR_ADDR")); - mem.past_wr_data = get_state(cell->getPort("\\WR_DATA")); + mem.past_wr_clk = get_state(cell->getPort(ID::WR_CLK)); + mem.past_wr_en = get_state(cell->getPort(ID::WR_EN)); + mem.past_wr_addr = get_state(cell->getPort(ID::WR_ADDR)); + mem.past_wr_data = get_state(cell->getPort(ID::WR_DATA)); } for (auto cell : formal_database) { string label = log_id(cell); - if (cell->attributes.count("\\src")) - label = cell->attributes.at("\\src").decode_string(); + if (cell->attributes.count(ID::src)) + label = cell->attributes.at(ID::src).decode_string(); - State a = get_state(cell->getPort("\\A"))[0]; - State en = get_state(cell->getPort("\\EN"))[0]; + State a = get_state(cell->getPort(ID::A))[0]; + State en = get_state(cell->getPort(ID::EN))[0]; - if (cell->type == "$cover" && en == State::S1 && a != State::S1) + if (cell->type == ID($cover) && en == State::S1 && a != State::S1) log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str()); - if (cell->type == "$assume" && en == State::S1 && a != State::S1) + if (cell->type == ID($assume) && en == State::S1 && a != State::S1) log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); - if (cell->type == "$assert" && en == State::S1 && a != State::S1) + if (cell->type == ID($assert) && en == State::S1 && a != State::S1) log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); } @@ -533,22 +533,22 @@ struct SimInstance wbmods.insert(module); for (auto wire : module->wires()) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); for (auto &it : ff_database) { Cell *cell = it.first; - SigSpec sig_q = cell->getPort("\\Q"); + SigSpec sig_q = cell->getPort(ID::Q); Const initval = get_state(sig_q); for (int i = 0; i < GetSize(sig_q); i++) { Wire *w = sig_q[i].wire; - if (w->attributes.count("\\init") == 0) - w->attributes["\\init"] = Const(State::Sx, GetSize(w)); + if (w->attributes.count(ID::init) == 0) + w->attributes[ID::init] = Const(State::Sx, GetSize(w)); - w->attributes["\\init"][sig_q[i].offset] = initval[i]; + w->attributes[ID::init][sig_q[i].offset] = initval[i]; } } @@ -564,7 +564,7 @@ struct SimInstance initval.bits.pop_back(); } - cell->setParam("\\INIT", initval); + cell->setParam(ID::INIT, initval); } for (auto it : children) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index e6c189c3e..78ecab1e7 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -170,7 +170,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) { if (clk_polarity != (cell->type == ID($_DFF_P_))) return; - if (clk_sig != assign_map(cell->getPort(ID(C)))) + if (clk_sig != assign_map(cell->getPort(ID::C))) return; if (GetSize(en_sig) != 0) return; @@ -183,17 +183,17 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) return; if (en_polarity != cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) return; - if (clk_sig != assign_map(cell->getPort(ID(C)))) + if (clk_sig != assign_map(cell->getPort(ID::C))) return; - if (en_sig != assign_map(cell->getPort(ID(E)))) + if (en_sig != assign_map(cell->getPort(ID::E))) return; goto matching_dff; } if (0) { matching_dff: - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); if (keepff) for (auto &c : sig_q.chunks()) @@ -263,7 +263,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) { RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID(S)); + RTLIL::SigSpec sig_s = cell->getPort(ID::S); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); assign_map.apply(sig_a); @@ -285,7 +285,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) { RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_c = cell->getPort(ID(C)); + RTLIL::SigSpec sig_c = cell->getPort(ID::C); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); assign_map.apply(sig_a); @@ -307,8 +307,8 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) { RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_c = cell->getPort(ID(C)); - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); + RTLIL::SigSpec sig_c = cell->getPort(ID::C); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); assign_map.apply(sig_a); @@ -1032,9 +1032,9 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin RTLIL::Wire *w = it.second; RTLIL::Wire *orig_wire = nullptr; RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire)); - if (orig_wire != nullptr && orig_wire->attributes.count(ID(src))) - wire->attributes[ID(src)] = orig_wire->attributes[ID(src)]; - if (markgroups) wire->attributes[ID(abcgroup)] = map_autoidx; + if (orig_wire != nullptr && orig_wire->attributes.count(ID::src)) + wire->attributes[ID::src] = orig_wire->attributes[ID::src]; + if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx; design->select(module, wire); } @@ -1060,7 +1060,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } if (c->type == ID(NOT)) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); design->select(module, cell); @@ -1068,7 +1068,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); @@ -1077,89 +1077,89 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } if (c->type.in(ID(MUX), ID(NMUX))) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)])); - cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)])); + cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); design->select(module, cell); continue; } if (c->type == ID(MUX4)) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)])); - cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)])); - cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)])); - cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)])); - cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)])); + cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)])); + cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)])); + cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)])); + cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); design->select(module, cell); continue; } if (c->type == ID(MUX8)) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)])); - cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)])); - cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)])); - cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)])); - cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)])); - cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)])); - cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)])); - cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)])); - cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)])); - cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)])); + cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)])); + cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)])); + cell->setPort(ID::E, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::E).as_wire()->name)])); + cell->setPort(ID::F, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::F).as_wire()->name)])); + cell->setPort(ID::G, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::G).as_wire()->name)])); + cell->setPort(ID::H, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::H).as_wire()->name)])); + cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)])); + cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)])); + cell->setPort(ID::U, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::U).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); design->select(module, cell); continue; } if (c->type == ID(MUX16)) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)])); - cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)])); - cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)])); - cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)])); - cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)])); - cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)])); - cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)])); - cell->setPort(ID(I), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(I)).as_wire()->name)])); - cell->setPort(ID(J), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(J)).as_wire()->name)])); - cell->setPort(ID(K), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(K)).as_wire()->name)])); - cell->setPort(ID(L), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(L)).as_wire()->name)])); - cell->setPort(ID(M), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(M)).as_wire()->name)])); - cell->setPort(ID(N), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(N)).as_wire()->name)])); - cell->setPort(ID(O), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(O)).as_wire()->name)])); - cell->setPort(ID(P), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(P)).as_wire()->name)])); - cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)])); - cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)])); - cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)])); - cell->setPort(ID(V), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(V)).as_wire()->name)])); + cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)])); + cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)])); + cell->setPort(ID::E, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::E).as_wire()->name)])); + cell->setPort(ID::F, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::F).as_wire()->name)])); + cell->setPort(ID::G, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::G).as_wire()->name)])); + cell->setPort(ID::H, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::H).as_wire()->name)])); + cell->setPort(ID::I, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::I).as_wire()->name)])); + cell->setPort(ID::J, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::J).as_wire()->name)])); + cell->setPort(ID::K, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::K).as_wire()->name)])); + cell->setPort(ID::L, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::L).as_wire()->name)])); + cell->setPort(ID::M, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::M).as_wire()->name)])); + cell->setPort(ID::N, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::N).as_wire()->name)])); + cell->setPort(ID::O, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::O).as_wire()->name)])); + cell->setPort(ID::P, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::P).as_wire()->name)])); + cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)])); + cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)])); + cell->setPort(ID::U, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::U).as_wire()->name)])); + cell->setPort(ID::V, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::V).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); design->select(module, cell); continue; } if (c->type.in(ID(AOI3), ID(OAI3))) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)])); - cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)])); + cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); design->select(module, cell); continue; } if (c->type.in(ID(AOI4), ID(OAI4))) { RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1)); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)])); cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)])); - cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)])); - cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)])); + cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)])); + cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)])); cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)])); design->select(module, cell); continue; @@ -1172,12 +1172,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } else { log_assert(en_sig.size() == 1); cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort(ID(E), en_sig); + cell->setPort(ID::E, en_sig); } - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; - cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)])); - cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)])); - cell->setPort(ID(C), clk_sig); + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; + cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)])); + cell->setPort(ID::Q, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Q).as_wire()->name)])); + cell->setPort(ID::C, clk_sig); design->select(module, cell); continue; } @@ -1201,17 +1201,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } else { log_assert(en_sig.size() == 1); cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort(ID(E), en_sig); + cell->setPort(ID::E, en_sig); } - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; - cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)])); - cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)])); - cell->setPort(ID(C), clk_sig); + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; + cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)])); + cell->setPort(ID::Q, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Q).as_wire()->name)])); + cell->setPort(ID::C, clk_sig); design->select(module, cell); continue; } - if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)).as_int() == 2) { + if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) { SigSpec my_a = module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]; SigSpec my_y = module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]; module->connect(my_y, my_a); @@ -1219,7 +1219,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); - if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx; cell->parameters = c->parameters; for (auto &conn : c->connections()) { RTLIL::SigSpec newsig; @@ -1244,10 +1244,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin if (recover_init) for (auto wire : mapped_mod->wires()) { - if (wire->attributes.count(ID(init))) { + if (wire->attributes.count(ID::init)) { Wire *w = module->wires_[remap_name(wire->name)]; - log_assert(w->attributes.count(ID(init)) == 0); - w->attributes[ID(init)] = wire->attributes.at(ID(init)); + log_assert(w->attributes.count(ID::init) == 0); + w->attributes[ID::init] = wire->attributes.at(ID::init); } } @@ -1869,9 +1869,9 @@ struct AbcPass : public Pass { signal_init.clear(); for (Wire *wire : mod->wires()) - if (wire->attributes.count(ID(init))) { + if (wire->attributes.count(ID::init)) { SigSpec initsig = assign_map(wire); - Const initval = wire->attributes.at(ID(init)); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) switch (initval[i]) { case State::S0: @@ -1930,14 +1930,14 @@ struct AbcPass : public Pass { if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { - key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); + key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID::C)), true, RTLIL::SigSpec()); } else if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)); bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)); - key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E)))); + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID::C)), this_en_pol, assign_map(cell->getPort(ID::E))); } else continue; diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 212e0692d..9757b1539 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -318,7 +318,7 @@ struct Abc9Pass : public ScriptPass log("Skipping module %s as it contains processes.\n", log_id(mod)); continue; } - log_assert(!mod->attributes.count(ID(abc9_box_id))); + log_assert(!mod->attributes.count(ID::abc9_box_id)); log_push(); active_design->selection().select(mod); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index e1baf4e3d..00af36615 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -41,8 +41,8 @@ void check(RTLIL::Design *design) if (m->name.begins_with("$paramod")) continue; - auto flop = m->get_bool_attribute(ID(abc9_flop)); - auto it = m->attributes.find(ID(abc9_box_id)); + auto flop = m->get_bool_attribute(ID::abc9_flop); + auto it = m->attributes.find(ID::abc9_box_id); if (!flop) { if (it == m->attributes.end()) continue; @@ -59,7 +59,7 @@ void check(RTLIL::Design *design) for (const auto &port_name : m->ports) { auto w = m->wire(port_name); log_assert(w); - if (w->get_bool_attribute("\\abc9_carry")) { + if (w->get_bool_attribute(ID::abc9_carry)) { if (w->port_input) { if (carry_in != IdString()) log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m)); @@ -99,7 +99,7 @@ void mark_scc(RTLIL::Module *module) // write_xaiger to break this wire into PI and POs) pool<RTLIL::Const> ids_seen; for (auto cell : module->cells()) { - auto it = cell->attributes.find(ID(abc9_scc_id)); + auto it = cell->attributes.find(ID::abc9_scc_id); if (it == cell->attributes.end()) continue; auto id = it->second; @@ -111,7 +111,7 @@ void mark_scc(RTLIL::Module *module) if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { Wire *w = module->addWire(NEW_ID, GetSize(c.second)); - w->set_bool_attribute(ID(abc9_scc)); + w->set_bool_attribute(ID::abc9_scc); module->connect(w, c.second); c.second = w; } @@ -130,7 +130,7 @@ void prep_dff(RTLIL::Module *module) dict<clkdomain_t, int> clk_to_mergeability; for (auto cell : module->cells()) { - if (cell->type != "$__ABC9_FF_") + if (cell->type != ID($__ABC9_FF_)) continue; Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str())); @@ -141,7 +141,7 @@ void prep_dff(RTLIL::Module *module) clkdomain_t key(abc9_clock); auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1)); - auto r2 = cell->attributes.insert(ID(abc9_mergeability));; + auto r2 = cell->attributes.insert(ID::abc9_mergeability); log_assert(r2.second); r2.first->second = r.first->second; } @@ -152,20 +152,20 @@ void prep_dff(RTLIL::Module *module) dict<SigSpec, SigSpec> replace; for (auto cell : holes_module->cells().to_vector()) { - if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_", - "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) + if (!cell->type.in(ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), + ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1), ID($_DFF_PP0_), ID($_DFF_PP1_))) continue; - SigBit D = cell->getPort("\\D"); - SigBit Q = cell->getPort("\\Q"); + SigBit D = cell->getPort(ID::D); + SigBit Q = cell->getPort(ID::Q); // Emulate async control embedded inside $_DFF_* cell with mux in front of D - if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_")) - D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R")); - else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_")) - D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R")); - else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_")) - D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R")); - else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_")) - D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R")); + if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_PN0_))) + D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort(ID::R)); + else if (cell->type.in(ID($_DFF_NN1_), ID($_DFF_PN1_))) + D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort(ID::R)); + else if (cell->type.in(ID($_DFF_NP0_), ID($_DFF_PP0_))) + D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort(ID::R)); + else if (cell->type.in(ID($_DFF_NP1_), ID($_DFF_PP1_))) + D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort(ID::R)); // Remove the $_DFF_* cell from what needs to be a combinatorial box holes_module->remove(cell); Wire *port; @@ -208,17 +208,17 @@ void prep_xaiger(RTLIL::Module *module, bool dff) dict<IdString, std::vector<IdString>> box_ports; for (auto cell : module->cells()) { - if (cell->type == "$__ABC9_FF_") + if (cell->type == ID($__ABC9_FF_)) continue; if (cell->has_keep_attr()) continue; auto inst_module = module->design->module(cell->type); - bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop"); + bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop); if (abc9_flop && !dff) continue; - if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) { + if ((inst_module && inst_module->get_bool_attribute(ID::abc9_box)) || abc9_flop) { auto r = box_ports.insert(cell->type); if (r.second) { // Make carry in the last PI, and carry out the last PO @@ -227,7 +227,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) for (const auto &port_name : inst_module->ports) { auto w = inst_module->wire(port_name); log_assert(w); - if (w->get_bool_attribute("\\abc9_carry")) { + if (w->get_bool_attribute(ID::abc9_carry)) { log_assert(w->port_input != w->port_output); if (w->port_input) carry_in = port_name; @@ -289,7 +289,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str())); log_assert(holes_module); - holes_module->set_bool_attribute("\\abc9_holes"); + holes_module->set_bool_attribute(ID::abc9_holes); dict<IdString, Cell*> cell_cache; TimingInfo timing; @@ -300,10 +300,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff) log_assert(cell); RTLIL::Module* box_module = design->module(cell->type); - if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop"))) + if (!box_module || (!box_module->get_bool_attribute(ID::abc9_box) && !box_module->get_bool_attribute(ID::abc9_flop))) continue; - cell->attributes["\\abc9_box_seq"] = box_count++; + cell->attributes[ID::abc9_box_seq] = box_count++; IdString derived_type = box_module->derive(design, cell->parameters); box_module = design->module(derived_type); @@ -314,7 +314,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) if (box_module->has_processes()) Pass::call_on_module(design, box_module, "proc"); - if (box_module->get_bool_attribute("\\whitebox")) { + if (box_module->get_bool_attribute(ID::whitebox)) { holes_cell = holes_module->addCell(cell->name, derived_type); if (box_module->has_processes()) @@ -345,7 +345,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) // For flops only, create an extra 1-bit input that drives a new wire // called "<cell>.abc9_ff.Q" that is used below - if (box_module->get_bool_attribute("\\abc9_flop")) { + if (box_module->get_bool_attribute(ID::abc9_flop)) { box_inputs++; Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs)); if (!holes_wire) { @@ -402,13 +402,13 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) continue; if (!inst_module->get_blackbox_attribute()) continue; - if (inst_module->attributes.count(ID(abc9_box))) + if (inst_module->attributes.count(ID::abc9_box)) continue; IdString derived_type = inst_module->derive(design, cell->parameters); inst_module = design->module(derived_type); log_assert(inst_module); - if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) { + if (dff_mode && inst_module->get_bool_attribute(ID::abc9_flop)) { flops.insert(inst_module); continue; // do not add $__ABC9_DELAY boxes to flops // as delays will be captured in the flop box @@ -451,9 +451,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) } #endif auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY)); - box->setPort(ID(I), conn.second[i]); - box->setPort(ID(O), O[i]); - box->setParam(ID(DELAY), d); + box->setPort(ID::I, conn.second[i]); + box->setPort(ID::O, O[i]); + box->setParam(ID::DELAY, d); conn.second[i] = O[i]; } } @@ -466,7 +466,7 @@ void prep_lut(RTLIL::Design *design, int maxlut) std::vector<std::tuple<int, IdString, int, std::vector<int>>> table; for (auto module : design->modules()) { - auto it = module->attributes.find(ID(abc9_lut)); + auto it = module->attributes.find(ID::abc9_lut); if (it == module->attributes.end()) continue; @@ -527,7 +527,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode) std::stringstream ss; int abc9_box_id = 1; for (auto module : design->modules()) { - auto it = module->attributes.find(ID(abc9_box_id)); + auto it = module->attributes.find(ID::abc9_box_id); if (it == module->attributes.end()) continue; abc9_box_id = std::max(abc9_box_id, it->second.as_int()); @@ -535,9 +535,9 @@ void prep_box(RTLIL::Design *design, bool dff_mode) dict<IdString,std::vector<IdString>> box_ports; for (auto module : design->modules()) { - auto abc9_flop = module->get_bool_attribute(ID(abc9_flop)); + auto abc9_flop = module->get_bool_attribute(ID::abc9_flop); if (abc9_flop) { - auto r = module->attributes.insert(ID(abc9_box_id)); + auto r = module->attributes.insert(ID::abc9_box_id); if (!r.second) continue; r.first->second = abc9_box_id++; @@ -604,10 +604,10 @@ void prep_box(RTLIL::Design *design, bool dff_mode) } } else { - if (!module->attributes.erase(ID(abc9_box))) + if (!module->attributes.erase(ID::abc9_box)) continue; - auto r = module->attributes.insert(ID(abc9_box_id)); + auto r = module->attributes.insert(ID::abc9_box_id); if (!r.second) continue; r.first->second = abc9_box_id++; @@ -621,7 +621,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode) for (const auto &port_name : module->ports) { auto w = module->wire(port_name); log_assert(w); - if (w->get_bool_attribute("\\abc9_carry")) { + if (w->get_bool_attribute(ID::abc9_carry)) { log_assert(w->port_input != w->port_output); if (w->port_input) carry_in = port_name; @@ -650,7 +650,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode) outputs.emplace_back(wire, i); } - ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int(); + ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int(); ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0"); ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl; @@ -727,7 +727,7 @@ void reintegrate(RTLIL::Module *module) dict<IdString,std::vector<IdString>> box_ports; for (auto m : design->modules()) { - if (!m->attributes.count(ID(abc9_box_id))) + if (!m->attributes.count(ID::abc9_box_id)) continue; auto r = box_ports.insert(m->name); @@ -740,7 +740,7 @@ void reintegrate(RTLIL::Module *module) for (const auto &port_name : m->ports) { auto w = m->wire(port_name); log_assert(w); - if (w->get_bool_attribute("\\abc9_carry")) { + if (w->get_bool_attribute(ID::abc9_carry)) { log_assert(w->port_input != w->port_output); if (w->port_input) carry_in = port_name; @@ -763,7 +763,7 @@ void reintegrate(RTLIL::Module *module) continue; if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) module->remove(cell); - else if (cell->attributes.erase("\\abc9_box_seq")) + else if (cell->attributes.erase(ID::abc9_box_seq)) boxes.emplace_back(cell); } @@ -874,7 +874,7 @@ void reintegrate(RTLIL::Module *module) IdString derived_type = box_module->derive(design, existing_cell->parameters); RTLIL::Module* derived_module = design->module(derived_type); log_assert(derived_module); - log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int())); + log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at(ID::abc9_box_id).as_int())); mapped_cell->type = existing_cell->type; RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); @@ -882,16 +882,16 @@ void reintegrate(RTLIL::Module *module) cell->attributes = existing_cell->attributes; module->swap_names(cell, existing_cell); - auto jt = mapped_cell->connections_.find("\\i"); + auto jt = mapped_cell->connections_.find(ID(i)); log_assert(jt != mapped_cell->connections_.end()); SigSpec inputs = std::move(jt->second); mapped_cell->connections_.erase(jt); - jt = mapped_cell->connections_.find("\\o"); + jt = mapped_cell->connections_.find(ID(o)); log_assert(jt != mapped_cell->connections_.end()); SigSpec outputs = std::move(jt->second); mapped_cell->connections_.erase(jt); - auto abc9_flop = box_module->attributes.count("\\abc9_flop"); + auto abc9_flop = box_module->attributes.count(ID::abc9_flop); if (!abc9_flop) { for (const auto &i : inputs) bit_users[i].insert(mapped_cell->name); @@ -966,7 +966,7 @@ void reintegrate(RTLIL::Module *module) RTLIL::Wire *mapped_wire = mapped_mod->wire(port); RTLIL::Wire *wire = module->wire(port); log_assert(wire); - wire->attributes.erase(ID(abc9_scc)); + wire->attributes.erase(ID::abc9_scc); RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire)); @@ -1033,7 +1033,7 @@ void reintegrate(RTLIL::Module *module) // Push downstream LUTs past inverter for (auto sink_cell : jt->second) { SigSpec A = sink_cell->getPort(ID::A); - RTLIL::Const mask = sink_cell->getParam(ID(LUT)); + RTLIL::Const mask = sink_cell->getParam(ID::LUT); int index = 0; for (; index < GetSize(A); index++) if (A[index] == a_bit) @@ -1047,7 +1047,7 @@ void reintegrate(RTLIL::Module *module) } A[index] = y_bit; sink_cell->setPort(ID::A, A); - sink_cell->setParam(ID(LUT), mask); + sink_cell->setParam(ID::LUT, mask); } // Since we have rewritten all sinks (which we know @@ -1056,7 +1056,7 @@ void reintegrate(RTLIL::Module *module) // that the original driving LUT will become dangling // and get cleaned away clone_lut: - driver_mask = driver_lut->getParam(ID(LUT)); + driver_mask = driver_lut->getParam(ID::LUT); for (auto &b : driver_mask.bits) { if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; @@ -1228,7 +1228,7 @@ struct Abc9OpsPass : public Pass { prep_box(design, dff_mode); for (auto mod : design->selected_modules()) { - if (mod->get_bool_attribute("\\abc9_holes")) + if (mod->get_bool_attribute(ID::abc9_holes)) continue; if (mod->processes.size() > 0) { diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 034731b87..1925145d3 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -72,7 +72,7 @@ struct AlumaccWorker RTLIL::SigSpec get_eq() { if (GetSize(cached_eq) == 0) - cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID(X)), false, alu_cell->get_src_attribute()); + cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute()); return cached_eq; } @@ -84,7 +84,7 @@ struct AlumaccWorker RTLIL::SigSpec get_cf() { if (GetSize(cached_cf) == 0) { - cached_cf = alu_cell->getPort(ID(CO)); + cached_cf = alu_cell->getPort(ID::CO); log_assert(GetSize(cached_cf) >= 1); cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute()); } @@ -93,7 +93,7 @@ struct AlumaccWorker RTLIL::SigSpec get_of() { if (GetSize(cached_of) == 0) { - cached_of = {alu_cell->getPort(ID(CO)), alu_cell->getPort(ID(CI))}; + cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)}; log_assert(GetSize(cached_of) >= 2); cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); } @@ -154,7 +154,7 @@ struct AlumaccWorker if (cell->type.in(ID($pos), ID($neg))) { new_port.in_a = sigmap(cell->getPort(ID::A)); - new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); + new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); new_port.do_subtract = cell->type == ID($neg); n->macc.ports.push_back(new_port); } @@ -162,12 +162,12 @@ struct AlumaccWorker if (cell->type.in(ID($add), ID($sub))) { new_port.in_a = sigmap(cell->getPort(ID::A)); - new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); + new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); new_port.do_subtract = false; n->macc.ports.push_back(new_port); new_port.in_a = sigmap(cell->getPort(ID::B)); - new_port.is_signed = cell->getParam(ID(B_SIGNED)).as_bool(); + new_port.is_signed = cell->getParam(ID::B_SIGNED).as_bool(); new_port.do_subtract = cell->type == ID($sub); n->macc.ports.push_back(new_port); } @@ -176,7 +176,7 @@ struct AlumaccWorker { new_port.in_a = sigmap(cell->getPort(ID::A)); new_port.in_b = sigmap(cell->getPort(ID::B)); - new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); + new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); new_port.do_subtract = false; n->macc.ports.push_back(new_port); } @@ -399,7 +399,7 @@ struct AlumaccWorker bool cmp_less = cell->type.in(ID($lt), ID($le)); bool cmp_equal = cell->type.in(ID($le), ID($ge)); - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); RTLIL::SigSpec B = sigmap(cell->getPort(ID::B)); @@ -439,7 +439,7 @@ struct AlumaccWorker for (auto cell : eq_cells) { bool cmp_equal = cell->type.in(ID($eq), ID($eqx)); - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); RTLIL::SigSpec A = sigmap(cell->getPort(ID::A)); RTLIL::SigSpec B = sigmap(cell->getPort(ID::B)); @@ -495,11 +495,11 @@ struct AlumaccWorker n->alu_cell->setPort(ID::A, n->a); n->alu_cell->setPort(ID::B, n->b); - n->alu_cell->setPort(ID(CI), GetSize(n->c) ? n->c : State::S0); - n->alu_cell->setPort(ID(BI), n->invert_b ? State::S1 : State::S0); + n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0); + n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0); n->alu_cell->setPort(ID::Y, n->y); - n->alu_cell->setPort(ID(X), module->addWire(NEW_ID, GetSize(n->y))); - n->alu_cell->setPort(ID(CO), module->addWire(NEW_ID, GetSize(n->y))); + n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y))); + n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y))); n->alu_cell->fixup_parameters(n->is_signed, n->is_signed); for (auto &it : n->cmp) diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index b9cd68883..3f4b6aa66 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -129,13 +129,13 @@ struct ClkbufmapPass : public Pass { if (module->get_blackbox_attribute()) { for (auto port : module->ports) { auto wire = module->wire(port); - if (wire->get_bool_attribute("\\clkbuf_driver")) + if (wire->get_bool_attribute(ID::clkbuf_driver)) for (int i = 0; i < GetSize(wire); i++) buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); - if (wire->get_bool_attribute("\\clkbuf_sink")) + if (wire->get_bool_attribute(ID::clkbuf_sink)) for (int i = 0; i < GetSize(wire); i++) sink_ports.insert(make_pair(module->name, make_pair(wire->name, i))); - auto it = wire->attributes.find("\\clkbuf_inv"); + auto it = wire->attributes.find(ID::clkbuf_inv); if (it != wire->attributes.end()) { IdString in_name = RTLIL::escape_id(it->second.decode_string()); for (int i = 0; i < GetSize(wire); i++) { @@ -215,7 +215,7 @@ struct ClkbufmapPass : public Pass { if (wire->port_input && wire->port_output) continue; bool process_wire = module->selected(wire); - if (!select && wire->get_bool_attribute("\\clkbuf_inhibit")) + if (!select && wire->get_bool_attribute(ID::clkbuf_inhibit)) process_wire = false; if (!process_wire) { // This wire is supposed to be bypassed, so make sure we don't buffer it in @@ -238,7 +238,7 @@ struct ClkbufmapPass : public Pass { buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); } else if (!sink_wire_bits.count(mapped_wire_bit)) { // Nothing to do. - } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute("\\top"))) { + } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) { // Clock network not yet buffered, driven by one of // our cells or a top-level input -- buffer it. @@ -247,7 +247,7 @@ struct ClkbufmapPass : public Pass { Wire *iwire = module->addWire(NEW_ID); cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); cell->setPort(RTLIL::escape_id(buf_portname2), iwire); - if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute("\\top")) { + if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top)) { log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i); RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index 35d43b106..a7dce9c81 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -113,7 +113,7 @@ struct DeminoutPass : public Pass { { if (bits_numports[bit] > 1 || bits_inout.count(bit)) new_input = true, new_output = true; - if (bit == State::S0 || bit == State::S1) + if (!bit.wire) new_output = true; if (bits_written.count(bit)) { new_output = true; diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 0242256e5..aa9bbfe17 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -88,7 +88,7 @@ struct Dff2dffeWorker cell_int_t mux_cell_int = bit2mux.at(d); RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID::A)); RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID::B)); - RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID(S))); + RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID::S)); int width = GetSize(sig_a), index = mux_cell_int.second; for (int i = 0; i < GetSize(sig_s); i++) @@ -185,8 +185,8 @@ struct Dff2dffeWorker void handle_dff_cell(RTLIL::Cell *dff_cell) { - RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID(D))); - RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID(Q))); + RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID::D)); + RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID::Q)); std::map<patterns_t, std::set<int>> grouped_patterns; std::set<int> remaining_indices; @@ -208,15 +208,15 @@ struct Dff2dffeWorker } if (!direct_dict.empty()) { log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q)); - dff_cell->setPort(ID(E), make_patterns_logic(it.first, true)); + dff_cell->setPort(ID::E, make_patterns_logic(it.first, true)); dff_cell->type = direct_dict.at(dff_cell->type); } else if (dff_cell->type == ID($dff)) { - RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID(CLK)), make_patterns_logic(it.first, false), - new_sig_d, new_sig_q, dff_cell->getParam(ID(CLK_POLARITY)).as_bool(), true); + RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID::CLK), make_patterns_logic(it.first, false), + new_sig_d, new_sig_q, dff_cell->getParam(ID::CLK_POLARITY).as_bool(), true); log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); } else { - RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID(C)), make_patterns_logic(it.first, true), + RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID::C), make_patterns_logic(it.first, true), new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true); log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); } @@ -235,9 +235,9 @@ struct Dff2dffeWorker new_sig_d.append(sig_d[i]); new_sig_q.append(sig_q[i]); } - dff_cell->setPort(ID(D), new_sig_d); - dff_cell->setPort(ID(Q), new_sig_q); - dff_cell->setParam(ID(WIDTH), GetSize(remaining_indices)); + dff_cell->setPort(ID::D, new_sig_d); + dff_cell->setPort(ID::Q, new_sig_q); + dff_cell->setParam(ID::WIDTH, GetSize(remaining_indices)); } } @@ -361,19 +361,19 @@ struct Dff2dffePass : public Pass { for (auto cell_other : mod->selected_cells()) { if (cell_other->type != cell->type) continue; - if (sigmap(cell->getPort(ID(EN))) == sigmap(cell_other->getPort(ID(EN)))) + if (sigmap(cell->getPort(ID::EN)) == sigmap(cell_other->getPort(ID::EN))) ce_use++; } if (ce_use >= min_ce_use) continue; } - RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID(D)))); - mod->addDff(NEW_ID, cell->getPort(ID(CLK)), tmp, cell->getPort(ID(Q)), cell->getParam(ID(CLK_POLARITY)).as_bool()); - if (cell->getParam(ID(EN_POLARITY)).as_bool()) - mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(EN)), tmp); + RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID::D))); + mod->addDff(NEW_ID, cell->getPort(ID::CLK), tmp, cell->getPort(ID::Q), cell->getParam(ID::CLK_POLARITY).as_bool()); + if (cell->getParam(ID::EN_POLARITY).as_bool()) + mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::EN), tmp); else - mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(EN)), tmp); + mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::EN), tmp); mod->remove(cell); continue; } @@ -383,7 +383,7 @@ struct Dff2dffePass : public Pass { for (auto cell_other : mod->selected_cells()) { if (cell_other->type != cell->type) continue; - if (sigmap(cell->getPort(ID(E))) == sigmap(cell_other->getPort(ID(E)))) + if (sigmap(cell->getPort(ID::E)) == sigmap(cell_other->getPort(ID::E))) ce_use++; } if (ce_use >= min_ce_use) @@ -393,11 +393,11 @@ struct Dff2dffePass : public Pass { bool clk_pol = cell->type.compare(7, 1, "P") == 0; bool en_pol = cell->type.compare(8, 1, "P") == 0; RTLIL::SigSpec tmp = mod->addWire(NEW_ID); - mod->addDff(NEW_ID, cell->getPort(ID(C)), tmp, cell->getPort(ID(Q)), clk_pol); + mod->addDff(NEW_ID, cell->getPort(ID::C), tmp, cell->getPort(ID::Q), clk_pol); if (en_pol) - mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(E)), tmp); + mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::E), tmp); else - mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(E)), tmp); + mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::E), tmp); mod->remove(cell); continue; } diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc index 3fa1ed5cf..c155297d9 100644 --- a/passes/techmap/dff2dffs.cc +++ b/passes/techmap/dff2dffs.cc @@ -90,7 +90,7 @@ struct Dff2dffsPass : public Pass { for (auto cell : ff_cells) { - SigSpec sig_d = cell->getPort(ID(D)); + SigSpec sig_d = cell->getPort(ID::D); if (GetSize(sig_d) < 1) continue; @@ -103,7 +103,7 @@ struct Dff2dffsPass : public Pass { Cell *mux_cell = sr_muxes.at(bit_d); SigBit bit_a = sigmap(mux_cell->getPort(ID::A)); SigBit bit_b = sigmap(mux_cell->getPort(ID::B)); - SigBit bit_s = sigmap(mux_cell->getPort(ID(S))); + SigBit bit_s = sigmap(mux_cell->getPort(ID::S)); SigBit sr_val, sr_sig; bool invert_sr; @@ -120,9 +120,9 @@ struct Dff2dffsPass : public Pass { } if (match_init) { - SigBit bit_q = cell->getPort(ID(Q)); + SigBit bit_q = cell->getPort(ID::Q); if (bit_q.wire) { - auto it = bit_q.wire->attributes.find(ID(init)); + auto it = bit_q.wire->attributes.find(ID::init); if (it != bit_q.wire->attributes.end()) { auto init_val = it->second[bit_q.offset]; if (init_val == State::S1 && sr_val != State::S1) @@ -155,8 +155,8 @@ struct Dff2dffsPass : public Pass { else cell->type = ID($__DFFS_PP0_); } } - cell->setPort(ID(R), sr_sig); - cell->setPort(ID(D), bit_d); + cell->setPort(ID::R, sr_sig); + cell->setPort(ID::D, bit_d); } } } diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index cf9301442..0424ce434 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -99,8 +99,8 @@ struct DffinitPass : public Pass { pool<SigBit> used_bits; for (auto wire : module->selected_wires()) { - if (wire->attributes.count(ID(init))) { - Const value = wire->attributes.at(ID(init)); + if (wire->attributes.count(ID::init)) { + Const value = wire->attributes.at(ID::init); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) if (value[i] != State::Sx) init_bits[sigmap(SigBit(wire, i))] = value[i]; @@ -161,8 +161,8 @@ struct DffinitPass : public Pass { } for (auto wire : module->selected_wires()) - if (wire->attributes.count(ID(init))) { - Const &value = wire->attributes.at(ID(init)); + if (wire->attributes.count(ID::init)) { + Const &value = wire->attributes.at(ID::init); bool do_cleanup = true; for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { SigBit bit = sigmap(SigBit(wire, i)); @@ -173,7 +173,7 @@ struct DffinitPass : public Pass { } if (do_cleanup) { log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); - wire->attributes.erase(ID(init)); + wire->attributes.erase(ID::init); } } } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index b15109cd3..aa344cf8a 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -78,7 +78,7 @@ static void logmap_all() static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol) { - if (cell == NULL || attr == NULL || attr->value.empty()) + if (cell == nullptr || attr == nullptr || attr->value.empty()) return false; std::string value = attr->value; @@ -117,7 +117,7 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool prepare_mode) { - LibertyAst *best_cell = NULL; + LibertyAst *best_cell = nullptr; std::map<std::string, char> best_cell_ports; int best_cell_pins = 0; bool best_cell_noninv = false; @@ -132,11 +132,11 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has continue; LibertyAst *dn = cell->find("dont_use"); - if (dn != NULL && dn->value == "true") + if (dn != nullptr && dn->value == "true") continue; LibertyAst *ff = cell->find("ff"); - if (ff == NULL) + if (ff == nullptr) continue; std::string cell_clk_pin, cell_rst_pin, cell_next_pin; @@ -163,7 +163,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has double area = 0; LibertyAst *ar = cell->find("area"); - if (ar != NULL && !ar->value.empty()) + if (ar != nullptr && !ar->value.empty()) area = atof(ar->value.c_str()); int num_pins = 0; @@ -175,7 +175,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has continue; LibertyAst *dir = pin->find("direction"); - if (dir == NULL || dir->value == "internal") + if (dir == nullptr || dir->value == "internal") continue; num_pins++; @@ -183,7 +183,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has goto continue_cell_loop; LibertyAst *func = pin->find("function"); - if (dir->value == "output" && func != NULL) { + if (dir->value == "output" && func != nullptr) { std::string value = func->value; for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t")) value.erase(pos, 1); @@ -205,10 +205,10 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has this_cell_ports[pin->args[0]] = 0; } - if (!found_output || (best_cell != NULL && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output)))) + if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output)))) continue; - if (best_cell != NULL && num_pins == best_cell_pins && area > best_cell_area) + if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area) continue; best_cell = cell; @@ -219,7 +219,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has continue_cell_loop:; } - if (best_cell != NULL) { + if (best_cell != nullptr) { log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n", best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str()); if (prepare_mode) { @@ -238,7 +238,7 @@ static void find_cell(LibertyAst *ast, IdString cell_type, bool clkpol, bool has static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool prepare_mode) { - LibertyAst *best_cell = NULL; + LibertyAst *best_cell = nullptr; std::map<std::string, char> best_cell_ports; int best_cell_pins = 0; bool best_cell_noninv = false; @@ -253,11 +253,11 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool continue; LibertyAst *dn = cell->find("dont_use"); - if (dn != NULL && dn->value == "true") + if (dn != nullptr && dn->value == "true") continue; LibertyAst *ff = cell->find("ff"); - if (ff == NULL) + if (ff == nullptr) continue; std::string cell_clk_pin, cell_set_pin, cell_clr_pin, cell_next_pin; @@ -280,7 +280,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool double area = 0; LibertyAst *ar = cell->find("area"); - if (ar != NULL && !ar->value.empty()) + if (ar != nullptr && !ar->value.empty()) area = atof(ar->value.c_str()); int num_pins = 0; @@ -292,7 +292,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool continue; LibertyAst *dir = pin->find("direction"); - if (dir == NULL || dir->value == "internal") + if (dir == nullptr || dir->value == "internal") continue; num_pins++; @@ -300,7 +300,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool goto continue_cell_loop; LibertyAst *func = pin->find("function"); - if (dir->value == "output" && func != NULL) { + if (dir->value == "output" && func != nullptr) { std::string value = func->value; for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t")) value.erase(pos, 1); @@ -322,10 +322,10 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool this_cell_ports[pin->args[0]] = 0; } - if (!found_output || (best_cell != NULL && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output)))) + if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output)))) continue; - if (best_cell != NULL && num_pins == best_cell_pins && area > best_cell_area) + if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area) continue; best_cell = cell; @@ -336,7 +336,7 @@ static void find_cell_sr(LibertyAst *ast, IdString cell_type, bool clkpol, bool continue_cell_loop:; } - if (best_cell != NULL) { + if (best_cell != nullptr) { log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n", best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str()); if (prepare_mode) { @@ -481,11 +481,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare SigMap sigmap(module); std::vector<RTLIL::Cell*> cell_list; - for (auto &it : module->cells_) { - if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) - cell_list.push_back(it.second); - if (it.second->type == ID($_NOT_)) - notmap[sigmap(it.second->getPort(ID::A))].insert(it.second); + for (auto cell : module->cells()) { + if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0) + cell_list.push_back(cell); + if (cell->type == ID($_NOT_)) + notmap[sigmap(cell->getPort(ID::A))].insert(cell); } std::map<std::string, int> stats; @@ -663,9 +663,9 @@ struct DfflibmapPass : public Pass { log(" final dff cell mappings:\n"); logmap_all(); - for (auto &it : design->modules_) - if (design->selected(it.second) && !it.second->get_blackbox_attribute()) - dfflibmap(design, it.second, prepare_mode); + for (auto module : design->selected_modules()) + if (!module->get_blackbox_attribute()) + dfflibmap(design, module, prepare_mode); cell_mappings.clear(); } diff --git a/passes/techmap/dffsr2dff.cc b/passes/techmap/dffsr2dff.cc index 61b06fdc1..4a3ddaf73 100644 --- a/passes/techmap/dffsr2dff.cc +++ b/passes/techmap/dffsr2dff.cc @@ -27,15 +27,15 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell) { if (cell->type == ID($dffsr)) { - int width = cell->getParam(ID(WIDTH)).as_int(); - bool setpol = cell->getParam(ID(SET_POLARITY)).as_bool(); - bool clrpol = cell->getParam(ID(CLR_POLARITY)).as_bool(); + int width = cell->getParam(ID::WIDTH).as_int(); + bool setpol = cell->getParam(ID::SET_POLARITY).as_bool(); + bool clrpol = cell->getParam(ID::CLR_POLARITY).as_bool(); SigBit setunused = setpol ? State::S0 : State::S1; SigBit clrunused = clrpol ? State::S0 : State::S1; - SigSpec setsig = sigmap(cell->getPort(ID(SET))); - SigSpec clrsig = sigmap(cell->getPort(ID(CLR))); + SigSpec setsig = sigmap(cell->getPort(ID::SET)); + SigSpec clrsig = sigmap(cell->getPort(ID::CLR)); Const reset_val; SigSpec setctrl, clrctrl; @@ -78,19 +78,19 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell) log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell)); if (GetSize(setctrl) == 1) { - cell->setPort(ID(ARST), setctrl); - cell->setParam(ID(ARST_POLARITY), setpol); + cell->setPort(ID::ARST, setctrl); + cell->setParam(ID::ARST_POLARITY, setpol); } else { - cell->setPort(ID(ARST), clrctrl); - cell->setParam(ID(ARST_POLARITY), clrpol); + cell->setPort(ID::ARST, clrctrl); + cell->setParam(ID::ARST_POLARITY, clrpol); } cell->type = ID($adff); - cell->unsetPort(ID(SET)); - cell->unsetPort(ID(CLR)); - cell->setParam(ID(ARST_VALUE), reset_val); - cell->unsetParam(ID(SET_POLARITY)); - cell->unsetParam(ID(CLR_POLARITY)); + cell->unsetPort(ID::SET); + cell->unsetPort(ID::CLR); + cell->setParam(ID::ARST_VALUE, reset_val); + cell->unsetParam(ID::SET_POLARITY); + cell->unsetParam(ID::CLR_POLARITY); return; } @@ -102,8 +102,8 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell) char setpol = cell->type.c_str()[9]; char clrpol = cell->type.c_str()[10]; - SigBit setbit = sigmap(cell->getPort(ID(S))); - SigBit clrbit = sigmap(cell->getPort(ID(R))); + SigBit setbit = sigmap(cell->getPort(ID::S)); + SigBit clrbit = sigmap(cell->getPort(ID::R)); SigBit setunused = setpol == 'P' ? State::S0 : State::S1; SigBit clrunused = clrpol == 'P' ? State::S0 : State::S1; @@ -112,14 +112,14 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell) if (setbit == setunused) { cell->type = stringf("$_DFF_%c%c0_", clkpol, clrpol); - cell->unsetPort(ID(S)); + cell->unsetPort(ID::S); goto converted_gate; } if (clrbit == clrunused) { cell->type = stringf("$_DFF_%c%c1_", clkpol, setpol); - cell->setPort(ID(R), cell->getPort(ID(S))); - cell->unsetPort(ID(S)); + cell->setPort(ID::R, cell->getPort(ID::S)); + cell->unsetPort(ID::S); goto converted_gate; } @@ -135,9 +135,9 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell) { if (cell->type == ID($adff)) { - bool rstpol = cell->getParam(ID(ARST_POLARITY)).as_bool(); + bool rstpol = cell->getParam(ID::ARST_POLARITY).as_bool(); SigBit rstunused = rstpol ? State::S0 : State::S1; - SigSpec rstsig = sigmap(cell->getPort(ID(ARST))); + SigSpec rstsig = sigmap(cell->getPort(ID::ARST)); if (rstsig != rstunused) return; @@ -145,9 +145,9 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell) log("Converting %s cell %s.%s to $dff.\n", log_id(cell->type), log_id(module), log_id(cell)); cell->type = ID($dff); - cell->unsetPort(ID(ARST)); - cell->unsetParam(ID(ARST_VALUE)); - cell->unsetParam(ID(ARST_POLARITY)); + cell->unsetPort(ID::ARST); + cell->unsetParam(ID::ARST_VALUE); + cell->unsetParam(ID::ARST_POLARITY); return; } @@ -158,7 +158,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell) char clkpol = cell->type.c_str()[6]; char rstpol = cell->type.c_str()[7]; - SigBit rstbit = sigmap(cell->getPort(ID(R))); + SigBit rstbit = sigmap(cell->getPort(ID::R)); SigBit rstunused = rstpol == 'P' ? State::S0 : State::S1; if (rstbit != rstunused) @@ -168,7 +168,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell) log("Converting %s cell %s.%s to %s.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(newtype)); cell->type = newtype; - cell->unsetPort(ID(R)); + cell->unsetPort(ID::R); return; } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index f8798eea5..f29044790 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -29,8 +29,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -using RTLIL::id2cstr; - class SubCircuitSolver : public SubCircuit::Solver { public: @@ -58,36 +56,36 @@ public: return value; #define param_bool(_n) if (param == _n) return value.as_bool(); - param_bool(ID(ARST_POLARITY)); - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - param_bool(ID(CLK_ENABLE)); - param_bool(ID(CLK_POLARITY)); - param_bool(ID(CLR_POLARITY)); - param_bool(ID(EN_POLARITY)); - param_bool(ID(SET_POLARITY)); - param_bool(ID(TRANSPARENT)); + param_bool(ID::ARST_POLARITY); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + param_bool(ID::CLK_ENABLE); + param_bool(ID::CLK_POLARITY); + param_bool(ID::CLR_POLARITY); + param_bool(ID::EN_POLARITY); + param_bool(ID::SET_POLARITY); + param_bool(ID::TRANSPARENT); #undef param_bool #define param_int(_n) if (param == _n) return value.as_int(); - param_int(ID(ABITS)) - param_int(ID(A_WIDTH)) - param_int(ID(B_WIDTH)) - param_int(ID(CTRL_IN_WIDTH)) - param_int(ID(CTRL_OUT_WIDTH)) - param_int(ID(OFFSET)) - param_int(ID(PRIORITY)) - param_int(ID(RD_PORTS)) - param_int(ID(SIZE)) - param_int(ID(STATE_BITS)) - param_int(ID(STATE_NUM)) - param_int(ID(STATE_NUM_LOG2)) - param_int(ID(STATE_RST)) - param_int(ID(S_WIDTH)) - param_int(ID(TRANS_NUM)) - param_int(ID(WIDTH)) - param_int(ID(WR_PORTS)) - param_int(ID(Y_WIDTH)) + param_int(ID::ABITS) + param_int(ID::A_WIDTH) + param_int(ID::B_WIDTH) + param_int(ID::CTRL_IN_WIDTH) + param_int(ID::CTRL_OUT_WIDTH) + param_int(ID::OFFSET) + param_int(ID::PRIORITY) + param_int(ID::RD_PORTS) + param_int(ID::SIZE) + param_int(ID::STATE_BITS) + param_int(ID::STATE_NUM) + param_int(ID::STATE_NUM_LOG2) + param_int(ID::STATE_RST) + param_int(ID::S_WIDTH) + param_int(ID::TRANS_NUM) + param_int(ID::WIDTH) + param_int(ID::WR_PORTS) + param_int(ID::Y_WIDTH) #undef param_int return value; @@ -121,8 +119,8 @@ public: if (wire_attr.size() > 0) { - RTLIL::Wire *lastNeedleWire = NULL; - RTLIL::Wire *lastHaystackWire = NULL; + RTLIL::Wire *lastNeedleWire = nullptr; + RTLIL::Wire *lastHaystackWire = nullptr; dict<RTLIL::IdString, RTLIL::Const> emptyAttr; for (auto &conn : needleCell->connections()) @@ -149,27 +147,27 @@ struct bit_ref_t { int bit; }; -bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, RTLIL::Design *sel = NULL, - int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = NULL) +bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, RTLIL::Design *sel = nullptr, + int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = nullptr) { SigMap sigmap(mod); std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref; if (sel && !sel->selected(mod)) { - log(" Skipping module %s as it is not selected.\n", id2cstr(mod->name)); + log(" Skipping module %s as it is not selected.\n", log_id(mod->name)); return false; } if (mod->processes.size() > 0) { - log(" Skipping module %s as it contains unprocessed processes.\n", id2cstr(mod->name)); + log(" Skipping module %s as it contains unprocessed processes.\n", log_id(mod->name)); return false; } if (constports) { - graph.createNode("$const$0", "$const$0", NULL, true); - graph.createNode("$const$1", "$const$1", NULL, true); - graph.createNode("$const$x", "$const$x", NULL, true); - graph.createNode("$const$z", "$const$z", NULL, true); + graph.createNode("$const$0", "$const$0", nullptr, true); + graph.createNode("$const$1", "$const$1", nullptr, true); + graph.createNode("$const$x", "$const$x", nullptr, true); + graph.createNode("$const$z", "$const$z", nullptr, true); graph.createPort("$const$0", "\\Y", 1); graph.createPort("$const$1", "\\Y", 1); graph.createPort("$const$x", "\\Y", 1); @@ -182,28 +180,26 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count; if (max_fanout > 0) - for (auto &cell_it : mod->cells_) + for (auto cell : mod->cells()) { - RTLIL::Cell *cell = cell_it.second; if (!sel || sel->selected(mod, cell)) for (auto &conn : cell->connections()) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); for (auto &bit : conn_sig) - if (bit.wire != NULL) + if (bit.wire != nullptr) sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++; } } // create graph nodes from cells - for (auto &cell_it : mod->cells_) + for (auto cell : mod->cells()) { - RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) continue; std::string type = cell->type.str(); - if (sel == NULL && type.compare(0, 2, "\\$") == 0) + if (sel == nullptr && type.compare(0, 2, "\\$") == 0) type = type.substr(1); graph.createNode(cell->name.str(), type, (void*)cell); @@ -221,7 +217,7 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, { auto &bit = conn_sig[i]; - if (bit.wire == NULL) { + if (bit.wire == nullptr) { if (constports) { std::string node = "$const$x"; if (bit == RTLIL::State::S0) node = "$const$0"; @@ -253,9 +249,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, } // mark external signals (used in non-selected cells) - for (auto &cell_it : mod->cells_) + for (auto cell : mod->cells()) { - RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) for (auto &conn : cell->connections()) { @@ -271,9 +266,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, } // mark external signals (used in module ports) - for (auto &wire_it : mod->wires_) + for (auto wire : mod->wires()) { - RTLIL::Wire *wire = wire_it.second; if (wire->port_id > 0) { RTLIL::SigSpec conn_sig(wire); @@ -300,8 +294,7 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit: RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name); // create cell ports - for (auto &it : needle->wires_) { - RTLIL::Wire *wire = it.second; + for (auto wire : needle->wires()) { if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i)); @@ -316,7 +309,7 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit: RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData; RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData; - if (needle_cell == NULL) + if (needle_cell == nullptr) continue; for (auto &conn : needle_cell->connections()) { @@ -341,10 +334,10 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit: bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right) { int left_idx = 0, right_idx = 0; - if (left->attributes.count(ID(extract_order)) > 0) - left_idx = left->attributes.at(ID(extract_order)).as_int(); - if (right->attributes.count(ID(extract_order)) > 0) - right_idx = right->attributes.at(ID(extract_order)).as_int(); + if (left->attributes.count(ID::extract_order) > 0) + left_idx = left->attributes.at(ID::extract_order).as_int(); + if (right->attributes.count(ID::extract_order) > 0) + right_idx = right->attributes.at(ID::extract_order).as_int(); if (left_idx != right_idx) return left_idx < right_idx; return left->name < right->name; @@ -587,7 +580,7 @@ struct ExtractPass : public Pass { if (map_filenames.empty() && mine_outfile.empty()) log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n"); - RTLIL::Design *map = NULL; + RTLIL::Design *map = nullptr; if (!mine_mode) { @@ -630,24 +623,24 @@ struct ExtractPass : public Pass { log_header(design, "Creating graphs for SubCircuit library.\n"); if (!mine_mode) - for (auto &mod_it : map->modules_) { + for (auto module : map->modules()) { SubCircuit::Graph mod_graph; - std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first); + std::string graph_name = "needle_" + RTLIL::unescape_id(module->name); log("Creating needle graph %s.\n", graph_name.c_str()); - if (module2graph(mod_graph, mod_it.second, constports)) { + if (module2graph(mod_graph, module, constports)) { solver.addGraph(graph_name, mod_graph); - needle_map[graph_name] = mod_it.second; - needle_list.push_back(mod_it.second); + needle_map[graph_name] = module; + needle_list.push_back(module); } } - for (auto &mod_it : design->modules_) { + for (auto module : design->modules()) { SubCircuit::Graph mod_graph; - std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first); + std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name); log("Creating haystack graph %s.\n", graph_name.c_str()); - if (module2graph(mod_graph, mod_it.second, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : NULL)) { + if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) { solver.addGraph(graph_name, mod_graph); - haystack_map[graph_name] = mod_it.second; + haystack_map[graph_name] = module; } } @@ -680,7 +673,7 @@ struct ExtractPass : public Pass { } RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result); design->select(haystack_map.at(result.haystackGraphId), new_cell); - log(" new cell: %s\n", id2cstr(new_cell->name)); + log(" new cell: %s\n", log_id(new_cell->name)); } } } @@ -697,12 +690,12 @@ struct ExtractPass : public Pass { for (auto &result: results) { log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits); - log(" primary match in %s:", id2cstr(haystack_map.at(result.graphId)->name)); + log(" primary match in %s:", log_id(haystack_map.at(result.graphId)->name)); for (auto &node : result.nodes) log(" %s", RTLIL::unescape_id(node.nodeId).c_str()); log("\n"); for (auto &it : result.matchesPerGraph) - log(" matches in %s: %d\n", id2cstr(haystack_map.at(it.first)->name), it.second); + log(" matches in %s: %d\n", log_id(haystack_map.at(it.first)->name), it.second); RTLIL::Module *mod = haystack_map.at(result.graphId); std::set<RTLIL::Cell*> cells; @@ -717,12 +710,12 @@ struct ExtractPass : public Pass { for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); for (auto &chunk : sig.chunks()) - if (chunk.wire != NULL) + if (chunk.wire != nullptr) wires.insert(chunk.wire); } RTLIL::Module *newMod = new RTLIL::Module; - newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); + newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, log_id(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); map->add(newMod); for (auto wire : wires) { @@ -739,8 +732,8 @@ struct ExtractPass : public Pass { for (auto &conn : cell->connections()) { std::vector<SigChunk> chunks = sigmap(conn.second); for (auto &chunk : chunks) - if (chunk.wire != NULL) - chunk.wire = newMod->wires_.at(chunk.wire->name); + if (chunk.wire != nullptr) + chunk.wire = newMod->wire(chunk.wire->name); newCell->setPort(conn.first, chunks); } } diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 639ae145b..68b338143 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -131,23 +131,23 @@ int counter_tryextract( SigMap& sigmap = index.sigmap; //Both inputs must be unsigned, so don't extract anything with a signed input - bool a_sign = cell->getParam(ID(A_SIGNED)).as_bool(); - bool b_sign = cell->getParam(ID(B_SIGNED)).as_bool(); + bool a_sign = cell->getParam(ID::A_SIGNED).as_bool(); + bool b_sign = cell->getParam(ID::B_SIGNED).as_bool(); if(a_sign || b_sign) return 3; //CO and X must be unconnected (exactly one connection to each port) - if(!is_unconnected(sigmap(cell->getPort(ID(CO))), index)) + if(!is_unconnected(sigmap(cell->getPort(ID::CO)), index)) return 7; - if(!is_unconnected(sigmap(cell->getPort(ID(X))), index)) + if(!is_unconnected(sigmap(cell->getPort(ID::X)), index)) return 8; //true if $alu is performing A - B, else A + B bool alu_is_subtract; //BI and CI must be both constant 0 or both constant 1 as well - const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI))); - const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI))); + const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID::BI)); + const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID::CI)); if(bi_port.is_fully_const() && bi_port.as_int() == 1 && ci_port.is_fully_const() && ci_port.as_int() == 1) { @@ -169,8 +169,8 @@ int counter_tryextract( if(alu_is_subtract) { - const int a_width = cell->getParam(ID(A_WIDTH)).as_int(); - const int b_width = cell->getParam(ID(B_WIDTH)).as_int(); + const int a_width = cell->getParam(ID::A_WIDTH).as_int(); + const int b_width = cell->getParam(ID::B_WIDTH).as_int(); const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B)); // down, cnt <= cnt - 1 @@ -197,8 +197,8 @@ int counter_tryextract( } else { - const int a_width = cell->getParam(ID(A_WIDTH)).as_int(); - const int b_width = cell->getParam(ID(B_WIDTH)).as_int(); + const int a_width = cell->getParam(ID::A_WIDTH).as_int(); + const int b_width = cell->getParam(ID::B_WIDTH).as_int(); const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A)); const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B)); @@ -245,9 +245,9 @@ int counter_tryextract( //Check if counter is an appropriate size int count_width; if (alu_port_use_a) - count_width = cell->getParam(ID(A_WIDTH)).as_int(); + count_width = cell->getParam(ID::A_WIDTH).as_int(); else - count_width = cell->getParam(ID(B_WIDTH)).as_int(); + count_width = cell->getParam(ID::B_WIDTH).as_int(); extract.width = count_width; if( (count_width < settings.minwidth) || (count_width > settings.maxwidth) ) return 1; @@ -283,7 +283,7 @@ int counter_tryextract( //S connection of the mux must come from an inverter if down, eq if up //(need not be the only load) - const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID(S))); + const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID::S)); extract.outsig = muxsel; pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux); Cell* overflow_cell = NULL; @@ -293,7 +293,7 @@ int counter_tryextract( continue; if(!extract.count_is_up && c->type != ID($logic_not)) continue; - if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID(S), true)) + if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID::S, true)) continue; overflow_cell = c; @@ -324,17 +324,17 @@ int counter_tryextract( return 24; count_reg = *cey_loads.begin(); - if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID(D)))) + if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID::D))) return 24; //Mux should have A driven by count Q, and B by muxy //if A and B are swapped, CE polarity is inverted if(sigmap(cemux->getPort(ID::B)) == muxy && - sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID(Q)))) + sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q))) { extract.ce_inverted = false; } else if(sigmap(cemux->getPort(ID::A)) == muxy && - sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID(Q)))) + sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q))) { extract.ce_inverted = true; } @@ -345,7 +345,7 @@ int counter_tryextract( //Select of the mux is our clock enable extract.has_ce = true; - extract.ce = sigmap(cemux->getPort(ID(S))); + extract.ce = sigmap(cemux->getPort(ID::S)); } else extract.has_ce = false; @@ -361,10 +361,10 @@ int counter_tryextract( extract.has_reset = true; //Check polarity of reset - we may have to add an inverter later on! - extract.rst_inverted = (count_reg->getParam(ID(ARST_POLARITY)).as_int() != 1); + extract.rst_inverted = (count_reg->getParam(ID::ARST_POLARITY).as_int() != 1); //Verify ARST_VALUE is zero or full scale - int rst_value = count_reg->getParam(ID(ARST_VALUE)).as_int(); + int rst_value = count_reg->getParam(ID::ARST_VALUE).as_int(); if(rst_value == 0) extract.rst_to_max = false; else if(rst_value == extract.count_value) @@ -373,7 +373,7 @@ int counter_tryextract( return 23; //Save the reset - extract.rst = sigmap(count_reg->getPort(ID(ARST))); + extract.rst = sigmap(count_reg->getPort(ID::ARST)); } //TODO: support synchronous reset else @@ -386,10 +386,10 @@ int counter_tryextract( return 16; if(extract.ce_inverted && !is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::A)) return 16; - if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID(D))) + if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID::D)) return 16; } - else if(!is_full_bus(muxy, index, count_mux, ID::Y, count_reg, ID(D))) + else if(!is_full_bus(muxy, index, count_mux, ID::Y, count_reg, ID::D)) return 16; //TODO: Verify count_reg CLK_POLARITY is 1 @@ -397,7 +397,7 @@ int counter_tryextract( //Register output must have exactly two loads, the inverter and ALU //(unless we have a parallel output!) //If we have a clock enable, 3 is OK - const RTLIL::SigSpec qport = count_reg->getPort(ID(Q)); + const RTLIL::SigSpec qport = count_reg->getPort(ID::Q); extract.poutsig = qport; extract.has_pout = false; const RTLIL::SigSpec cnout = sigmap(qport); @@ -450,12 +450,12 @@ int counter_tryextract( } if(!extract.count_is_up) { - if(!is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true)) + if(!is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true)) return 18; } else { - if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true)) + if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true)) { // B must be the overflow value const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B)); @@ -463,7 +463,7 @@ int counter_tryextract( return 12; extract.count_value = overflow.as_int(); } - else if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::B, true)) + else if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::B, true)) { // A must be the overflow value const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A)); @@ -476,21 +476,21 @@ int counter_tryextract( return 18; } } - if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true)) + if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID::Q, cell, ID::A, true)) return 19; - if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::B, true)) + if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID::Q, cell, ID::B, true)) return 19; //Look up the clock from the register - extract.clk = sigmap(count_reg->getPort(ID(CLK))); + extract.clk = sigmap(count_reg->getPort(ID::CLK)); if(!extract.count_is_up) { //Register output net must have an INIT attribute equal to the count value extract.rwire = cnout.as_wire(); - if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end()) + if(extract.rwire->attributes.find(ID::init) == extract.rwire->attributes.end()) return 20; - int rinit = extract.rwire->attributes[ID(init)].as_int(); + int rinit = extract.rwire->attributes[ID::init].as_int(); if(rinit != extract.count_value) return 21; } @@ -498,9 +498,9 @@ int counter_tryextract( { //Register output net must not have an INIT attribute or it must be zero extract.rwire = cnout.as_wire(); - if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end()) + if(extract.rwire->attributes.find(ID::init) == extract.rwire->attributes.end()) return 0; - int rinit = extract.rwire->attributes[ID(init)].as_int(); + int rinit = extract.rwire->attributes[ID::init].as_int(); if(rinit != 0) return 21; } @@ -534,7 +534,7 @@ void counter_worker( RTLIL::Wire* port_wire = port.as_wire(); bool force_extract = false; bool never_extract = false; - string count_reg_src = port_wire->attributes[ID(src)].decode_string().c_str(); + string count_reg_src = port_wire->attributes[ID::src].decode_string().c_str(); if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end()) { pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT)); @@ -618,16 +618,16 @@ void counter_worker( //Wipe all of the old connections to the ALU cell->unsetPort(ID::A); cell->unsetPort(ID::B); - cell->unsetPort(ID(BI)); - cell->unsetPort(ID(CI)); - cell->unsetPort(ID(CO)); - cell->unsetPort(ID(X)); + cell->unsetPort(ID::BI); + cell->unsetPort(ID::CI); + cell->unsetPort(ID::CO); + cell->unsetPort(ID::X); cell->unsetPort(ID::Y); - cell->unsetParam(ID(A_SIGNED)); - cell->unsetParam(ID(A_WIDTH)); - cell->unsetParam(ID(B_SIGNED)); - cell->unsetParam(ID(B_WIDTH)); - cell->unsetParam(ID(Y_WIDTH)); + cell->unsetParam(ID::A_SIGNED); + cell->unsetParam(ID::A_WIDTH); + cell->unsetParam(ID::B_SIGNED); + cell->unsetParam(ID::B_WIDTH); + cell->unsetParam(ID::Y_WIDTH); //Change the cell type cell->type = ID($__COUNT_); @@ -657,8 +657,8 @@ void counter_worker( //Hook up other stuff //cell->setParam(ID(CLKIN_DIVIDE), RTLIL::Const(1)); cell->setParam(ID(COUNT_TO), RTLIL::Const(extract.count_value)); - cell->setParam(ID(WIDTH), RTLIL::Const(extract.width)); - cell->setPort(ID(CLK), extract.clk); + cell->setParam(ID::WIDTH, RTLIL::Const(extract.width)); + cell->setPort(ID::CLK, extract.clk); cell->setPort(ID(OUT), extract.outsig); //Hook up clock enable @@ -747,7 +747,7 @@ void counter_worker( int newbits = ceil(log2(extract.count_value)); if(extract.width != newbits) { - cell->setParam(ID(WIDTH), RTLIL::Const(newbits)); + cell->setParam(ID::WIDTH, RTLIL::Const(newbits)); log(" Optimizing out %d unused high-order bits (new width is %d)\n", extract.width - newbits, newbits); diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 9f3bb525b..9023d8687 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -262,7 +262,7 @@ struct ExtractFaWorker pool<SigBit> new_leaves = leaves; new_leaves.erase(bit); - for (auto port : {ID::A, ID::B, ID(C), ID(D)}) { + for (auto port : {ID::A, ID::B, ID::C, ID::D}) { if (!cell->hasPort(port)) continue; auto bit = sigmap(SigBit(cell->getPort(port))); @@ -395,18 +395,18 @@ struct ExtractFaWorker else { Cell *cell = module->addCell(NEW_ID, ID($fa)); - cell->setParam(ID(WIDTH), 1); + cell->setParam(ID::WIDTH, 1); log(" Created $fa cell %s.\n", log_id(cell)); cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A); cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C); + cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C); X = module->addWire(NEW_ID); Y = module->addWire(NEW_ID); - cell->setPort(ID(X), X); + cell->setPort(ID::X, X); cell->setPort(ID::Y, Y); facache[fakey] = make_tuple(X, Y, cell); @@ -501,18 +501,18 @@ struct ExtractFaWorker else { Cell *cell = module->addCell(NEW_ID, ID($fa)); - cell->setParam(ID(WIDTH), 1); + cell->setParam(ID::WIDTH, 1); log(" Created $fa cell %s.\n", log_id(cell)); cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A); cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(ID(C), State::S0); + cell->setPort(ID::C, State::S0); X = module->addWire(NEW_ID); Y = module->addWire(NEW_ID); - cell->setPort(ID(X), X); + cell->setPort(ID::X, X); cell->setPort(ID::Y, Y); } diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 11cfddcd9..2d63e413f 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -286,7 +286,7 @@ struct ExtractReducePass : public Pass SigSpec input; for (auto b : input_pool) if (input_pool_intermed.count(b) == 0) - input.append_bit(b); + input.append(b); SigBit output = sigmap(head_cell->getPort(ID::Y)[0]); @@ -294,9 +294,9 @@ struct ExtractReducePass : public Pass gt == GateType::And ? ID($reduce_and) : gt == GateType::Or ? ID($reduce_or) : gt == GateType::Xor ? ID($reduce_xor) : ""); - new_reduce_cell->setParam(ID(A_SIGNED), 0); - new_reduce_cell->setParam(ID(A_WIDTH), input.size()); - new_reduce_cell->setParam(ID(Y_WIDTH), 1); + new_reduce_cell->setParam(ID::A_SIGNED, 0); + new_reduce_cell->setParam(ID::A_WIDTH, input.size()); + new_reduce_cell->setParam(ID::Y_WIDTH, 1); new_reduce_cell->setPort(ID::A, input); new_reduce_cell->setPort(ID::Y, output); diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index dda71f12a..269fe5c6c 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -90,7 +90,7 @@ struct ExtractinvPass : public Pass { auto cell_wire = cell_module->wire(port.first); if (!cell_wire) continue; - auto it = cell_wire->attributes.find("\\invertible_pin"); + auto it = cell_wire->attributes.find(ID::invertible_pin); if (it == cell_wire->attributes.end()) continue; IdString param_name = RTLIL::escape_id(it->second.decode_string()); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index a2ad87f7d..72947237b 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1405,7 +1405,7 @@ struct FlowmapWorker RTLIL::SigSpec lut_a, lut_y = node; for (auto input_node : input_nodes) - lut_a.append_bit(input_node); + lut_a.append(input_node); lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); @@ -1413,7 +1413,7 @@ struct FlowmapWorker for (auto gate_node : lut_gates[node]) { auto gate_origin = node_origins[gate_node]; - lut->add_strpool_attribute(ID(src), gate_origin.cell->get_strpool_attribute(ID(src))); + lut->add_strpool_attribute(ID::src, gate_origin.cell->get_strpool_attribute(ID::src)); packed_count++; } lut_count++; diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index 2173049b4..0686c0f2b 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -41,16 +41,16 @@ struct InsbufPass : public Pass { { log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n"); - std::string celltype = "$_BUF_", in_portname = "\\A", out_portname = "\\Y"; + IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-buf" && argidx+3 < args.size()) { - celltype = args[++argidx]; - in_portname = args[++argidx]; - out_portname = args[++argidx]; + celltype = RTLIL::escape_id(args[++argidx]); + in_portname = RTLIL::escape_id(args[++argidx]); + out_portname = RTLIL::escape_id(args[++argidx]); continue; } break; @@ -76,9 +76,9 @@ struct InsbufPass : public Pass { continue; } - Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->setPort(RTLIL::escape_id(in_portname), rhs); - cell->setPort(RTLIL::escape_id(out_portname), lhs); + Cell *cell = module->addCell(NEW_ID, celltype); + cell->setPort(in_portname, rhs); + cell->setPort(out_portname, lhs); log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs)); } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index f63012d1a..a18d02652 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -203,7 +203,7 @@ struct IopadmapPass : public Pass { // Collect explicitly-marked already-buffered SigBits. for (auto wire : module->wires()) - if (wire->get_bool_attribute("\\iopad_external_pin") || ignore.count(make_pair(module->name, wire->name))) + if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(module->name, wire->name))) for (int i = 0; i < GetSize(wire); i++) buf_bits.insert(sigmap(SigBit(wire, i))); @@ -229,11 +229,13 @@ struct IopadmapPass : public Pass { for (auto module : design->selected_modules()) { dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits; + pool<SigSig> remove_conns; if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty()) { dict<SigBit, Cell *> tbuf_bits; pool<SigBit> driven_bits; + dict<SigBit, SigSig> z_conns; // Gather tristate buffers and always-on drivers. for (auto cell : module->cells()) @@ -252,8 +254,10 @@ struct IopadmapPass : public Pass { for (int i = 0; i < GetSize(conn.first); i++) { SigBit dstbit = conn.first[i]; SigBit srcbit = conn.second[i]; - if (!srcbit.wire && srcbit.data == State::Sz) + if (!srcbit.wire && srcbit.data == State::Sz) { + z_conns[dstbit] = conn; continue; + } driven_bits.insert(dstbit); } @@ -287,7 +291,7 @@ struct IopadmapPass : public Pass { if (tbuf_cell != nullptr) { // Found a tristate buffer — use it. - en_sig = tbuf_cell->getPort(ID(E)).as_bit(); + en_sig = tbuf_cell->getPort(ID::E).as_bit(); data_sig = tbuf_cell->getPort(ID::A).as_bit(); } else if (is_driven) { // No tristate buffer, but an always-on driver is present. @@ -302,13 +306,17 @@ struct IopadmapPass : public Pass { // enable. en_sig = SigBit(State::S0); data_sig = SigBit(State::Sx); + if (z_conns.count(wire_bit)) + remove_conns.insert(z_conns[wire_bit]); } if (wire->port_input) { log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str()); - Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype)); + Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), + RTLIL::escape_id(tinoutpad_celltype)); cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig); cell->attributes[ID::keep] = RTLIL::Const(1); @@ -328,7 +336,9 @@ struct IopadmapPass : public Pass { } else { log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str()); - Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype)); + Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), + RTLIL::escape_id(toutpad_celltype)); cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig); @@ -406,7 +416,9 @@ struct IopadmapPass : public Pass { SigBit wire_bit(wire, i); - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); + RTLIL::Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))), + RTLIL::escape_id(celltype)); cell->setPort(RTLIL::escape_id(portname_int), wire_bit); if (!portname_pad.empty()) @@ -420,12 +432,16 @@ struct IopadmapPass : public Pass { } else { - RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); + RTLIL::Cell *cell = module->addCell( + module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))), + RTLIL::escape_id(celltype)); cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire)); if (!portname_pad.empty()) { RTLIL::Wire *new_wire = NULL; - new_wire = module->addWire(NEW_ID, wire); + new_wire = module->addWire( + module->uniquify(stringf("$iopadmap$%s", log_id(wire))), + wire); module->swap_names(new_wire, wire); wire->attributes.clear(); cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire)); @@ -444,9 +460,19 @@ struct IopadmapPass : public Pass { } } + if (!remove_conns.empty()) { + std::vector<SigSig> new_conns; + for (auto &conn : module->connections()) + if (!remove_conns.count(conn)) + new_conns.push_back(conn); + module->new_connections(new_conns); + } + for (auto &it : rewrite_bits) { RTLIL::Wire *wire = it.first; - RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire); + RTLIL::Wire *new_wire = module->addWire( + module->uniquify(stringf("$iopadmap$%s", log_id(wire))), + wire); module->swap_names(new_wire, wire); wire->attributes.clear(); for (int i = 0; i < wire->width; i++) @@ -464,10 +490,10 @@ struct IopadmapPass : public Pass { } if (wire->port_output) { - auto jt = new_wire->attributes.find(ID(init)); + auto jt = new_wire->attributes.find(ID::init); // For output ports, move \init attributes from old wire to new wire if (jt != new_wire->attributes.end()) { - wire->attributes[ID(init)] = std::move(jt->second); + wire->attributes[ID::init] = std::move(jt->second); new_wire->attributes.erase(jt); } } diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index c6618fc9d..703bf6ff6 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -27,7 +27,7 @@ int lut2mux(Cell *cell) { SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_y = cell->getPort(ID::Y); - Const lut = cell->getParam(ID(LUT)); + Const lut = cell->getParam(ID::LUT); int count = 1; if (GetSize(sig_a) == 1) diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 09f61927c..3bb929009 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -112,12 +112,12 @@ struct MaccmapWorker RTLIL::Wire *w2 = module->addWire(NEW_ID, width); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::A, in1); cell->setPort(ID::B, in2); - cell->setPort(ID(C), in3); + cell->setPort(ID::C, in3); cell->setPort(ID::Y, w1); - cell->setPort(ID(X), w2); + cell->setPort(ID::X, w2); out1 = {out_zeros_msb, w1, out_zeros_lsb}; out2 = {out_zeros_msb, w2, out_zeros_lsb}; @@ -240,15 +240,15 @@ struct MaccmapWorker RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu)); c->setPort(ID::A, summands.front()); c->setPort(ID::B, summands.back()); - c->setPort(ID(CI), State::S0); - c->setPort(ID(BI), State::S0); + c->setPort(ID::CI, State::S0); + c->setPort(ID::BI, State::S0); c->setPort(ID::Y, module->addWire(NEW_ID, width)); - c->setPort(ID(X), module->addWire(NEW_ID, width)); - c->setPort(ID(CO), module->addWire(NEW_ID, width)); + c->setPort(ID::X, module->addWire(NEW_ID, width)); + c->setPort(ID::CO, module->addWire(NEW_ID, width)); c->fixup_parameters(); if (!tree_sum_bits.empty()) { - c->setPort(ID(CI), tree_sum_bits.back()); + c->setPort(ID::CI, tree_sum_bits.back()); tree_sum_bits.pop_back(); } log_assert(tree_sum_bits.empty()); diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 5541b6122..bd049d86d 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -116,7 +116,7 @@ struct MuxcoverWorker if (!cell->input(conn.first)) continue; for (auto bit : sigmap(conn.second)) { - if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID(S)) + if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID::S) roots.insert(bit); used_once.insert(bit); } @@ -519,7 +519,7 @@ struct MuxcoverWorker Cell *cell = module->addCell(NEW_ID, ID($_MUX_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID(S), mux.selects[0]); + cell->setPort(ID::S, mux.selects[0]); cell->setPort(ID::Y, bit); return; } @@ -529,10 +529,10 @@ struct MuxcoverWorker Cell *cell = module->addCell(NEW_ID, ID($_MUX4_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID(C), mux.inputs[2]); - cell->setPort(ID(D), mux.inputs[3]); - cell->setPort(ID(S), mux.selects[0]); - cell->setPort(ID(T), mux.selects[1]); + cell->setPort(ID::C, mux.inputs[2]); + cell->setPort(ID::D, mux.inputs[3]); + cell->setPort(ID::S, mux.selects[0]); + cell->setPort(ID::T, mux.selects[1]); cell->setPort(ID::Y, bit); return; } @@ -542,15 +542,15 @@ struct MuxcoverWorker Cell *cell = module->addCell(NEW_ID, ID($_MUX8_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID(C), mux.inputs[2]); - cell->setPort(ID(D), mux.inputs[3]); - cell->setPort(ID(E), mux.inputs[4]); - cell->setPort(ID(F), mux.inputs[5]); - cell->setPort(ID(G), mux.inputs[6]); - cell->setPort(ID(H), mux.inputs[7]); - cell->setPort(ID(S), mux.selects[0]); - cell->setPort(ID(T), mux.selects[1]); - cell->setPort(ID(U), mux.selects[2]); + cell->setPort(ID::C, mux.inputs[2]); + cell->setPort(ID::D, mux.inputs[3]); + cell->setPort(ID::E, mux.inputs[4]); + cell->setPort(ID::F, mux.inputs[5]); + cell->setPort(ID::G, mux.inputs[6]); + cell->setPort(ID::H, mux.inputs[7]); + cell->setPort(ID::S, mux.selects[0]); + cell->setPort(ID::T, mux.selects[1]); + cell->setPort(ID::U, mux.selects[2]); cell->setPort(ID::Y, bit); return; } @@ -560,24 +560,24 @@ struct MuxcoverWorker Cell *cell = module->addCell(NEW_ID, ID($_MUX16_)); cell->setPort(ID::A, mux.inputs[0]); cell->setPort(ID::B, mux.inputs[1]); - cell->setPort(ID(C), mux.inputs[2]); - cell->setPort(ID(D), mux.inputs[3]); - cell->setPort(ID(E), mux.inputs[4]); - cell->setPort(ID(F), mux.inputs[5]); - cell->setPort(ID(G), mux.inputs[6]); - cell->setPort(ID(H), mux.inputs[7]); - cell->setPort(ID(I), mux.inputs[8]); - cell->setPort(ID(J), mux.inputs[9]); - cell->setPort(ID(K), mux.inputs[10]); - cell->setPort(ID(L), mux.inputs[11]); - cell->setPort(ID(M), mux.inputs[12]); - cell->setPort(ID(N), mux.inputs[13]); - cell->setPort(ID(O), mux.inputs[14]); - cell->setPort(ID(P), mux.inputs[15]); - cell->setPort(ID(S), mux.selects[0]); - cell->setPort(ID(T), mux.selects[1]); - cell->setPort(ID(U), mux.selects[2]); - cell->setPort(ID(V), mux.selects[3]); + cell->setPort(ID::C, mux.inputs[2]); + cell->setPort(ID::D, mux.inputs[3]); + cell->setPort(ID::E, mux.inputs[4]); + cell->setPort(ID::F, mux.inputs[5]); + cell->setPort(ID::G, mux.inputs[6]); + cell->setPort(ID::H, mux.inputs[7]); + cell->setPort(ID::I, mux.inputs[8]); + cell->setPort(ID::J, mux.inputs[9]); + cell->setPort(ID::K, mux.inputs[10]); + cell->setPort(ID::L, mux.inputs[11]); + cell->setPort(ID::M, mux.inputs[12]); + cell->setPort(ID::N, mux.inputs[13]); + cell->setPort(ID::O, mux.inputs[14]); + cell->setPort(ID::P, mux.inputs[15]); + cell->setPort(ID::S, mux.selects[0]); + cell->setPort(ID::T, mux.selects[1]); + cell->setPort(ID::U, mux.selects[2]); + cell->setPort(ID::V, mux.selects[3]); cell->setPort(ID::Y, bit); return; } diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index 31ab13cec..2810b7f2d 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -93,7 +93,7 @@ struct PmuxtreePass : public Pass { continue; SigSpec sig_data = cell->getPort(ID::B); - SigSpec sig_sel = cell->getPort(ID(S)); + SigSpec sig_sel = cell->getPort(ID::S); if (!cell->getPort(ID::A).is_fully_undef()) { sig_data.append(cell->getPort(ID::A)); diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index be00e5030..d7a381e0a 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -71,12 +71,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech bool fixup(Cell *cell, dict<int, SigBit> &taps) { - auto D = cell->getPort(ID(D)); - auto C = cell->getPort(ID(C)); + auto D = cell->getPort(ID::D); + auto C = cell->getPort(ID::C); auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG)); newcell->setPort(ID(nRST), State::S1); - newcell->setPort(ID(CLK), C); + newcell->setPort(ID::CLK, C); newcell->setPort(ID(IN), D); int i = 0; @@ -117,9 +117,9 @@ struct ShregmapWorker sigbit_with_non_chain_users.insert(bit); } - if (wire->attributes.count(ID(init))) { + if (wire->attributes.count(ID::init)) { SigSpec initsig = sigmap(wire); - Const initval = wire->attributes.at(ID(init)); + Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) if (initval[i] == State::S0 && !opts.zinit) sigbit_init[initsig[i]] = false; @@ -319,7 +319,7 @@ struct ShregmapWorker initval.push_back(State::S0); remove_init.insert(bit); } - first_cell->setParam(ID(INIT), initval); + first_cell->setParam(ID::INIT, initval); } if (opts.zinit) @@ -348,7 +348,7 @@ struct ShregmapWorker first_cell->type = shreg_cell_type_str; first_cell->setPort(q_port, last_cell->getPort(q_port)); - first_cell->setParam(ID(DEPTH), depth); + first_cell->setParam(ID::DEPTH, depth); if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) remove_cells.insert(first_cell); @@ -366,18 +366,18 @@ struct ShregmapWorker for (auto wire : module->wires()) { - if (wire->attributes.count(ID(init)) == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec initsig = sigmap(wire); - Const &initval = wire->attributes.at(ID(init)); + Const &initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) if (remove_init.count(initsig[i])) initval[i] = State::Sx; if (SigSpec(initval).is_fully_undef()) - wire->attributes.erase(ID(init)); + wire->attributes.erase(ID::init); } remove_cells.clear(); @@ -548,19 +548,19 @@ struct ShregmapPass : public Pass { bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none"; if (clk_pos && en_none) - opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); + opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q)); if (clk_neg && en_none) - opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); + opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q)); if (clk_pos && en_pos) - opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); + opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q)); if (clk_pos && en_neg) - opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); + opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q)); if (clk_neg && en_pos) - opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); + opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q)); if (clk_neg && en_neg) - opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q))); + opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q)); if (en_pos || en_neg) opts.ffe = true; diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 91574f3c6..b65b3e972 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -31,11 +31,11 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); - sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool()); + sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); } @@ -46,7 +46,7 @@ void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); - sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool()); + sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); module->connect(RTLIL::SigSig(sig_y, sig_a)); } @@ -57,8 +57,8 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_b = cell->getPort(ID::B); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); - sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool()); - sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID(B_SIGNED)).as_bool()); + sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); + sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); if (cell->type == ID($xnor)) { @@ -66,7 +66,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_t[i]); gate->setPort(ID::Y, sig_y[i]); } @@ -83,7 +83,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::Y, sig_y[i]); @@ -134,7 +134,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -147,7 +147,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($reduce_xnor)) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); last_output_cell = gate; @@ -175,7 +175,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig[i]); gate->setPort(ID::B, sig[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -204,7 +204,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); } @@ -233,7 +233,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); gate->setPort(ID::Y, sig_y); @@ -244,24 +244,24 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_b = cell->getPort(ID::B); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); - bool is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool(); + bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); bool is_ne = cell->type.in(ID($ne), ID($nex)); RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); - xor_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); - reduce_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); - not_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); simplemap_lognot(module, not_cell); module->remove(not_cell); } @@ -275,10 +275,10 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); - gate->setPort(ID(S), cell->getPort(ID(S))); + gate->setPort(ID::S, cell->getPort(ID::S)); gate->setPort(ID::Y, sig_y[i]); } } @@ -286,14 +286,14 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec sig_a = cell->getPort(ID::A); - RTLIL::SigSpec sig_e = cell->getPort(ID(EN)); + RTLIL::SigSpec sig_e = cell->getPort(ID::EN); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, sig_a[i]); - gate->setPort(ID(E), sig_e); + gate->setPort(ID::E, sig_e); gate->setPort(ID::Y, sig_y[i]); } } @@ -301,18 +301,18 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) { SigSpec lut_ctrl = cell->getPort(ID::A); - SigSpec lut_data = cell->getParam(ID(LUT)); - lut_data.extend_u0(1 << cell->getParam(ID(WIDTH)).as_int()); + SigSpec lut_data = cell->getParam(ID::LUT); + lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int()); for (int idx = 0; GetSize(lut_data) > 1; idx++) { SigSpec sig_s = lut_ctrl[idx]; SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); gate->setPort(ID::A, lut_data[i]); gate->setPort(ID::B, lut_data[i+1]); - gate->setPort(ID(S), lut_ctrl[idx]); + gate->setPort(ID::S, lut_ctrl[idx]); gate->setPort(ID::Y, new_lut_data[i/2]); } lut_data = new_lut_data; @@ -324,10 +324,10 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) { SigSpec ctrl = cell->getPort(ID::A); - SigSpec table = cell->getParam(ID(TABLE)); + SigSpec table = cell->getParam(ID::TABLE); - int width = cell->getParam(ID(WIDTH)).as_int(); - int depth = cell->getParam(ID(DEPTH)).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int depth = cell->getParam(ID::DEPTH).as_int(); table.extend_u0(2 * width * depth); SigSpec products; @@ -353,7 +353,7 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) { - int offset = cell->parameters.at(ID(OFFSET)).as_int(); + int offset = cell->parameters.at(ID::OFFSET).as_int(); RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); @@ -369,156 +369,156 @@ void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N'; - char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N'; + int width = cell->parameters.at(ID::WIDTH).as_int(); + char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N'; + char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_s = cell->getPort(ID(SET)); - RTLIL::SigSpec sig_r = cell->getPort(ID(CLR)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_s = cell->getPort(ID::SET); + RTLIL::SigSpec sig_r = cell->getPort(ID::CLR); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); - gate->setPort(ID(S), sig_s[i]); - gate->setPort(ID(R), sig_r[i]); - gate->setPort(ID(Q), sig_q[i]); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::S, sig_s[i]); + gate->setPort(ID::R, sig_r[i]); + gate->setPort(ID::Q, sig_q[i]); } } void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); + int width = cell->parameters.at(ID::WIDTH).as_int(); - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); IdString gate_type = ID($_FF_); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); - gate->setPort(ID(D), sig_d[i]); - gate->setPort(ID(Q), sig_q[i]); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::D, sig_d[i]); + gate->setPort(ID::Q, sig_q[i]); } } void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N'; + int width = cell->parameters.at(ID::WIDTH).as_int(); + char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK)); - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); IdString gate_type = stringf("$_DFF_%c_", clk_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); - gate->setPort(ID(C), sig_clk); - gate->setPort(ID(D), sig_d[i]); - gate->setPort(ID(Q), sig_q[i]); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::C, sig_clk); + gate->setPort(ID::D, sig_d[i]); + gate->setPort(ID::Q, sig_q[i]); } } void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N'; - char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N'; + int width = cell->parameters.at(ID::WIDTH).as_int(); + char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N'; + char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK)); - RTLIL::SigSpec sig_en = cell->getPort(ID(EN)); - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK); + RTLIL::SigSpec sig_en = cell->getPort(ID::EN); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); IdString gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); - gate->setPort(ID(C), sig_clk); - gate->setPort(ID(E), sig_en); - gate->setPort(ID(D), sig_d[i]); - gate->setPort(ID(Q), sig_q[i]); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::C, sig_clk); + gate->setPort(ID::E, sig_en); + gate->setPort(ID::D, sig_d[i]); + gate->setPort(ID::Q, sig_q[i]); } } void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N'; - char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N'; - char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N'; + int width = cell->parameters.at(ID::WIDTH).as_int(); + char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N'; + char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N'; + char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK)); - RTLIL::SigSpec sig_s = cell->getPort(ID(SET)); - RTLIL::SigSpec sig_r = cell->getPort(ID(CLR)); - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK); + RTLIL::SigSpec sig_s = cell->getPort(ID::SET); + RTLIL::SigSpec sig_r = cell->getPort(ID::CLR); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); IdString gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); - gate->setPort(ID(C), sig_clk); - gate->setPort(ID(S), sig_s[i]); - gate->setPort(ID(R), sig_r[i]); - gate->setPort(ID(D), sig_d[i]); - gate->setPort(ID(Q), sig_q[i]); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::C, sig_clk); + gate->setPort(ID::S, sig_s[i]); + gate->setPort(ID::R, sig_r[i]); + gate->setPort(ID::D, sig_d[i]); + gate->setPort(ID::Q, sig_q[i]); } } void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N'; - char rst_pol = cell->parameters.at(ID(ARST_POLARITY)).as_bool() ? 'P' : 'N'; + int width = cell->parameters.at(ID::WIDTH).as_int(); + char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N'; + char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N'; - std::vector<RTLIL::State> rst_val = cell->parameters.at(ID(ARST_VALUE)).bits; + std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits; while (int(rst_val.size()) < width) rst_val.push_back(RTLIL::State::S0); - RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK)); - RTLIL::SigSpec sig_rst = cell->getPort(ID(ARST)); - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK); + RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); IdString gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol); IdString gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); - gate->setPort(ID(C), sig_clk); - gate->setPort(ID(R), sig_rst); - gate->setPort(ID(D), sig_d[i]); - gate->setPort(ID(Q), sig_q[i]); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::C, sig_clk); + gate->setPort(ID::R, sig_rst); + gate->setPort(ID::D, sig_d[i]); + gate->setPort(ID::Q, sig_q[i]); } } void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N'; + int width = cell->parameters.at(ID::WIDTH).as_int(); + char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_en = cell->getPort(ID(EN)); - RTLIL::SigSpec sig_d = cell->getPort(ID(D)); - RTLIL::SigSpec sig_q = cell->getPort(ID(Q)); + RTLIL::SigSpec sig_en = cell->getPort(ID::EN); + RTLIL::SigSpec sig_d = cell->getPort(ID::D); + RTLIL::SigSpec sig_q = cell->getPort(ID::Q); IdString gate_type = stringf("$_DLATCH_%c_", en_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src))); - gate->setPort(ID(E), sig_en); - gate->setPort(ID(D), sig_d[i]); - gate->setPort(ID(Q), sig_q[i]); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::E, sig_en); + gate->setPort(ID::D, sig_d[i]); + gate->setPort(ID::Q, sig_q[i]); } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0c57733d4..518afa1a7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -146,7 +146,7 @@ struct TechmapWorker record.value = it.second; result[p].push_back(record); it.second->attributes[ID::keep] = RTLIL::Const(1); - it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1); + it.second->attributes[ID::_techmap_special_] = RTLIL::Const(1); } } @@ -175,12 +175,12 @@ struct TechmapWorker } std::string orig_cell_name; - pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src)); + pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src); + orig_cell_name = cell->name.str(); if (!flatten_mode) { for (auto &it : tpl->cells_) - if (it.first == ID(_TECHMAP_REPLACE_)) { - orig_cell_name = cell->name.str(); + if (it.first == ID::_TECHMAP_REPLACE_) { module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); break; } @@ -197,8 +197,8 @@ struct TechmapWorker m->start_offset = it.second->start_offset; m->size = it.second->size; m->attributes = it.second->attributes; - if (m->attributes.count(ID(src))) - m->add_strpool_attribute(ID(src), extra_src_attrs); + if (m->attributes.count(ID::src)) + m->add_strpool_attribute(ID::src, extra_src_attrs); module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); @@ -215,7 +215,7 @@ struct TechmapWorker IdString posportname = stringf("$%d", it.second->port_id); positional_ports[posportname] = it.first; - if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) && + if (!flatten_mode && it.second->get_bool_attribute(ID::techmap_autopurge) && (!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) && (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) { @@ -231,12 +231,12 @@ struct TechmapWorker apply_prefix(cell->name, w_name); RTLIL::Wire *w = module->wire(w_name); if (w != nullptr) { - if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) { + if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) { temp_renamed_wires[w] = w->name; module->rename(w, NEW_ID); w = nullptr; } else { - w->attributes.erase(ID(hierconn)); + w->attributes.erase(ID::hierconn); if (GetSize(w) < GetSize(it.second)) { log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); @@ -250,11 +250,11 @@ struct TechmapWorker w->port_output = false; w->port_id = 0; if (!flatten_mode) - w->attributes.erase(ID(techmap_autopurge)); - if (it.second->get_bool_attribute(ID(_techmap_special_))) + w->attributes.erase(ID::techmap_autopurge); + if (it.second->get_bool_attribute(ID::_techmap_special_)) w->attributes.clear(); - if (w->attributes.count(ID(src))) - w->add_strpool_attribute(ID(src), extra_src_attrs); + if (w->attributes.count(ID::src)) + w->add_strpool_attribute(ID::src, extra_src_attrs); } design->select(module, w); @@ -363,7 +363,7 @@ struct TechmapWorker } for (auto &attr : w->attributes) { - if (attr.first == ID(src)) + if (attr.first == ID::src) continue; auto lhs = GetSize(extra_connect.first); auto rhs = GetSize(extra_connect.second); @@ -380,7 +380,7 @@ struct TechmapWorker for (auto &it : tpl->cells_) { IdString c_name = it.second->name.str(); - bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_)); + bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_); if (techmap_replace_cell) c_name = orig_cell_name; @@ -421,19 +421,19 @@ struct TechmapWorker c->unsetPort(it2); if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) { - IdString memid = c->getParam(ID(MEMID)).decode_string(); + IdString memid = c->getParam(ID::MEMID).decode_string(); log_assert(memory_renames.count(memid) != 0); - c->setParam(ID(MEMID), Const(memory_renames[memid].str())); + c->setParam(ID::MEMID, Const(memory_renames[memid].str())); } if (c->type == ID($mem)) { - IdString memid = c->getParam(ID(MEMID)).decode_string(); + IdString memid = c->getParam(ID::MEMID).decode_string(); apply_prefix(cell->name, memid); - c->setParam(ID(MEMID), Const(memid.c_str())); + c->setParam(ID::MEMID, Const(memid.c_str())); } - if (c->attributes.count(ID(src))) - c->add_strpool_attribute(ID(src), extra_src_attrs); + if (c->attributes.count(ID::src)) + c->add_strpool_attribute(ID::src, extra_src_attrs); if (techmap_replace_cell) for (auto attr : cell->attributes) @@ -481,8 +481,8 @@ struct TechmapWorker pool<SigBit> remove_init_bits; for (auto wire : module->wires()) { - if (wire->attributes.count("\\init")) { - Const value = wire->attributes.at("\\init"); + if (wire->attributes.count(ID::init)) { + Const value = wire->attributes.at(ID::init); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) if (value[i] != State::Sx) init_bits[sigmap(SigBit(wire, i))] = value[i]; @@ -509,9 +509,9 @@ struct TechmapWorker } if (flatten_mode) { - bool keepit = cell->get_bool_attribute(ID(keep_hierarchy)); + bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); for (auto &tpl_name : celltypeMap.at(cell_type)) - if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy))) + if (map->modules_[tpl_name]->get_bool_attribute(ID::keep_hierarchy)) keepit = true; if (keepit) { if (!flatten_keep_list[cell]) { @@ -577,13 +577,13 @@ struct TechmapWorker { std::string extmapper_name; - if (tpl->get_bool_attribute(ID(techmap_simplemap))) + if (tpl->get_bool_attribute(ID::techmap_simplemap)) extmapper_name = "simplemap"; - if (tpl->get_bool_attribute(ID(techmap_maccmap))) + if (tpl->get_bool_attribute(ID::techmap_maccmap)) extmapper_name = "maccmap"; - if (tpl->attributes.count(ID(techmap_wrap))) + if (tpl->attributes.count(ID::techmap_wrap)) extmapper_name = "wrap"; if (!extmapper_name.empty()) @@ -598,7 +598,7 @@ struct TechmapWorker m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); if (extmapper_name == "wrap") - m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string()); + m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string()); RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; RTLIL::Module *extmapper_module = extmapper_design->module(m_name); @@ -613,7 +613,7 @@ struct TechmapWorker int port_counter = 1; for (auto &c : extmapper_cell->connections_) { RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); - if (w->name.in(ID::Y, ID(Q))) + if (w->name.in(ID::Y, ID::Q)) w->port_output = true; else w->port_input = true; @@ -641,7 +641,7 @@ struct TechmapWorker } if (extmapper_name == "wrap") { - std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string(); + std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); mkdebug.on(); Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); @@ -709,8 +709,8 @@ struct TechmapWorker continue; } - if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0) - parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type); + if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) + parameters[ID::_TECHMAP_CELLTYPE_] = RTLIL::unescape_id(cell->type); for (auto conn : cell->connections()) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) { @@ -760,8 +760,8 @@ struct TechmapWorker bits = i; // Increment index by one to get number of bits bits++; - if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_))) - parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits; + if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_)) + parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits; for (auto conn : cell->connections()) if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { @@ -906,8 +906,8 @@ struct TechmapWorker RTLIL::SigSig port_conn; for (auto &it : port_connmap) { - port_conn.first.append_bit(it.first); - port_conn.second.append_bit(it.second); + port_conn.first.append(it.first); + port_conn.second.append(it.second); } tpl->connect(port_conn); @@ -1030,8 +1030,8 @@ struct TechmapWorker if (!remove_init_bits.empty()) { for (auto wire : module->wires()) - if (wire->attributes.count("\\init")) { - Const &value = wire->attributes.at("\\init"); + if (wire->attributes.count(ID::init)) { + Const &value = wire->attributes.at(ID::init); bool do_cleanup = true; for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { SigBit bit = sigmap(SigBit(wire, i)); @@ -1042,7 +1042,7 @@ struct TechmapWorker } if (do_cleanup) { log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); } } } @@ -1302,8 +1302,8 @@ struct TechmapPass : public Pass { std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap; for (auto &it : map->modules_) { - if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) { - char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str()); + if (it.second->attributes.count(ID::techmap_celltype) && !it.second->attributes.at(ID::techmap_celltype).bits.empty()) { + char *p = strdup(it.second->attributes.at(ID::techmap_celltype).decode_string().c_str()); for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n")) celltypeMap[RTLIL::escape_id(q)].insert(it.first); free(p); @@ -1389,7 +1389,7 @@ struct FlattenPass : public Pass { RTLIL::Module *top_mod = NULL; if (design->full_selection()) for (auto mod : design->modules()) - if (mod->get_bool_attribute(ID(top))) + if (mod->get_bool_attribute(ID::top)) top_mod = mod; std::set<RTLIL::Cell*> handled_cells; diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index decf9a202..90f3a9d6f 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -71,7 +71,7 @@ struct TribufWorker { if (cell->type.in(ID($mux), ID($_MUX_))) { - IdString en_port = cell->type == ID($mux) ? ID(EN) : ID(E); + IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E; IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_); if (is_all_z(cell->getPort(ID::A)) && is_all_z(cell->getPort(ID::B))) { @@ -81,9 +81,9 @@ struct TribufWorker { if (is_all_z(cell->getPort(ID::A))) { cell->setPort(ID::A, cell->getPort(ID::B)); - cell->setPort(en_port, cell->getPort(ID(S))); + cell->setPort(en_port, cell->getPort(ID::S)); cell->unsetPort(ID::B); - cell->unsetPort(ID(S)); + cell->unsetPort(ID::S); cell->type = tri_type; tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell); module->design->scratchpad_set_bool("tribuf.added_something", true); @@ -91,9 +91,9 @@ struct TribufWorker { } if (is_all_z(cell->getPort(ID::B))) { - cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID(S)))); + cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S))); cell->unsetPort(ID::B); - cell->unsetPort(ID(S)); + cell->unsetPort(ID::S); cell->type = tri_type; tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell); module->design->scratchpad_set_bool("tribuf.added_something", true); @@ -121,9 +121,9 @@ struct TribufWorker { SigSpec pmux_b, pmux_s; for (auto cell : it.second) { if (cell->type == ID($tribuf)) - pmux_s.append(cell->getPort(ID(EN))); + pmux_s.append(cell->getPort(ID::EN)); else - pmux_s.append(cell->getPort(ID(E))); + pmux_s.append(cell->getPort(ID::E)); pmux_b.append(cell->getPort(ID::A)); module->remove(cell); } diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index ac3d4ed4a..a427c4987 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -62,12 +62,12 @@ struct ZinitPass : public Pass { for (auto wire : module->selected_wires()) { - if (wire->attributes.count(ID(init)) == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec wirebits = sigmap(wire); - Const initval = wire->attributes.at(ID(init)); - wire->attributes.erase(ID(init)); + Const initval = wire->attributes.at(ID::init); + wire->attributes.erase(ID::init); for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) { @@ -103,8 +103,8 @@ struct ZinitPass : public Pass { if (!dff_types.count(cell->type)) continue; - SigSpec sig_d = sigmap(cell->getPort(ID(D))); - SigSpec sig_q = sigmap(cell->getPort(ID(Q))); + SigSpec sig_d = sigmap(cell->getPort(ID::D)); + SigSpec sig_q = sigmap(cell->getPort(ID::Q)); if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1) continue; @@ -120,14 +120,14 @@ struct ZinitPass : public Pass { } Wire *initwire = module->addWire(NEW_ID, GetSize(initval)); - initwire->attributes[ID(init)] = initval; + initwire->attributes[ID::init] = initval; for (int i = 0; i < GetSize(initwire); i++) if (initval.bits.at(i) == State::S1) { sig_d[i] = module->NotGate(NEW_ID, sig_d[i]); module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]); - initwire->attributes[ID(init)].bits.at(i) = State::S0; + initwire->attributes[ID::init].bits.at(i) = State::S0; } else { @@ -137,8 +137,8 @@ struct ZinitPass : public Pass { log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type), log_signal(sig_q), log_signal(initval)); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), initwire); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, initwire); } for (auto &it : initbits) diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 5d5466afe..894610e2b 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -55,7 +55,7 @@ static void test_abcloop() while (1) { - module = design->addModule("\\uut"); + module = design->addModule(ID(UUT)); create_cycles++; in_sig = {}; diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 2b6a86c25..42e8a61ea 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -85,7 +85,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("reg [31:0] xorshift128_x = 123456789;\n"); f << stringf("reg [31:0] xorshift128_y = 362436069;\n"); f << stringf("reg [31:0] xorshift128_z = 521288629;\n"); - f << stringf("reg [31:0] xorshift128_w = %u; // <-- seed value\n", seed ? seed : int(time(NULL))); + f << stringf("reg [31:0] xorshift128_w = %u; // <-- seed value\n", seed ? seed : int(time(nullptr))); f << stringf("reg [31:0] xorshift128_t;\n\n"); f << stringf("task xorshift128;\n"); f << stringf("begin\n"); @@ -97,29 +97,26 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("end\n"); f << stringf("endtask\n\n"); - for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) + for (auto mod : design->modules()) { std::map<std::string, int> signal_in; std::map<std::string, std::string> signal_const; std::map<std::string, int> signal_clk; std::map<std::string, int> signal_out; - RTLIL::Module *mod = it->second; - - if (mod->get_bool_attribute("\\gentb_skip")) + if (mod->get_bool_attribute(ID::gentb_skip)) continue; int count_ports = 0; - log("Generating test bench for module `%s'.\n", it->first.c_str()); - for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); ++it2) { - RTLIL::Wire *wire = it2->second; + log("Generating test bench for module `%s'.\n", mod->name.c_str()); + for (auto wire : mod->wires()) { if (wire->port_output) { count_ports++; signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width; f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } else if (wire->port_input) { count_ports++; - bool is_clksignal = wire->get_bool_attribute("\\gentb_clock"); + bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock); for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); ++it3) for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); ++it4) { if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1) @@ -129,19 +126,18 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s if (c.wire == wire) is_clksignal = true; } - if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { + if (is_clksignal && wire->attributes.count(ID::gentb_constant) == 0) { signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width; } else { signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width; - if (wire->attributes.count("\\gentb_constant") != 0) - signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string(); + if (wire->attributes.count(ID::gentb_constant) != 0) + signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string(); } f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } } f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str()); - for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); ++it2) { - RTLIL::Wire *wire = it2->second; + for (auto wire : mod->wires()) { if (wire->port_output || wire->port_input) f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(), idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : ""); @@ -312,9 +308,9 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("\t// $dumpfile(\"testbench.vcd\");\n"); f << stringf("\t// $dumpvars(0, testbench);\n"); f << stringf("\tfile = $fopen(`outfile);\n"); - for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) - if (!it->second->get_bool_attribute("\\gentb_skip")) - f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str()); + for (auto module : design->modules()) + if (!module->get_bool_attribute(ID::gentb_skip)) + f << stringf("\t%s;\n", idy(module->name.str(), "test").c_str()); f << stringf("\t$fclose(file);\n"); f << stringf("\t$finish;\n"); f << stringf("end\n\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 88116eeec..cdbe922b2 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -39,98 +39,98 @@ static uint32_t xorshift32(uint32_t limit) { static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv) { - RTLIL::Module *module = design->addModule("\\gold"); - RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); + RTLIL::Module *module = design->addModule(ID(gold)); + RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type); RTLIL::Wire *wire; - if (cell_type.in("$mux", "$pmux")) + if (cell_type.in(ID($mux), ID($pmux))) { int width = 1 + xorshift32(8); - int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8); + int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); wire->width = width * swidth; wire->port_input = true; - cell->setPort("\\B", wire); + cell->setPort(ID::B, wire); - wire = module->addWire("\\S"); + wire = module->addWire(ID::S); wire->width = swidth; wire->port_input = true; - cell->setPort("\\S", wire); + cell->setPort(ID::S, wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); } - if (cell_type == "$fa") + if (cell_type == ID($fa)) { int width = 1 + xorshift32(8); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); wire->width = width; wire->port_input = true; - cell->setPort("\\B", wire); + cell->setPort(ID::B, wire); - wire = module->addWire("\\C"); + wire = module->addWire(ID::C); wire->width = width; wire->port_input = true; - cell->setPort("\\C", wire); + cell->setPort(ID::C, wire); - wire = module->addWire("\\X"); + wire = module->addWire(ID::X); wire->width = width; wire->port_output = true; - cell->setPort("\\X", wire); + cell->setPort(ID::X, wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); } - if (cell_type == "$lcu") + if (cell_type == ID($lcu)) { int width = 1 + xorshift32(8); - wire = module->addWire("\\P"); + wire = module->addWire(ID::P); wire->width = width; wire->port_input = true; - cell->setPort("\\P", wire); + cell->setPort(ID::P, wire); - wire = module->addWire("\\G"); + wire = module->addWire(ID::G); wire->width = width; wire->port_input = true; - cell->setPort("\\G", wire); + cell->setPort(ID::G, wire); - wire = module->addWire("\\CI"); + wire = module->addWire(ID::CI); wire->port_input = true; - cell->setPort("\\CI", wire); + cell->setPort(ID::CI, wire); - wire = module->addWire("\\CO"); + wire = module->addWire(ID::CO); wire->width = width; wire->port_output = true; - cell->setPort("\\CO", wire); + cell->setPort(ID::CO, wire); } - if (cell_type == "$macc") + if (cell_type == ID($macc)) { Macc macc; int width = 1 + xorshift32(8); int depth = 1 + xorshift32(6); int mulbits_a = 0, mulbits_b = 0; - RTLIL::Wire *wire_a = module->addWire("\\A"); + RTLIL::Wire *wire_a = module->addWire(ID::A); wire_a->width = 0; wire_a->port_input = true; @@ -158,52 +158,52 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, macc.ports.push_back(this_port); } - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1); wire->port_input = true; macc.bit_ports = wire; - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = width; wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); macc.to_cell(cell); } - if (cell_type == "$lut") + if (cell_type == ID($lut)) { int width = 1 + xorshift32(6); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); RTLIL::SigSpec config; for (int i = 0; i < (1 << width); i++) config.append(xorshift32(2) ? State::S1 : State::S0); - cell->setParam("\\LUT", config.as_const()); + cell->setParam(ID::LUT, config.as_const()); } - if (cell_type == "$sop") + if (cell_type == ID($sop)) { int width = 1 + xorshift32(8); int depth = 1 + xorshift32(8); - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = width; wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); RTLIL::SigSpec config; for (int i = 0; i < width*depth; i++) @@ -222,74 +222,74 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, break; } - cell->setParam("\\DEPTH", depth); - cell->setParam("\\TABLE", config.as_const()); + cell->setParam(ID::DEPTH, depth); + cell->setParam(ID::TABLE, config.as_const()); } if (cell_type_flags.find('A') != std::string::npos) { - wire = module->addWire("\\A"); + wire = module->addWire(ID::A); wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->setPort("\\A", wire); + cell->setPort(ID::A, wire); } if (cell_type_flags.find('B') != std::string::npos) { - wire = module->addWire("\\B"); + wire = module->addWire(ID::B); if (cell_type_flags.find('h') != std::string::npos) wire->width = 1 + xorshift32(6); else wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->setPort("\\B", wire); + cell->setPort(ID::B, wire); } if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) { if (cell_type_flags.find('A') != std::string::npos) - cell->parameters["\\A_SIGNED"] = true; + cell->parameters[ID::A_SIGNED] = true; if (cell_type_flags.find('B') != std::string::npos) - cell->parameters["\\B_SIGNED"] = true; + cell->parameters[ID::B_SIGNED] = true; } if (cell_type_flags.find('s') != std::string::npos) { if (cell_type_flags.find('A') != std::string::npos && xorshift32(2)) - cell->parameters["\\A_SIGNED"] = true; + cell->parameters[ID::A_SIGNED] = true; if (cell_type_flags.find('B') != std::string::npos && xorshift32(2)) - cell->parameters["\\B_SIGNED"] = true; + cell->parameters[ID::B_SIGNED] = true; } if (cell_type_flags.find('Y') != std::string::npos) { - wire = module->addWire("\\Y"); + wire = module->addWire(ID::Y); wire->width = 1 + xorshift32(8); wire->port_output = true; - cell->setPort("\\Y", wire); + cell->setPort(ID::Y, wire); } - if (muxdiv && cell_type.in("$div", "$mod")) { - auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B")); - auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y"))); - module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y")); - cell->setPort("\\Y", div_out); + if (muxdiv && cell_type.in(ID($div), ID($mod))) { + auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); + auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); + module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); + cell->setPort(ID::Y, div_out); } - if (cell_type == "$alu") + if (cell_type == ID($alu)) { - wire = module->addWire("\\CI"); + wire = module->addWire(ID::CI); wire->port_input = true; - cell->setPort("\\CI", wire); + cell->setPort(ID::CI, wire); - wire = module->addWire("\\BI"); + wire = module->addWire(ID::BI); wire->port_input = true; - cell->setPort("\\BI", wire); + cell->setPort(ID::BI, wire); - wire = module->addWire("\\X"); - wire->width = GetSize(cell->getPort("\\Y")); + wire = module->addWire(ID::X); + wire->width = GetSize(cell->getPort(ID::Y)); wire->port_output = true; - cell->setPort("\\X", wire); + cell->setPort(ID::X, wire); - wire = module->addWire("\\CO"); - wire->width = GetSize(cell->getPort("\\Y")); + wire = module->addWire(ID::CO); + wire->width = GetSize(cell->getPort(ID::Y)); wire->port_output = true; - cell->setPort("\\CO", wire); + cell->setPort(ID::CO, wire); } if (constmode) @@ -421,8 +421,8 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: { log("Eval testing:%c", verbose ? '\n' : ' '); - RTLIL::Module *gold_mod = design->module("\\gold"); - RTLIL::Module *gate_mod = design->module("\\gate"); + RTLIL::Module *gold_mod = design->module(ID(gold)); + RTLIL::Module *gate_mod = design->module(ID(gate)); ConstEval gold_ce(gold_mod), gate_ce(gate_mod); ezSatPtr ez1, ez2; @@ -800,65 +800,65 @@ struct TestCellPass : public Pass { log("Rng seed value: %d\n", int(xorshift32_state)); } - std::map<std::string, std::string> cell_types; - std::vector<std::string> selected_cell_types; - - cell_types["$not"] = "ASY"; - cell_types["$pos"] = "ASY"; - cell_types["$neg"] = "ASY"; - - cell_types["$and"] = "ABSY"; - cell_types["$or"] = "ABSY"; - cell_types["$xor"] = "ABSY"; - cell_types["$xnor"] = "ABSY"; - - cell_types["$reduce_and"] = "ASY"; - cell_types["$reduce_or"] = "ASY"; - cell_types["$reduce_xor"] = "ASY"; - cell_types["$reduce_xnor"] = "ASY"; - cell_types["$reduce_bool"] = "ASY"; - - cell_types["$shl"] = "ABshY"; - cell_types["$shr"] = "ABshY"; - cell_types["$sshl"] = "ABshY"; - cell_types["$sshr"] = "ABshY"; - cell_types["$shift"] = "ABshY"; - cell_types["$shiftx"] = "ABshY"; - - cell_types["$lt"] = "ABSY"; - cell_types["$le"] = "ABSY"; - cell_types["$eq"] = "ABSY"; - cell_types["$ne"] = "ABSY"; - // cell_types["$eqx"] = "ABSY"; - // cell_types["$nex"] = "ABSY"; - cell_types["$ge"] = "ABSY"; - cell_types["$gt"] = "ABSY"; - - cell_types["$add"] = "ABSY"; - cell_types["$sub"] = "ABSY"; - cell_types["$mul"] = "ABSY"; - cell_types["$div"] = "ABSY"; - cell_types["$mod"] = "ABSY"; - // cell_types["$pow"] = "ABsY"; - - cell_types["$logic_not"] = "ASY"; - cell_types["$logic_and"] = "ABSY"; - cell_types["$logic_or"] = "ABSY"; + std::map<IdString, std::string> cell_types; + std::vector<IdString> selected_cell_types; + + cell_types[ID($not)] = "ASY"; + cell_types[ID($pos)] = "ASY"; + cell_types[ID($neg)] = "ASY"; + + cell_types[ID($and)] = "ABSY"; + cell_types[ID($or)] = "ABSY"; + cell_types[ID($xor)] = "ABSY"; + cell_types[ID($xnor)] = "ABSY"; + + cell_types[ID($reduce_and)] = "ASY"; + cell_types[ID($reduce_or)] = "ASY"; + cell_types[ID($reduce_xor)] = "ASY"; + cell_types[ID($reduce_xnor)] = "ASY"; + cell_types[ID($reduce_bool)] = "ASY"; + + cell_types[ID($shl)] = "ABshY"; + cell_types[ID($shr)] = "ABshY"; + cell_types[ID($sshl)] = "ABshY"; + cell_types[ID($sshr)] = "ABshY"; + cell_types[ID($shift)] = "ABshY"; + cell_types[ID($shiftx)] = "ABshY"; + + cell_types[ID($lt)] = "ABSY"; + cell_types[ID($le)] = "ABSY"; + cell_types[ID($eq)] = "ABSY"; + cell_types[ID($ne)] = "ABSY"; + // cell_types[ID($eqx)] = "ABSY"; + // cell_types[ID($nex)] = "ABSY"; + cell_types[ID($ge)] = "ABSY"; + cell_types[ID($gt)] = "ABSY"; + + cell_types[ID($add)] = "ABSY"; + cell_types[ID($sub)] = "ABSY"; + cell_types[ID($mul)] = "ABSY"; + cell_types[ID($div)] = "ABSY"; + cell_types[ID($mod)] = "ABSY"; + // cell_types[ID($pow)] = "ABsY"; + + cell_types[ID($logic_not)] = "ASY"; + cell_types[ID($logic_and)] = "ABSY"; + cell_types[ID($logic_or)] = "ABSY"; if (edges) { - cell_types["$mux"] = "*"; - cell_types["$pmux"] = "*"; + cell_types[ID($mux)] = "*"; + cell_types[ID($pmux)] = "*"; } - // cell_types["$slice"] = "A"; - // cell_types["$concat"] = "A"; + // cell_types[ID($slice)] = "A"; + // cell_types[ID($concat)] = "A"; - cell_types["$lut"] = "*"; - cell_types["$sop"] = "*"; - cell_types["$alu"] = "ABSY"; - cell_types["$lcu"] = "*"; - cell_types["$macc"] = "*"; - cell_types["$fa"] = "*"; + cell_types[ID($lut)] = "*"; + cell_types[ID($sop)] = "*"; + cell_types[ID($alu)] = "ABSY"; + cell_types[ID($lcu)] = "*"; + cell_types[ID($macc)] = "*"; + cell_types[ID($fa)] = "*"; for (; argidx < GetSize(args); argidx++) { @@ -873,7 +873,7 @@ struct TestCellPass : public Pass { } if (args[argidx].compare(0, 1, "/") == 0) { - std::vector<std::string> new_selected_cell_types; + std::vector<IdString> new_selected_cell_types; for (auto it : selected_cell_types) if (it != args[argidx].substr(1)) new_selected_cell_types.push_back(it); @@ -886,10 +886,10 @@ struct TestCellPass : public Pass { int charcount = 100; for (auto &it : cell_types) { if (charcount > 60) { - cell_type_list += "\n" + it.first; + cell_type_list += stringf("\n%s", + log_id(it.first)); charcount = 0; } else - cell_type_list += " " + it.first; + cell_type_list += stringf(" %s", log_id(it.first)); charcount += GetSize(it.first); } log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n", diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc index 070d39a20..e4fa4413f 100644 --- a/techlibs/anlogic/anlogic_eqn.cc +++ b/techlibs/anlogic/anlogic_eqn.cc @@ -74,34 +74,34 @@ struct AnlogicEqnPass : public Pass { { for (auto cell : module->selected_cells()) { - if (cell->type == "\\AL_MAP_LUT1") + if (cell->type == ID(AL_MAP_LUT1)) { - cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),1)); + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),1)); cnt++; } - if (cell->type == "\\AL_MAP_LUT2") + if (cell->type == ID(AL_MAP_LUT2)) { - cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),2)); + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),2)); cnt++; } - if (cell->type == "\\AL_MAP_LUT3") + if (cell->type == ID(AL_MAP_LUT3)) { - cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),3)); + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),3)); cnt++; } - if (cell->type == "\\AL_MAP_LUT4") + if (cell->type == ID(AL_MAP_LUT4)) { - cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),4)); + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),4)); cnt++; } - if (cell->type == "\\AL_MAP_LUT5") + if (cell->type == ID(AL_MAP_LUT5)) { - cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),5)); + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),5)); cnt++; } - if (cell->type == "\\AL_MAP_LUT6") + if (cell->type == ID(AL_MAP_LUT6)) { - cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),6)); + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),6)); cnt++; } } diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index 87164d375..f8e70260c 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -39,13 +39,13 @@ static void fix_carry_chain(Module *module) for (auto cell : module->cells()) { - if (cell->type == "\\AL_MAP_ADDER") { - if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue; - SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a")); - SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b")); + if (cell->type == ID(AL_MAP_ADDER)) { + if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue; + SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a))); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b))); if (bit_i0 == State::S0 && bit_i1== State::S0) { - SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c")); - SigSpec o = cell->getPort("\\o"); + SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c))); + SigSpec o = cell->getPort(ID(o)); if (GetSize(o) == 2) { SigBit bit_o = o[0]; ci_bits.insert(bit_ci); @@ -57,11 +57,11 @@ static void fix_carry_chain(Module *module) vector<Cell*> adders_to_fix_cells; for (auto cell : module->cells()) { - if (cell->type == "\\AL_MAP_ADDER") { - if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue; - SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c")); - SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a")); - SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b")); + if (cell->type == ID(AL_MAP_ADDER)) { + if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue; + SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c))); + SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a))); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b))); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) continue; @@ -75,23 +75,23 @@ static void fix_carry_chain(Module *module) for (auto cell : adders_to_fix_cells) { - SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c")); + SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c))); SigBit canonical_bit = sigmap(bit_ci); auto bit = mapping_bits.at(canonical_bit); log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell)); - Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER"); + Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER)); SigBit new_bit = module->addWire(NEW_ID); SigBit dummy_bit = module->addWire(NEW_ID); SigSpec bits; bits.append(dummy_bit); bits.append(new_bit); - c->setParam("\\ALUTYPE", Const("ADD_CARRY")); - c->setPort("\\a", bit); - c->setPort("\\b", State::S0); - c->setPort("\\c", State::S0); - c->setPort("\\o", bits); + c->setParam(ID(ALUTYPE), Const("ADD_CARRY")); + c->setPort(ID(a), bit); + c->setPort(ID(b), State::S0); + c->setPort(ID(c), State::S0); + c->setPort(ID(o), bits); - cell->setPort("\\c", new_bit); + cell->setPort(ID(c), new_bit); } } diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index d5e69a241..7b1e4b430 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -30,3 +30,4 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v)) $(eval $(call add_share_file,share,techlibs/common/abc9_model.v)) +$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v)) diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v new file mode 100644 index 000000000..b6f4aeed6 --- /dev/null +++ b/techlibs/common/cmp2lcu.v @@ -0,0 +1,116 @@ +// This pass performs an optimisation that decomposes wide arithmetic +// comparisons into LUT-size chunks (as guided by the `LUT_WIDTH +// macro) connected to a single lookahead-carry-unit $lcu cell, +// which is typically mapped to dedicated (and fast) FPGA +// carry-chains. +(* techmap_celltype = "$lt $le $gt $ge" *) +module _80_lcu_cmp_ (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [Y_WIDTH-1:0] Y; + +parameter _TECHMAP_CELLTYPE_ = ""; + +generate + if (_TECHMAP_CELLTYPE_ == "" || `LUT_WIDTH < 2) + wire _TECHMAP_FAIL_ = 1; + else if (_TECHMAP_CELLTYPE_ == "$lt") begin + // Transform $lt into $gt by swapping A and B + $gt #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y)); + end + else if (_TECHMAP_CELLTYPE_ == "$le") begin + // Transform $le into $ge by swapping A and B + $ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y)); + end + else begin + // Perform sign extension on A and B + localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH; + wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A}; + wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B}; + // For $ge operation, start with the assumption that A and B are + // equal (propagating this equality if A and B turn out to be so) + if (_TECHMAP_CELLTYPE_ == "$ge") + localparam CI = 1'b1; + else + localparam CI = 1'b0; + $__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI)) + _TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y)); + end +endgenerate +endmodule + +module $__CMP2LCU (A, B, P, G, Y); + +parameter AB_WIDTH = 0; +parameter AB_SIGNED = 0; +parameter LCU_WIDTH = 1; +parameter BUDGET = 0; +parameter CI = 0; + +input [AB_WIDTH-1:0] A; // A from original $gt/$ge +input [AB_WIDTH-1:0] B; // B from original $gt/$ge +input [LCU_WIDTH-1:0] P; // P of $lcu +input [LCU_WIDTH-1:0] G; // G of $lcu +output Y; + +parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0; +parameter [AB_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; +parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0; + +generate + if (AB_WIDTH == 0) begin + wire [LCU_WIDTH-1:0] CO; + $lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO)); + assign Y = CO[LCU_WIDTH-1]; + end + else begin + if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]) + localparam COST = 0; + else if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]) + localparam COST = 1; + else + localparam COST = 2; + + if (BUDGET < COST) + $__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI)) + _TECHMAP_REPLACE_ (.A(A), .B(B), .P({P, 1'b1}), .G({G, 1'b0}), .Y(Y)); + else begin + wire PP, GG; + // Bit-wise equality (xnor) of A and B + assign PP = A[AB_WIDTH-1] ^~ B[AB_WIDTH-1]; + if (AB_SIGNED) + assign GG = ~A[AB_WIDTH-1] & B[AB_WIDTH-1]; + else if (_TECHMAP_CONSTMSK_P_[LCU_WIDTH-1]) // First compare for LUT if P (and G) is constant + assign GG = A[AB_WIDTH-1] & ~B[AB_WIDTH-1]; + else + // Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0 + // from MSB down, deferring to less significant bits if the + // MSBs are equal + assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]); + if (LCU_WIDTH == 1) begin + // Propagate only if all pairs are equal + // (inconclusive evidence to say A >= B) + wire P_ = P[0] & PP; + // Generate if any comparisons call for it + wire G_ = G[0] | GG; + end + else begin + // Propagate only if all pairs are equal + // (inconclusive evidence to say A >= B) + wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP}; + // Generate if any comparisons call for it + wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG}; + end + $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI)) + _TECHMAP_REPLACE_ (.A(A[AB_WIDTH-2:0]), .B(B[AB_WIDTH-2:0]), .P(P_), .G(G_), .Y(Y)); + end + end +endgenerate +endmodule diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v index 1c8192b85..8ecd356cc 100644 --- a/techlibs/common/cmp2lut.v +++ b/techlibs/common/cmp2lut.v @@ -57,10 +57,6 @@ function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut; o_bit = (lhs > rhs); if (operation == 3) o_bit = (lhs >= rhs); - if (operation == 4) - o_bit = (lhs == rhs); - if (operation == 5) - o_bit = (lhs != rhs); gen_lut = gen_lut | (o_bit << n); end end @@ -75,10 +71,6 @@ generate localparam operation = 2; if (_TECHMAP_CELLTYPE_ == "$ge") localparam operation = 3; - if (_TECHMAP_CELLTYPE_ == "$eq") - localparam operation = 4; - if (_TECHMAP_CELLTYPE_ == "$ne") - localparam operation = 5; if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1) wire _TECHMAP_FAIL_ = 1; diff --git a/techlibs/common/gen_fine_ffs.py b/techlibs/common/gen_fine_ffs.py new file mode 100644 index 000000000..3a9aa6c59 --- /dev/null +++ b/techlibs/common/gen_fine_ffs.py @@ -0,0 +1,239 @@ +TEMPLATES = [ +""" +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_SR_{S:N|P}{R:N|P}_ (S, R, Q) +//- +//- A set-reset latch with {S:negative|positive} polarity SET and {R:negative|positive} polarity RESET. +//- +//- Truth table: S R | Q +//- -----+--- +//- {S:0|1} {R:0|1} | x +//- {S:0|1} {R:1|0} | 1 +//- {S:1|0} {R:0|1} | 0 +//- {S:1|0} {R:1|0} | y +//- +module \$_SR_{S:N|P}{R:N|P}_ (S, R, Q); +input S, R; +output reg Q; +always @({S:neg|pos}edge S, {R:neg|pos}edge R) begin + if (R == {R:0|1}) + Q <= 0; + else if (S == {S:0|1}) + Q <= 1; +end +endmodule +""", +""" +`ifdef SIMCELLS_FF +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_FF_ (D, Q) +//- +//- A D-type flip-flop that is clocked from the implicit global clock. (This cell +//- type is usually only used in netlists for formal verification.) +//- +module \$_FF_ (D, Q); +input D; +output reg Q; +always @($global_clock) begin + Q <= D; +end +endmodule +`endif +""", +""" +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_DFF_{C:N|P}_ (D, C, Q) +//- +//- A {C:negative|positive} edge D-type flip-flop. +//- +//- Truth table: D C | Q +//- -----+--- +//- d {C:\\|/} | d +//- - - | q +//- +module \$_DFF_{C:N|P}_ (D, C, Q); +input D, C; +output reg Q; +always @({C:neg|pos}edge C) begin + Q <= D; +end +endmodule +""", +""" +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q) +//- +//- A {C:negative|positive} edge D-type flip-flop with {E:negative|positive} polarity enable. +//- +//- Truth table: D C E | Q +//- -------+--- +//- d {C:\\|/} {E:0|1} | d +//- - - - | q +//- +module \$_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q); +input D, C, E; +output reg Q; +always @({C:neg|pos}edge C) begin + if ({E:!E|E}) Q <= D; +end +endmodule +""", +""" +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q) +//- +//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set}. +//- +//- Truth table: D C R | Q +//- -------+--- +//- - - {R:0|1} | {V:0|1} +//- d {C:\\|/} - | d +//- - - - | q +//- +module \$_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q); +input D, C, R; +output reg Q; +always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin + if (R == {R:0|1}) + Q <= {V:0|1}; + else + Q <= D; +end +endmodule +""", +""" +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q) +//- +//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive} +//- polarity reset. +//- +//- Truth table: C S R D | Q +//- ---------+--- +//- - - {R:0|1} - | 0 +//- - {S:0|1} - - | 1 +//- {C:\\|/} - - d | d +//- - - - - | q +//- +module \$_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q); +input C, S, R, D; +output reg Q; +always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin + if (R == {R:0|1}) + Q <= 0; + else if (S == {S:0|1}) + Q <= 1; + else + Q <= D; +end +endmodule +""", +""" +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_DLATCH_{E:N|P}_ (E, D, Q) +//- +//- A {E:negative|positive} enable D-type latch. +//- +//- Truth table: E D | Q +//- -----+--- +//- {E:0|1} d | d +//- - - | q +//- +module \$_DLATCH_{E:N|P}_ (E, D, Q); +input E, D; +output reg Q; +always @* begin + if (E == {E:0|1}) + Q <= D; +end +endmodule +""", +""" +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q) +//- +//- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive} +//- polarity reset. +//- +//- Truth table: E S R D | Q +//- ---------+--- +//- - - {R:0|1} - | 0 +//- - {S:0|1} - - | 1 +//- {E:0|1} - - d | d +//- - - - - | q +//- +module \$_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q); +input E, S, R, D; +output reg Q; +always @* begin + if (R == {R:0|1}) + Q <= 0; + else if (S == {S:0|1}) + Q <= 1; + else if (E == {E:0|1}) + Q <= D; +end +endmodule +""", +] + +lines = [] +with open('simcells.v') as f: + for l in f: + lines.append(l) + if 'START AUTOGENERATED CELL TYPES' in l: + break + +with open('simcells.v', 'w') as f: + for l in lines: + f.write(l) + for template in TEMPLATES: + chunks = [] + vars = {} + pos = 0 + while pos < len(template): + if template[pos] != '{': + np = template.find('{', pos) + if np == -1: + np = len(template) + chunks.append(template[pos:np]) + pos = np + else: + np = template.index('}', pos) + sub = template[pos + 1:np] + pos = np + 1 + var, _, vals = sub.partition(':') + if not vals: + raise ValueError(sub) + vals = vals.split('|') + if var not in vars: + vars[var] = len(vals) + else: + if vars[var] != len(vals): + raise ValueError(vars[var], vals) + chunks.append((var, vals)) + combs = [{}] + for var in vars: + combs = [ + { + var: i, + **comb, + } + for comb in combs + for i in range(vars[var]) + ] + for comb in combs: + f.write( + ''.join( + c if isinstance(c, str) else c[1][comb[c[0]]] + for c in chunks + ) + ) diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 64720e598..2bac78d38 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -456,11 +456,16 @@ output Y; assign Y = E ? A : 1'bz; endmodule +// NOTE: the following cell types are autogenerated. DO NOT EDIT them manually, +// instead edit the templates in gen_ff_types.py and rerun it. + +// START AUTOGENERATED CELL TYPES + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_SR_NN_ (S, R, Q) //- -//- A set-reset latch with negative polarity SET and RESET. +//- A set-reset latch with negative polarity SET and negative polarity RESET. //- //- Truth table: S R | Q //- -----+--- @@ -532,7 +537,7 @@ endmodule //- //- $_SR_PP_ (S, R, Q) //- -//- A set-reset latch with positive polarity SET and RESET. +//- A set-reset latch with positive polarity SET and positive polarity RESET. //- //- Truth table: S R | Q //- -----+--- @@ -871,7 +876,8 @@ endmodule //- //- $_DFFSR_NNN_ (C, S, R, D, Q) //- -//- A negative edge D-type flip-flop with negative polarity set and reset. +//- A negative edge D-type flip-flop with negative polarity set and negative +//- polarity reset. //- //- Truth table: C S R D | Q //- ---------+--- @@ -951,7 +957,8 @@ endmodule //- //- $_DFFSR_NPP_ (C, S, R, D, Q) //- -//- A negative edge D-type flip-flop with positive polarity set and reset. +//- A negative edge D-type flip-flop with positive polarity set and positive +//- polarity reset. //- //- Truth table: C S R D | Q //- ---------+--- @@ -977,7 +984,8 @@ endmodule //- //- $_DFFSR_PNN_ (C, S, R, D, Q) //- -//- A positive edge D-type flip-flop with negative polarity set and reset. +//- A positive edge D-type flip-flop with negative polarity set and negative +//- polarity reset. //- //- Truth table: C S R D | Q //- ---------+--- @@ -1057,7 +1065,8 @@ endmodule //- //- $_DFFSR_PPP_ (C, S, R, D, Q) //- -//- A positive edge D-type flip-flop with positive polarity set and reset. +//- A positive edge D-type flip-flop with positive polarity set and positive +//- polarity reset. //- //- Truth table: C S R D | Q //- ---------+--- @@ -1123,7 +1132,8 @@ endmodule //- //- $_DLATCHSR_NNN_ (E, S, R, D, Q) //- -//- A negative enable D-type latch with negative polarity set and reset. +//- A negative enable D-type latch with negative polarity set and negative +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1149,8 +1159,8 @@ endmodule //- //- $_DLATCHSR_NNP_ (E, S, R, D, Q) //- -//- A negative enable D-type latch with negative polarity set and positive polarity -//- reset. +//- A negative enable D-type latch with negative polarity set and positive +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1176,8 +1186,8 @@ endmodule //- //- $_DLATCHSR_NPN_ (E, S, R, D, Q) //- -//- A negative enable D-type latch with positive polarity set and negative polarity -//- reset. +//- A negative enable D-type latch with positive polarity set and negative +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1203,7 +1213,8 @@ endmodule //- //- $_DLATCHSR_NPP_ (E, S, R, D, Q) //- -//- A negative enable D-type latch with positive polarity set and reset. +//- A negative enable D-type latch with positive polarity set and positive +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1229,7 +1240,8 @@ endmodule //- //- $_DLATCHSR_PNN_ (E, S, R, D, Q) //- -//- A positive enable D-type latch with negative polarity set and reset. +//- A positive enable D-type latch with negative polarity set and negative +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1255,8 +1267,8 @@ endmodule //- //- $_DLATCHSR_PNP_ (E, S, R, D, Q) //- -//- A positive enable D-type latch with negative polarity set and positive polarity -//- reset. +//- A positive enable D-type latch with negative polarity set and positive +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1282,8 +1294,8 @@ endmodule //- //- $_DLATCHSR_PPN_ (E, S, R, D, Q) //- -//- A positive enable D-type latch with positive polarity set and negative polarity -//- reset. +//- A positive enable D-type latch with positive polarity set and negative +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1309,7 +1321,8 @@ endmodule //- //- $_DLATCHSR_PPP_ (E, S, R, D, Q) //- -//- A positive enable D-type latch with positive polarity set and reset. +//- A positive enable D-type latch with positive polarity set and positive +//- polarity reset. //- //- Truth table: E S R D | Q //- ---------+--- @@ -1330,4 +1343,3 @@ always @* begin Q <= D; end endmodule - diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index e7a192c07..d6dffdd7f 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -225,9 +225,9 @@ struct SynthPass : public ScriptPass run("peepopt"); run("opt_clean"); if (help_mode) - run("techmap -map +/cmp2lut.v", " (if -lut)"); - else - run(stringf("techmap -map +/cmp2lut.v -D LUT_WIDTH=%d", lut)); + run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); + else if (lut) + run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); if (!noalumacc) run("alumacc", " (unless -noalumacc)"); if (!noshare) diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc index a71a1227e..8bbff9ba5 100644 --- a/techlibs/coolrunner2/coolrunner2_fixup.cc +++ b/techlibs/coolrunner2/coolrunner2_fixup.cc @@ -34,9 +34,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname))); auto xor_cell = module->addCell( module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)), - "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", true); - xor_cell->setPort("\\OUT", outwire); + ID(MACROCELL_XOR)); + xor_cell->setParam(ID(INVERT_OUT), true); + xor_cell->setPort(ID(OUT), outwire); } else if (inwire == SigBit(false)) { @@ -45,9 +45,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname))); auto xor_cell = module->addCell( module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)), - "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", false); - xor_cell->setPort("\\OUT", outwire); + ID(MACROCELL_XOR)); + xor_cell->setParam(ID(INVERT_OUT), false); + xor_cell->setPort(ID(OUT), outwire); } else if (inwire == SigBit(RTLIL::State::Sx)) { @@ -57,9 +57,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname))); auto xor_cell = module->addCell( module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)), - "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", false); - xor_cell->setPort("\\OUT", outwire); + ID(MACROCELL_XOR)); + xor_cell->setParam(ID(INVERT_OUT), false); + xor_cell->setPort(ID(OUT), outwire); } else { @@ -73,19 +73,19 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel auto and_cell = module->addCell( module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)), - "\\ANDTERM"); - and_cell->setParam("\\TRUE_INP", 1); - and_cell->setParam("\\COMP_INP", 0); - and_cell->setPort("\\OUT", and_to_xor_wire); - and_cell->setPort("\\IN", inwire); - and_cell->setPort("\\IN_B", SigSpec()); + ID(ANDTERM)); + and_cell->setParam(ID(TRUE_INP), 1); + and_cell->setParam(ID(COMP_INP), 0); + and_cell->setPort(ID(OUT), and_to_xor_wire); + and_cell->setPort(ID(IN), inwire); + and_cell->setPort(ID(IN_B), SigSpec()); auto xor_cell = module->addCell( module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)), - "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", false); - xor_cell->setPort("\\IN_PTC", and_to_xor_wire); - xor_cell->setPort("\\OUT", outwire); + ID(MACROCELL_XOR)); + xor_cell->setParam(ID(INVERT_OUT), false); + xor_cell->setPort(ID(IN_PTC), and_to_xor_wire); + xor_cell->setPort(ID(OUT), outwire); } return outwire; @@ -100,12 +100,12 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire) auto and_cell = module->addCell( module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)), - "\\ANDTERM"); - and_cell->setParam("\\TRUE_INP", 1); - and_cell->setParam("\\COMP_INP", 0); - and_cell->setPort("\\OUT", outwire); - and_cell->setPort("\\IN", inwire); - and_cell->setPort("\\IN_B", SigSpec()); + ID(ANDTERM)); + and_cell->setParam(ID(TRUE_INP), 1); + and_cell->setParam(ID(COMP_INP), 0); + and_cell->setPort(ID(OUT), outwire); + and_cell->setPort(ID(IN), inwire); + and_cell->setPort(ID(IN_B), SigSpec()); return outwire; } @@ -133,10 +133,10 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_ff; for (auto cell : module->selected_cells()) { - if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", - "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) + if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N), + ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE))) { - auto output = sigmap(cell->getPort("\\Q")[0]); + auto output = sigmap(cell->getPort(ID::Q)[0]); sig_fed_by_ff.insert(output); } } @@ -145,9 +145,9 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_xor; for (auto cell : module->selected_cells()) { - if (cell->type == "\\MACROCELL_XOR") + if (cell->type == ID(MACROCELL_XOR)) { - auto output = sigmap(cell->getPort("\\OUT")[0]); + auto output = sigmap(cell->getPort(ID(OUT))[0]); sig_fed_by_xor.insert(output); } } @@ -156,10 +156,10 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_io; for (auto cell : module->selected_cells()) { - if (cell->type.in("\\IBUF", "\\IOBUFE")) + if (cell->type.in(ID(IBUF), ID(IOBUFE))) { - if (cell->hasPort("\\O")) { - auto output = sigmap(cell->getPort("\\O")[0]); + if (cell->hasPort(ID::O)) { + auto output = sigmap(cell->getPort(ID::O)[0]); sig_fed_by_io.insert(output); } } @@ -169,9 +169,9 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_pterm; for (auto cell : module->selected_cells()) { - if (cell->type == "\\ANDTERM") + if (cell->type == ID(ANDTERM)) { - auto output = sigmap(cell->getPort("\\OUT")[0]); + auto output = sigmap(cell->getPort(ID(OUT))[0]); sig_fed_by_pterm.insert(output); } } @@ -180,9 +180,9 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_bufg; for (auto cell : module->selected_cells()) { - if (cell->type == "\\BUFG") + if (cell->type == ID(BUFG)) { - auto output = sigmap(cell->getPort("\\O")[0]); + auto output = sigmap(cell->getPort(ID::O)[0]); sig_fed_by_bufg.insert(output); } } @@ -191,9 +191,9 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_bufgsr; for (auto cell : module->selected_cells()) { - if (cell->type == "\\BUFGSR") + if (cell->type == ID(BUFGSR)) { - auto output = sigmap(cell->getPort("\\O")[0]); + auto output = sigmap(cell->getPort(ID::O)[0]); sig_fed_by_bufgsr.insert(output); } } @@ -202,9 +202,9 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_bufgts; for (auto cell : module->selected_cells()) { - if (cell->type == "\\BUFGTS") + if (cell->type == ID(BUFGTS)) { - auto output = sigmap(cell->getPort("\\O")[0]); + auto output = sigmap(cell->getPort(ID::O)[0]); sig_fed_by_bufgts.insert(output); } } @@ -213,9 +213,9 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> sig_fed_by_ibuf; for (auto cell : module->selected_cells()) { - if (cell->type == "\\IBUF") + if (cell->type == ID(IBUF)) { - auto output = sigmap(cell->getPort("\\O")[0]); + auto output = sigmap(cell->getPort(ID::O)[0]); sig_fed_by_ibuf.insert(output); } } @@ -254,15 +254,15 @@ struct Coolrunner2FixupPass : public Pass { // the pad-to-zia path has to be used up and the register // can't be packed with the ibuf. if (fanout_count == 1 && maybe_ff_cell->type.in( - "\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", - "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) + ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N), + ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE))) { SigBit input; - if (maybe_ff_cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) - input = sigmap(maybe_ff_cell->getPort("\\T")[0]); + if (maybe_ff_cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP))) + input = sigmap(maybe_ff_cell->getPort(ID::T)[0]); else - input = sigmap(maybe_ff_cell->getPort("\\D")[0]); - SigBit output = sigmap(maybe_ff_cell->getPort("\\Q")[0]); + input = sigmap(maybe_ff_cell->getPort(ID::D)[0]); + SigBit output = sigmap(maybe_ff_cell->getPort(ID::Q)[0]); if (input == ibuf_out_wire) { @@ -279,17 +279,17 @@ struct Coolrunner2FixupPass : public Pass { for (auto cell : module->selected_cells()) { - if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", - "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) + if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N), + ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE))) { // Buffering FF inputs. FF inputs can only come from either // an IO pin or from an XOR. Otherwise AND/XOR cells need // to be inserted. SigBit input; - if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) - input = sigmap(cell->getPort("\\T")[0]); + if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP))) + input = sigmap(cell->getPort(ID::T)[0]); else - input = sigmap(cell->getPort("\\D")[0]); + input = sigmap(cell->getPort(ID::D)[0]); // If the input wasn't an XOR nor an IO, then a buffer // definitely needs to be added. @@ -302,10 +302,10 @@ struct Coolrunner2FixupPass : public Pass { auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str()); - if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) - cell->setPort("\\T", xor_to_ff_wire); + if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP))) + cell->setPort(ID::T, xor_to_ff_wire); else - cell->setPort("\\D", xor_to_ff_wire); + cell->setPort(ID::D, xor_to_ff_wire); } // Buffering FF clocks. FF clocks can only come from either @@ -313,10 +313,10 @@ struct Coolrunner2FixupPass : public Pass { // in coolrunner2_sop (e.g. if clock is generated from // AND-ing two signals) but not in all cases. SigBit clock; - if (cell->type.in("\\LDCP", "\\LDCP_N")) - clock = sigmap(cell->getPort("\\G")[0]); + if (cell->type.in(ID(LDCP), ID(LDCP_N))) + clock = sigmap(cell->getPort(ID::G)[0]); else - clock = sigmap(cell->getPort("\\C")[0]); + clock = sigmap(cell->getPort(ID::C)[0]); if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock]) { @@ -324,16 +324,16 @@ struct Coolrunner2FixupPass : public Pass { auto pterm_to_ff_wire = makeptermbuffer(module, clock); - if (cell->type.in("\\LDCP", "\\LDCP_N")) - cell->setPort("\\G", pterm_to_ff_wire); + if (cell->type.in(ID(LDCP), ID(LDCP_N))) + cell->setPort(ID::G, pterm_to_ff_wire); else - cell->setPort("\\C", pterm_to_ff_wire); + cell->setPort(ID::C, pterm_to_ff_wire); } // Buffering FF set/reset. This can only come from either // a pterm or a bufgsr. SigBit set; - set = sigmap(cell->getPort("\\PRE")[0]); + set = sigmap(cell->getPort(ID(PRE))[0]); if (set != SigBit(false)) { if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set]) @@ -342,12 +342,12 @@ struct Coolrunner2FixupPass : public Pass { auto pterm_to_ff_wire = makeptermbuffer(module, set); - cell->setPort("\\PRE", pterm_to_ff_wire); + cell->setPort(ID(PRE), pterm_to_ff_wire); } } SigBit reset; - reset = sigmap(cell->getPort("\\CLR")[0]); + reset = sigmap(cell->getPort(ID::CLR)[0]); if (reset != SigBit(false)) { if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset]) @@ -356,24 +356,24 @@ struct Coolrunner2FixupPass : public Pass { auto pterm_to_ff_wire = makeptermbuffer(module, reset); - cell->setPort("\\CLR", pterm_to_ff_wire); + cell->setPort(ID::CLR, pterm_to_ff_wire); } } // Buffering FF clock enable // FIXME: This doesn't fully fix PTC conflicts // FIXME: Need to ensure constant enables are optimized out - if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) + if (cell->type.in(ID(FDCPE), ID(FDCPE_N), ID(FDDCPE))) { SigBit ce; - ce = sigmap(cell->getPort("\\CE")[0]); + ce = sigmap(cell->getPort(ID(CE))[0]); if (!sig_fed_by_pterm[ce]) { log("Buffering clock enable to \"%s\"\n", cell->name.c_str()); auto pterm_to_ff_wire = makeptermbuffer(module, ce); - cell->setPort("\\CE", pterm_to_ff_wire); + cell->setPort(ID(CE), pterm_to_ff_wire); } } } @@ -381,10 +381,10 @@ struct Coolrunner2FixupPass : public Pass { for (auto cell : module->selected_cells()) { - if (cell->type == "\\IOBUFE") + if (cell->type == ID(IOBUFE)) { // Buffer IOBUFE inputs. This can only be fed from an XOR or FF. - SigBit input = sigmap(cell->getPort("\\I")[0]); + SigBit input = sigmap(cell->getPort(ID::I)[0]); if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) || packed_reg_out[input]) @@ -393,22 +393,22 @@ struct Coolrunner2FixupPass : public Pass { auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str()); - cell->setPort("\\I", xor_to_io_wire); + cell->setPort(ID::I, xor_to_io_wire); } // Buffer IOBUFE enables. This can only be fed from a pterm // or a bufgts. - if (cell->hasPort("\\E")) + if (cell->hasPort(ID::E)) { SigBit oe; - oe = sigmap(cell->getPort("\\E")[0]); + oe = sigmap(cell->getPort(ID::E)[0]); if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe]) { log("Buffering output enable to \"%s\"\n", cell->name.c_str()); auto pterm_to_oe_wire = makeptermbuffer(module, oe); - cell->setPort("\\E", pterm_to_oe_wire); + cell->setPort(ID::E, pterm_to_oe_wire); } } } @@ -422,9 +422,9 @@ struct Coolrunner2FixupPass : public Pass { dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell; for (auto cell : module->selected_cells()) { - if (cell->type == "\\MACROCELL_XOR") + if (cell->type == ID(MACROCELL_XOR)) { - auto output = sigmap(cell->getPort("\\OUT")[0]); + auto output = sigmap(cell->getPort(ID(OUT))[0]); xor_out_to_xor_cell[output] = cell; } } @@ -433,7 +433,7 @@ struct Coolrunner2FixupPass : public Pass { pool<SigBit> xor_fanout_once; for (auto cell : module->selected_cells()) { - if (cell->type == "\\ANDTERM") + if (cell->type == ID(ANDTERM)) continue; for (auto &conn : cell->connections()) @@ -456,7 +456,7 @@ struct Coolrunner2FixupPass : public Pass { module->uniquify(xor_cell->name), xor_cell); auto new_wire = module->addWire( module->uniquify(wire_in.wire->name)); - new_xor_cell->setPort("\\OUT", new_wire); + new_xor_cell->setPort(ID(OUT), new_wire); cell->setPort(conn.first, new_wire); } xor_fanout_once.insert(wire_in); @@ -473,9 +473,9 @@ struct Coolrunner2FixupPass : public Pass { dict<SigBit, RTLIL::Cell *> or_out_to_or_cell; for (auto cell : module->selected_cells()) { - if (cell->type == "\\ORTERM") + if (cell->type == ID(ORTERM)) { - auto output = sigmap(cell->getPort("\\OUT")[0]); + auto output = sigmap(cell->getPort(ID(OUT))[0]); or_out_to_or_cell[output] = cell; } } @@ -504,7 +504,7 @@ struct Coolrunner2FixupPass : public Pass { module->uniquify(or_cell->name), or_cell); auto new_wire = module->addWire( module->uniquify(wire_in.wire->name)); - new_or_cell->setPort("\\OUT", new_wire); + new_or_cell->setPort(ID(OUT), new_wire); cell->setPort(conn.first, new_wire); } or_fanout_once.insert(wire_in); diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index 581477473..045c73978 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -47,52 +47,52 @@ struct Coolrunner2SopPass : public Pass { dict<SigBit, tuple<SigBit, Cell*>> not_cells; for (auto cell : module->selected_cells()) { - if (cell->type == "$_NOT_") + if (cell->type == ID($_NOT_)) { - auto not_input = sigmap(cell->getPort("\\A")[0]); - auto not_output = sigmap(cell->getPort("\\Y")[0]); + auto not_input = sigmap(cell->getPort(ID::A)[0]); + auto not_output = sigmap(cell->getPort(ID::Y)[0]); not_cells[not_input] = tuple<SigBit, Cell*>(not_output, cell); } } // Find wires that need to become special product terms - dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_no_inv; - dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv; + dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_no_inv; + dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_inv; for (auto cell : module->selected_cells()) { - if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP", - "\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N")) + if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP), + ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N))) { - if (cell->hasPort("\\PRE")) - special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert( - tuple<Cell*, const char *>(cell, "\\PRE")); - if (cell->hasPort("\\CLR")) - special_pterms_no_inv[sigmap(cell->getPort("\\CLR")[0])].insert( - tuple<Cell*, const char *>(cell, "\\CLR")); - if (cell->hasPort("\\CE")) - special_pterms_no_inv[sigmap(cell->getPort("\\CE")[0])].insert( - tuple<Cell*, const char *>(cell, "\\CE")); - - if (cell->hasPort("\\C")) - special_pterms_inv[sigmap(cell->getPort("\\C")[0])].insert( - tuple<Cell*, const char *>(cell, "\\C")); - if (cell->hasPort("\\G")) - special_pterms_inv[sigmap(cell->getPort("\\G")[0])].insert( - tuple<Cell*, const char *>(cell, "\\G")); + if (cell->hasPort(ID(PRE))) + special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert( + make_tuple(cell, ID(PRE))); + if (cell->hasPort(ID::CLR)) + special_pterms_no_inv[sigmap(cell->getPort(ID::CLR)[0])].insert( + make_tuple(cell, ID::CLR)); + if (cell->hasPort(ID(CE))) + special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert( + make_tuple(cell, ID(CE))); + + if (cell->hasPort(ID::C)) + special_pterms_inv[sigmap(cell->getPort(ID::C)[0])].insert( + make_tuple(cell, ID::C)); + if (cell->hasPort(ID::G)) + special_pterms_inv[sigmap(cell->getPort(ID::G)[0])].insert( + make_tuple(cell, ID::G)); } } // Process $sop cells for (auto cell : module->selected_cells()) { - if (cell->type == "$sop") + if (cell->type == ID($sop)) { // Read the inputs/outputs/parameters of the $sop cell - auto sop_inputs = sigmap(cell->getPort("\\A")); - auto sop_output = sigmap(cell->getPort("\\Y"))[0]; - auto sop_depth = cell->getParam("\\DEPTH").as_int(); - auto sop_width = cell->getParam("\\WIDTH").as_int(); - auto sop_table = cell->getParam("\\TABLE"); + auto sop_inputs = sigmap(cell->getPort(ID::A)); + auto sop_output = sigmap(cell->getPort(ID::Y))[0]; + auto sop_depth = cell->getParam(ID::DEPTH).as_int(); + auto sop_width = cell->getParam(ID::WIDTH).as_int(); + auto sop_table = cell->getParam(ID::TABLE); auto sop_output_wire_name = sop_output.wire->name.c_str(); @@ -139,12 +139,12 @@ struct Coolrunner2SopPass : public Pass { // Construct the cell auto and_cell = module->addCell( module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)), - "\\ANDTERM"); - and_cell->setParam("\\TRUE_INP", GetSize(and_in_true)); - and_cell->setParam("\\COMP_INP", GetSize(and_in_comp)); - and_cell->setPort("\\OUT", and_out); - and_cell->setPort("\\IN", and_in_true); - and_cell->setPort("\\IN_B", and_in_comp); + ID(ANDTERM)); + and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true)); + and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp)); + and_cell->setPort(ID(OUT), and_out); + and_cell->setPort(ID(IN), and_in_true); + and_cell->setPort(ID(IN_B), and_in_comp); } if (sop_depth == 1) @@ -152,17 +152,17 @@ struct Coolrunner2SopPass : public Pass { // If there is only one term, don't construct an OR cell. Directly construct the XOR gate auto xor_cell = module->addCell( module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)), - "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", has_invert); - xor_cell->setPort("\\IN_PTC", *intermed_wires.begin()); - xor_cell->setPort("\\OUT", sop_output); + ID(MACROCELL_XOR)); + xor_cell->setParam(ID(INVERT_OUT), has_invert); + xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin()); + xor_cell->setPort(ID(OUT), sop_output); // Special P-term handling if (is_special_pterm) { // Can always connect the P-term directly if it's going // into something invert-capable - for (auto x : special_pterms_inv[sop_output]) + for (const auto &x : special_pterms_inv[sop_output]) { std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin()); @@ -170,14 +170,14 @@ struct Coolrunner2SopPass : public Pass { if (has_invert) { auto cell = std::get<0>(x); - if (cell->type == "\\FDCP") cell->type = "\\FDCP_N"; - else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP"; - else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N"; - else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP"; - else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N"; - else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE"; - else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N"; - else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP"; + if (cell->type == ID(FDCP)) cell->type = ID(FDCP_N); + else if (cell->type == ID(FDCP_N)) cell->type = ID(FDCP); + else if (cell->type == ID(FTCP)) cell->type = ID(FTCP_N); + else if (cell->type == ID(FTCP_N)) cell->type = ID(FTCP); + else if (cell->type == ID(FDCPE)) cell->type = ID(FDCPE_N); + else if (cell->type == ID(FDCPE_N)) cell->type = ID(FDCPE); + else if (cell->type == ID(LDCP)) cell->type = ID(LDCP_N); + else if (cell->type == ID(LDCP_N)) cell->type = ID(LDCP); else log_assert(!"Internal error! Bad cell type!"); } } @@ -203,18 +203,18 @@ struct Coolrunner2SopPass : public Pass { // Construct the OR cell auto or_cell = module->addCell( module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)), - "\\ORTERM"); - or_cell->setParam("\\WIDTH", sop_depth); - or_cell->setPort("\\IN", intermed_wires); - or_cell->setPort("\\OUT", or_to_xor_wire); + ID(ORTERM)); + or_cell->setParam(ID::WIDTH, sop_depth); + or_cell->setPort(ID(IN), intermed_wires); + or_cell->setPort(ID(OUT), or_to_xor_wire); // Construct the XOR cell auto xor_cell = module->addCell( module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)), - "\\MACROCELL_XOR"); - xor_cell->setParam("\\INVERT_OUT", has_invert); - xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire); - xor_cell->setPort("\\OUT", sop_output); + ID(MACROCELL_XOR)); + xor_cell->setParam(ID(INVERT_OUT), has_invert); + xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire); + xor_cell->setPort(ID(OUT), sop_output); } // Finally, remove the $sop cell diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc index dbd16cac9..e85bee64e 100644 --- a/techlibs/ecp5/ecp5_ffinit.cc +++ b/techlibs/ecp5/ecp5_ffinit.cc @@ -63,11 +63,11 @@ struct Ecp5FfinitPass : public Pass { for (auto wire : module->selected_wires()) { - if (wire->attributes.count("\\init") == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec wirebits = sigmap(wire); - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); init_wires.insert(wire); for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) @@ -94,11 +94,11 @@ struct Ecp5FfinitPass : public Pass { } for (auto cell : module->selected_cells()) { - if (cell->type != "\\TRELLIS_FF") + if (cell->type != ID(TRELLIS_FF)) continue; - SigSpec sig_d = cell->getPort("\\DI"); - SigSpec sig_q = cell->getPort("\\Q"); - SigSpec sig_lsr = cell->getPort("\\LSR"); + SigSpec sig_d = cell->getPort(ID(DI)); + SigSpec sig_q = cell->getPort(ID::Q); + SigSpec sig_lsr = cell->getPort(ID(LSR)); if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1) continue; @@ -107,8 +107,8 @@ struct Ecp5FfinitPass : public Pass { SigBit bit_q = sigmap(sig_q[0]); std::string regset = "RESET"; - if (cell->hasParam("\\REGSET")) - regset = cell->getParam("\\REGSET").decode_string(); + if (cell->hasParam(ID(REGSET))) + regset = cell->getParam(ID(REGSET)).decode_string(); State resetState; if (regset == "SET") resetState = State::S1; @@ -136,8 +136,8 @@ struct Ecp5FfinitPass : public Pass { if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) { std::string srmode = "LSR_OVER_CE"; - if (cell->hasParam("\\SRMODE")) - srmode = cell->getParam("\\SRMODE").decode_string(); + if (cell->hasParam(ID(SRMODE))) + srmode = cell->getParam(ID(SRMODE)).decode_string(); if (srmode == "ASYNC") { log("Async reset value %c for FF cell %s inconsistent with init value %c.\n", resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0'); @@ -150,14 +150,14 @@ struct Ecp5FfinitPass : public Pass { module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d); } - cell->setPort("\\DI", new_bit_d); - cell->setPort("\\LSR", State::S0); + cell->setPort(ID(DI), new_bit_d); + cell->setPort(ID(LSR), State::S0); - if(cell->hasPort("\\CE")) { + if(cell->hasPort(ID(CE))) { std::string cemux = "CE"; - if (cell->hasParam("\\CEMUX")) - cemux = cell->getParam("\\CEMUX").decode_string(); - SigSpec sig_ce = cell->getPort("\\CE"); + if (cell->hasParam(ID(CEMUX))) + cemux = cell->getParam(ID(CEMUX)).decode_string(); + SigSpec sig_ce = cell->getPort(ID(CE)); if (GetSize(sig_ce) >= 1) { SigBit bit_ce = sigmap(sig_ce[0]); Wire *new_bit_ce = module->addWire(NEW_ID); @@ -165,25 +165,25 @@ struct Ecp5FfinitPass : public Pass { module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce); else module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce); - cell->setPort("\\CE", new_bit_ce); + cell->setPort(ID(CE), new_bit_ce); } } - cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET")); + cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET")); handled_initbits.insert(bit_q); } } else { - cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET")); + cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET")); handled_initbits.insert(bit_q); } } for (auto wire : init_wires) { - if (wire->attributes.count("\\init") == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec wirebits = sigmap(wire); - Const &initval = wire->attributes.at("\\init"); + Const &initval = wire->attributes.at(ID::init); bool remove_attribute = true; for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) { @@ -194,7 +194,7 @@ struct Ecp5FfinitPass : public Pass { } if (remove_attribute) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); } } } diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index 2bc714b6f..d1503f71f 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -85,7 +85,7 @@ struct Ecp5GsrPass : public Pass { continue; bool gsren = found_gsr; - if (cell->get_bool_attribute("\\nogsr")) + if (cell->get_bool_attribute(ID(nogsr))) gsren = false; cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED")); @@ -102,7 +102,7 @@ struct Ecp5GsrPass : public Pass { { if (cell->type != ID($_NOT_)) continue; - SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y)); + SigSpec sig_a = cell->getPort(ID::A), sig_y = cell->getPort(ID::Y); if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1) continue; SigBit a = sigmap(sig_a[0]); diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index b7cd995b8..1a1733a17 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -39,12 +39,12 @@ static void fix_carry_chain(Module *module) for (auto cell : module->cells()) { - if (cell->type == "\\EFX_ADD") { - SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0")); - SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1")); + if (cell->type == ID(EFX_ADD)) { + SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0))); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); if (bit_i0 == State::S0 && bit_i1== State::S0) { - SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI")); - SigBit bit_o = sigmap(cell->getPort("\\O")); + SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); + SigBit bit_o = sigmap(cell->getPort(ID::O)); ci_bits.insert(bit_ci); mapping_bits[bit_ci] = bit_o; } @@ -54,10 +54,10 @@ static void fix_carry_chain(Module *module) vector<Cell*> adders_to_fix_cells; for (auto cell : module->cells()) { - if (cell->type == "\\EFX_ADD") { - SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI")); - SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0")); - SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1")); + if (cell->type == ID(EFX_ADD)) { + SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); + SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0))); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) continue; @@ -71,20 +71,20 @@ static void fix_carry_chain(Module *module) for (auto cell : adders_to_fix_cells) { - SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI")); + SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); SigBit canonical_bit = sigmap(bit_ci); auto bit = mapping_bits.at(canonical_bit); log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell)); - Cell *c = module->addCell(NEW_ID, "\\EFX_ADD"); + Cell *c = module->addCell(NEW_ID, ID(EFX_ADD)); SigBit new_bit = module->addWire(NEW_ID); - c->setParam("\\I0_POLARITY", State::S1); - c->setParam("\\I1_POLARITY", State::S1); - c->setPort("\\I0", bit); - c->setPort("\\I1", State::S1); - c->setPort("\\CI", State::S0); - c->setPort("\\CO", new_bit); + c->setParam(ID(I0_POLARITY), State::S1); + c->setParam(ID(I1_POLARITY), State::S1); + c->setPort(ID(I0), bit); + c->setPort(ID(I1), State::S1); + c->setPort(ID::CI, State::S0); + c->setPort(ID::CO, new_bit); - cell->setPort("\\CI", new_bit); + cell->setPort(ID::CI, new_bit); } } @@ -101,7 +101,7 @@ struct EfinixCarryFixPass : public Pass { } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { - log_header(design, "Executing efinix_fixcarry pass (fix invalid carry chain).\n"); + log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc index e75fb3f4d..55dfb3c79 100644 --- a/techlibs/efinix/efinix_gbuf.cc +++ b/techlibs/efinix/efinix_gbuf.cc @@ -34,14 +34,14 @@ static void handle_gbufs(Module *module) for (auto cell : module->cells()) { - if (cell->type == "\\EFX_FF") { - for (auto bit : sigmap(cell->getPort("\\CLK"))) + if (cell->type == ID(EFX_FF)) { + for (auto bit : sigmap(cell->getPort(ID::CLK))) clk_bits.insert(bit); } - if (cell->type == "\\EFX_RAM_5K") { - for (auto bit : sigmap(cell->getPort("\\RCLK"))) + if (cell->type == ID(EFX_RAM_5K)) { + for (auto bit : sigmap(cell->getPort(ID(RCLK)))) clk_bits.insert(bit); - for (auto bit : sigmap(cell->getPort("\\WCLK"))) + for (auto bit : sigmap(cell->getPort(ID(WCLK)))) clk_bits.insert(bit); } } @@ -59,11 +59,11 @@ static void handle_gbufs(Module *module) if (!clk_bits.count(canonical_bit)) continue; - Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE"); + Cell *c = module->addCell(NEW_ID, ID(EFX_GBUFCE)); SigBit new_bit = module->addWire(NEW_ID); - c->setParam("\\CE_POLARITY", State::S1); - c->setPort("\\O", new_bit); - c->setPort("\\CE", State::S1); + c->setParam(ID(CE_POLARITY), State::S1); + c->setPort(ID::O, new_bit); + c->setPort(ID(CE), State::S1); pad_bits.push_back(make_pair(c, bit)); rewrite_bits[canonical_bit] = new_bit; @@ -82,7 +82,7 @@ static void handle_gbufs(Module *module) module->rewrite_sigspecs(rewrite_function); for (auto &it : pad_bits) - it.first->setPort("\\I", it.second); + it.first->setPort(ID::I, it.second); } struct EfinixGbufPass : public Pass { diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc index d9a0880f6..18a64e451 100644 --- a/techlibs/gowin/determine_init.cc +++ b/techlibs/gowin/determine_init.cc @@ -55,12 +55,12 @@ struct DetermineInitPass : public Pass { { for (auto cell : module->selected_cells()) { - if (cell->type == "\\RAM16S4") + if (cell->type == ID(RAM16S4)) { - cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0"))); - cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1"))); - cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2"))); - cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3"))); + cell->setParam(ID(INIT_0), determine_init(cell->getParam(ID(INIT_0)))); + cell->setParam(ID(INIT_1), determine_init(cell->getParam(ID(INIT_1)))); + cell->setParam(ID(INIT_2), determine_init(cell->getParam(ID(INIT_2)))); + cell->setParam(ID(INIT_3), determine_init(cell->getParam(ID(INIT_3)))); cnt++; } } diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc index d57e978a0..62057318b 100644 --- a/techlibs/greenpak4/greenpak4_dffinv.cc +++ b/techlibs/greenpak4/greenpak4_dffinv.cc @@ -33,37 +33,37 @@ void invert_gp_dff(Cell *cell, bool invert_input) if (!invert_input) { - Const initval = cell->getParam("\\INIT"); + Const initval = cell->getParam(ID::INIT); if (GetSize(initval) >= 1) { if (initval.bits[0] == State::S0) initval.bits[0] = State::S1; else if (initval.bits[0] == State::S1) initval.bits[0] = State::S0; - cell->setParam("\\INIT", initval); + cell->setParam(ID::INIT, initval); } if (cell_type_r && cell_type_s) { - Const srmode = cell->getParam("\\SRMODE"); + Const srmode = cell->getParam(ID(SRMODE)); if (GetSize(srmode) >= 1) { if (srmode.bits[0] == State::S0) srmode.bits[0] = State::S1; else if (srmode.bits[0] == State::S1) srmode.bits[0] = State::S0; - cell->setParam("\\SRMODE", srmode); + cell->setParam(ID(SRMODE), srmode); } } else { if (cell_type_r) { - cell->setPort("\\nSET", cell->getPort("\\nRST")); - cell->unsetPort("\\nRST"); + cell->setPort(ID(nSET), cell->getPort(ID(nRST))); + cell->unsetPort(ID(nRST)); cell_type_r = false; cell_type_s = true; } else if (cell_type_s) { - cell->setPort("\\nRST", cell->getPort("\\nSET")); - cell->unsetPort("\\nSET"); + cell->setPort(ID(nRST), cell->getPort(ID(nSET))); + cell->unsetPort(ID(nSET)); cell_type_r = true; cell_type_s = false; } @@ -71,12 +71,12 @@ void invert_gp_dff(Cell *cell, bool invert_input) } if (cell_type_i) { - cell->setPort("\\Q", cell->getPort("\\nQ")); - cell->unsetPort("\\nQ"); + cell->setPort(ID::Q, cell->getPort(ID(nQ))); + cell->unsetPort(ID(nQ)); cell_type_i = false; } else { - cell->setPort("\\nQ", cell->getPort("\\Q")); - cell->unsetPort("\\Q"); + cell->setPort(ID(nQ), cell->getPort(ID::Q)); + cell->unsetPort(ID::Q); cell_type_i = true; } @@ -115,23 +115,23 @@ struct Greenpak4DffInvPass : public Pass { extra_args(args, argidx, design); pool<IdString> gp_dff_types; - gp_dff_types.insert("\\GP_DFF"); - gp_dff_types.insert("\\GP_DFFI"); - gp_dff_types.insert("\\GP_DFFR"); - gp_dff_types.insert("\\GP_DFFRI"); - gp_dff_types.insert("\\GP_DFFS"); - gp_dff_types.insert("\\GP_DFFSI"); - gp_dff_types.insert("\\GP_DFFSR"); - gp_dff_types.insert("\\GP_DFFSRI"); - - gp_dff_types.insert("\\GP_DLATCH"); - gp_dff_types.insert("\\GP_DLATCHI"); - gp_dff_types.insert("\\GP_DLATCHR"); - gp_dff_types.insert("\\GP_DLATCHRI"); - gp_dff_types.insert("\\GP_DLATCHS"); - gp_dff_types.insert("\\GP_DLATCHSI"); - gp_dff_types.insert("\\GP_DLATCHSR"); - gp_dff_types.insert("\\GP_DLATCHSRI"); + gp_dff_types.insert(ID(GP_DFF)); + gp_dff_types.insert(ID(GP_DFFI)); + gp_dff_types.insert(ID(GP_DFFR)); + gp_dff_types.insert(ID(GP_DFFRI)); + gp_dff_types.insert(ID(GP_DFFS)); + gp_dff_types.insert(ID(GP_DFFSI)); + gp_dff_types.insert(ID(GP_DFFSR)); + gp_dff_types.insert(ID(GP_DFFSRI)); + + gp_dff_types.insert(ID(GP_DLATCH)); + gp_dff_types.insert(ID(GP_DLATCHI)); + gp_dff_types.insert(ID(GP_DLATCHR)); + gp_dff_types.insert(ID(GP_DLATCHRI)); + gp_dff_types.insert(ID(GP_DLATCHS)); + gp_dff_types.insert(ID(GP_DLATCHSI)); + gp_dff_types.insert(ID(GP_DLATCHSR)); + gp_dff_types.insert(ID(GP_DLATCHSRI)); for (auto module : design->selected_modules()) { @@ -163,9 +163,9 @@ struct Greenpak4DffInvPass : public Pass { continue; } - if (cell->type == "\\GP_INV") { - SigBit in_bit = sigmap(cell->getPort("\\IN")); - SigBit out_bit = sigmap(cell->getPort("\\OUT")); + if (cell->type == ID(GP_INV)) { + SigBit in_bit = sigmap(cell->getPort(ID(IN))); + SigBit out_bit = sigmap(cell->getPort(ID(OUT))); inv_in2out[in_bit] = out_bit; inv_out2in[out_bit] = in_bit; inv_in2cell[in_bit] = cell; @@ -175,15 +175,15 @@ struct Greenpak4DffInvPass : public Pass { for (auto cell : dff_cells) { - SigBit d_bit = sigmap(cell->getPort("\\D")); - SigBit q_bit = sigmap(cell->hasPort("\\Q") ? cell->getPort("\\Q") : cell->getPort("\\nQ")); + SigBit d_bit = sigmap(cell->getPort(ID::D)); + SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(ID::Q) : cell->getPort(ID(nQ))); while (inv_out2in.count(d_bit)) { sig_use_cnt[d_bit]--; invert_gp_dff(cell, true); d_bit = inv_out2in.at(d_bit); - cell->setPort("\\D", d_bit); + cell->setPort(ID::D, d_bit); sig_use_cnt[d_bit]++; } @@ -197,10 +197,10 @@ struct Greenpak4DffInvPass : public Pass { inv_in2cell.erase(q_bit); invert_gp_dff(cell, false); - if (cell->hasPort("\\Q")) - cell->setPort("\\Q", new_q_bit); + if (cell->hasPort(ID::Q)) + cell->setPort(ID::Q, new_q_bit); else - cell->setPort("\\nQ", new_q_bit); + cell->setPort(ID(nQ), new_q_bit); } } } diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index aa1d7aa86..6a0e3031e 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2382,9 +2382,9 @@ module SB_SPRAM256KA ( // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167 //$setup(negedge STANDBY, posedge CLOCK, 1715); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206 - $setup(WREN, posedge CLK, 289); + $setup(WREN, posedge CLOCK, 289); // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222 - (posedge RCLK => (DATAOUT : 16'bx)) = 1821; + (posedge CLOCK => (DATAOUT : 16'bx)) = 1821; // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238 (posedge SLEEP => (DATAOUT : 16'b0)) = 1099; endspecify diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc index 1a139ffea..936c189ea 100644 --- a/techlibs/ice40/ice40_braminit.cc +++ b/techlibs/ice40/ice40_braminit.cc @@ -33,15 +33,15 @@ static void run_ice40_braminit(Module *module) uint16_t mem[256]; /* Only consider cells we're interested in */ - if (cell->type != "\\SB_RAM40_4K" && - cell->type != "\\SB_RAM40_4KNR" && - cell->type != "\\SB_RAM40_4KNW" && - cell->type != "\\SB_RAM40_4KNRNW") + if (cell->type != ID(SB_RAM40_4K) && + cell->type != ID(SB_RAM40_4KNR) && + cell->type != ID(SB_RAM40_4KNW) && + cell->type != ID(SB_RAM40_4KNRNW)) continue; - if (!cell->hasParam("\\INIT_FILE")) + if (!cell->hasParam(ID(INIT_FILE))) continue; - std::string init_file = cell->getParam("\\INIT_FILE").decode_string(); - cell->unsetParam("\\INIT_FILE"); + std::string init_file = cell->getParam(ID(INIT_FILE)).decode_string(); + cell->unsetParam(ID(INIT_FILE)); if (init_file == "") continue; diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index c098736e9..d7715135e 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -62,11 +62,11 @@ struct Ice40FfinitPass : public Pass { for (auto wire : module->selected_wires()) { - if (wire->attributes.count("\\init") == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec wirebits = sigmap(wire); - Const initval = wire->attributes.at("\\init"); + Const initval = wire->attributes.at(ID::init); init_wires.insert(wire); for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) @@ -93,9 +93,9 @@ struct Ice40FfinitPass : public Pass { } pool<IdString> sb_dff_types = { - "\\SB_DFF", "\\SB_DFFE", "\\SB_DFFSR", "\\SB_DFFR", "\\SB_DFFSS", "\\SB_DFFS", "\\SB_DFFESR", - "\\SB_DFFER", "\\SB_DFFESS", "\\SB_DFFES", "\\SB_DFFN", "\\SB_DFFNE", "\\SB_DFFNSR", "\\SB_DFFNR", - "\\SB_DFFNSS", "\\SB_DFFNS", "\\SB_DFFNESR", "\\SB_DFFNER", "\\SB_DFFNESS", "\\SB_DFFNES" + ID(SB_DFF), ID(SB_DFFE), ID(SB_DFFSR), ID(SB_DFFR), ID(SB_DFFSS), ID(SB_DFFS), ID(SB_DFFESR), + ID(SB_DFFER), ID(SB_DFFESS), ID(SB_DFFES), ID(SB_DFFN), ID(SB_DFFNE), ID(SB_DFFNSR), ID(SB_DFFNR), + ID(SB_DFFNSS), ID(SB_DFFNS), ID(SB_DFFNESR), ID(SB_DFFNER), ID(SB_DFFNESS), ID(SB_DFFNES) }; for (auto cell : module->selected_cells()) @@ -103,8 +103,8 @@ struct Ice40FfinitPass : public Pass { if (!sb_dff_types.count(cell->type)) continue; - SigSpec sig_d = cell->getPort("\\D"); - SigSpec sig_q = cell->getPort("\\Q"); + SigSpec sig_d = cell->getPort(ID::D); + SigSpec sig_q = cell->getPort(ID::Q); if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1) continue; @@ -133,14 +133,14 @@ struct Ice40FfinitPass : public Pass { if (type_str.back() == 'S') { type_str.back() = 'R'; cell->type = type_str; - cell->setPort("\\R", cell->getPort("\\S")); - cell->unsetPort("\\S"); + cell->setPort(ID::R, cell->getPort(ID::S)); + cell->unsetPort(ID::S); } else if (type_str.back() == 'R') { type_str.back() = 'S'; cell->type = type_str; - cell->setPort("\\S", cell->getPort("\\R")); - cell->unsetPort("\\R"); + cell->setPort(ID::S, cell->getPort(ID::R)); + cell->unsetPort(ID::R); } Wire *new_bit_d = module->addWire(NEW_ID); @@ -149,17 +149,17 @@ struct Ice40FfinitPass : public Pass { module->addNotGate(NEW_ID, bit_d, new_bit_d); module->addNotGate(NEW_ID, new_bit_q, bit_q); - cell->setPort("\\D", new_bit_d); - cell->setPort("\\Q", new_bit_q); + cell->setPort(ID::D, new_bit_d); + cell->setPort(ID::Q, new_bit_q); } for (auto wire : init_wires) { - if (wire->attributes.count("\\init") == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec wirebits = sigmap(wire); - Const &initval = wire->attributes.at("\\init"); + Const &initval = wire->attributes.at(ID::init); bool remove_attribute = true; for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) { @@ -170,7 +170,7 @@ struct Ice40FfinitPass : public Pass { } if (remove_attribute) - wire->attributes.erase("\\init"); + wire->attributes.erase(ID::init); } } } diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index a7649d7a0..ffb8c74b1 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -49,10 +49,10 @@ struct Ice40FfssrPass : public Pass { extra_args(args, argidx, design); pool<IdString> sb_dff_types; - sb_dff_types.insert("\\SB_DFF"); - sb_dff_types.insert("\\SB_DFFE"); - sb_dff_types.insert("\\SB_DFFN"); - sb_dff_types.insert("\\SB_DFFNE"); + sb_dff_types.insert(ID(SB_DFF)); + sb_dff_types.insert(ID(SB_DFFE)); + sb_dff_types.insert(ID(SB_DFFN)); + sb_dff_types.insert(ID(SB_DFFNE)); for (auto module : design->selected_modules()) { @@ -69,22 +69,22 @@ struct Ice40FfssrPass : public Pass { continue; } - if (cell->type != "$_MUX_") + if (cell->type != ID($_MUX_)) continue; - SigBit bit_a = sigmap(cell->getPort("\\A")); - SigBit bit_b = sigmap(cell->getPort("\\B")); + SigBit bit_a = sigmap(cell->getPort(ID::A)); + SigBit bit_b = sigmap(cell->getPort(ID::B)); if (bit_a.wire == nullptr || bit_b.wire == nullptr) - sr_muxes[sigmap(cell->getPort("\\Y"))] = cell; + sr_muxes[sigmap(cell->getPort(ID::Y))] = cell; } for (auto cell : ff_cells) { - if (cell->get_bool_attribute("\\dont_touch")) + if (cell->get_bool_attribute(ID(dont_touch))) continue; - SigSpec sig_d = cell->getPort("\\D"); + SigSpec sig_d = cell->getPort(ID::D); if (GetSize(sig_d) < 1) continue; @@ -95,9 +95,9 @@ struct Ice40FfssrPass : public Pass { continue; Cell *mux_cell = sr_muxes.at(bit_d); - SigBit bit_a = sigmap(mux_cell->getPort("\\A")); - SigBit bit_b = sigmap(mux_cell->getPort("\\B")); - SigBit bit_s = sigmap(mux_cell->getPort("\\S")); + SigBit bit_a = sigmap(mux_cell->getPort(ID::A)); + SigBit bit_b = sigmap(mux_cell->getPort(ID::B)); + SigBit bit_s = sigmap(mux_cell->getPort(ID::S)); log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); @@ -116,12 +116,12 @@ struct Ice40FfssrPass : public Pass { if (sr_val == State::S1) { cell->type = cell->type.str() + "SS"; - cell->setPort("\\S", sr_sig); - cell->setPort("\\D", bit_d); + cell->setPort(ID::S, sr_sig); + cell->setPort(ID::D, bit_d); } else { cell->type = cell->type.str() + "SR"; - cell->setPort("\\R", sr_sig); - cell->setPort("\\D", bit_d); + cell->setPort(ID::R, sr_sig); + cell->setPort(ID::D, bit_d); } } } diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 925ab31bb..18c1a58cf 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -41,26 +41,26 @@ static void run_ice40_opts(Module *module) for (auto cell : module->selected_cells()) { - if (!cell->type.in("\\SB_LUT4", "\\SB_CARRY", "$__ICE40_CARRY_WRAPPER")) + if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), ID($__ICE40_CARRY_WRAPPER))) continue; if (cell->has_keep_attr()) continue; - if (cell->type == "\\SB_LUT4") + if (cell->type == ID(SB_LUT4)) { sb_lut_cells.push_back(cell); continue; } - if (cell->type == "\\SB_CARRY") + if (cell->type == ID(SB_CARRY)) { SigSpec non_const_inputs, replacement_output; int count_zeros = 0, count_ones = 0; SigBit inbit[3] = { - get_bit_or_zero(cell->getPort("\\I0")), - get_bit_or_zero(cell->getPort("\\I1")), - get_bit_or_zero(cell->getPort("\\CI")) + get_bit_or_zero(cell->getPort(ID(I0))), + get_bit_or_zero(cell->getPort(ID(I1))), + get_bit_or_zero(cell->getPort(ID::CI)) }; for (int i = 0; i < 3; i++) if (inbit[i].wire == nullptr) { @@ -79,8 +79,8 @@ static void run_ice40_opts(Module *module) replacement_output = non_const_inputs; if (GetSize(replacement_output)) { - optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); - module->connect(cell->getPort("\\CO")[0], replacement_output); + optimized_co.insert(sigmap(cell->getPort(ID::CO)[0])); + module->connect(cell->getPort(ID::CO)[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized away SB_CARRY cell %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); @@ -89,15 +89,15 @@ static void run_ice40_opts(Module *module) continue; } - if (cell->type == "$__ICE40_CARRY_WRAPPER") + if (cell->type == ID($__ICE40_CARRY_WRAPPER)) { SigSpec non_const_inputs, replacement_output; int count_zeros = 0, count_ones = 0; SigBit inbit[3] = { - cell->getPort("\\A"), - cell->getPort("\\B"), - cell->getPort("\\CI") + cell->getPort(ID::A), + cell->getPort(ID::B), + cell->getPort(ID::CI) }; for (int i = 0; i < 3; i++) if (inbit[i].wire == nullptr) { @@ -116,7 +116,7 @@ static void run_ice40_opts(Module *module) replacement_output = non_const_inputs; if (GetSize(replacement_output)) { - optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); + optimized_co.insert(sigmap(cell->getPort(ID::CO)[0])); auto it = cell->attributes.find(ID(SB_LUT4.name)); if (it != cell->attributes.end()) { module->rename(cell, it->second.decode_string()); @@ -124,9 +124,9 @@ static void run_ice40_opts(Module *module) for (const auto &a : cell->attributes) if (a.first.begins_with("\\SB_LUT4.\\")) new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second; - else if (a.first == ID(src)) + else if (a.first == ID::src) new_attr.insert(std::make_pair(a.first, a.second)); - else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived))) + else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived)) continue; else if (a.first.begins_with("\\SB_CARRY.\\")) continue; @@ -134,22 +134,22 @@ static void run_ice40_opts(Module *module) log_abort(); cell->attributes = std::move(new_attr); } - module->connect(cell->getPort("\\CO")[0], replacement_output); + module->connect(cell->getPort(ID::CO)[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); - cell->type = "$lut"; - auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); - cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) }); - cell->setPort("\\Y", cell->getPort("\\O")); - cell->unsetPort("\\B"); - cell->unsetPort("\\CI"); - cell->unsetPort("\\I0"); - cell->unsetPort("\\I3"); - cell->unsetPort("\\CO"); - cell->unsetPort("\\O"); - cell->setParam("\\WIDTH", 4); - cell->unsetParam("\\I3_IS_CI"); + cell->type = ID($lut); + auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3))); + cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) }); + cell->setPort(ID::Y, cell->getPort(ID::O)); + cell->unsetPort(ID::B); + cell->unsetPort(ID::CI); + cell->unsetPort(ID(I0)); + cell->unsetPort(ID(I3)); + cell->unsetPort(ID::CO); + cell->unsetPort(ID::O); + cell->setParam(ID::WIDTH, 4); + cell->unsetParam(ID(I3_IS_CI)); } continue; } @@ -159,10 +159,10 @@ static void run_ice40_opts(Module *module) { SigSpec inbits; - inbits.append(get_bit_or_zero(cell->getPort("\\I0"))); - inbits.append(get_bit_or_zero(cell->getPort("\\I1"))); - inbits.append(get_bit_or_zero(cell->getPort("\\I2"))); - inbits.append(get_bit_or_zero(cell->getPort("\\I3"))); + inbits.append(get_bit_or_zero(cell->getPort(ID(I0)))); + inbits.append(get_bit_or_zero(cell->getPort(ID(I1)))); + inbits.append(get_bit_or_zero(cell->getPort(ID(I2)))); + inbits.append(get_bit_or_zero(cell->getPort(ID(I3)))); sigmap.apply(inbits); if (optimized_co.count(inbits[0])) goto remap_lut; @@ -177,23 +177,23 @@ static void run_ice40_opts(Module *module) module->design->scratchpad_set_bool("opt.did_something", true); log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell)); - cell->type ="$lut"; - cell->setParam("\\WIDTH", 4); - cell->setParam("\\LUT", cell->getParam("\\LUT_INIT")); - cell->unsetParam("\\LUT_INIT"); + cell->type = ID($lut); + cell->setParam(ID::WIDTH, 4); + cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT))); + cell->unsetParam(ID(LUT_INIT)); - cell->setPort("\\A", SigSpec({ - get_bit_or_zero(cell->getPort("\\I3")), - get_bit_or_zero(cell->getPort("\\I2")), - get_bit_or_zero(cell->getPort("\\I1")), - get_bit_or_zero(cell->getPort("\\I0")) + cell->setPort(ID::A, SigSpec({ + get_bit_or_zero(cell->getPort(ID(I3))), + get_bit_or_zero(cell->getPort(ID(I2))), + get_bit_or_zero(cell->getPort(ID(I1))), + get_bit_or_zero(cell->getPort(ID(I0))) })); - cell->setPort("\\Y", cell->getPort("\\O")[0]); - cell->unsetPort("\\I0"); - cell->unsetPort("\\I1"); - cell->unsetPort("\\I2"); - cell->unsetPort("\\I3"); - cell->unsetPort("\\O"); + cell->setPort(ID::Y, cell->getPort(ID::O)[0]); + cell->unsetPort(ID(I0)); + cell->unsetPort(ID(I1)); + cell->unsetPort(ID(I2)); + cell->unsetPort(ID(I3)); + cell->unsetPort(ID::O); cell->check(); simplemap_lut(module, cell); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 80bd05a84..59ada8bae 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -96,9 +96,9 @@ struct SynthIce40Pass : public ScriptPass log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); - log(" -flowmap\n"); - log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n"); - log("\n"); + log(" -flowmap\n"); + log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -126,7 +126,7 @@ struct SynthIce40Pass : public ScriptPass abc2 = false; vpr = false; abc9 = false; - flowmap = false; + flowmap = false; device_opt = "hx"; } @@ -345,6 +345,7 @@ struct SynthIce40Pass : public ScriptPass if (min_ce_use >= 0) { run("opt_merge"); run(stringf("dff2dffe -unmap-mince %d", min_ce_use)); + run("simplemap t:$dff"); } run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v"); run("opt_expr -mux_undef"); diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc index 3d43332e2..619888d38 100644 --- a/techlibs/sf2/sf2_iobs.cc +++ b/techlibs/sf2/sf2_iobs.cc @@ -34,14 +34,14 @@ static void handle_iobufs(Module *module, bool clkbuf_mode) for (auto cell : module->cells()) { - if (clkbuf_mode && cell->type == "\\SLE") { - for (auto bit : sigmap(cell->getPort("\\CLK"))) + if (clkbuf_mode && cell->type == ID(SLE)) { + for (auto bit : sigmap(cell->getPort(ID::CLK))) clk_bits.insert(bit); } - if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUFF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF", - "\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUFF_DIFF", "\\CLKBUF_DIFF", - "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) { - for (auto bit : sigmap(cell->getPort("\\PAD"))) + if (cell->type.in(ID(INBUF), ID(OUTBUF), ID(TRIBUFF), ID(BIBUF), ID(CLKBUF), ID(CLKBIBUF), + ID(INBUF_DIFF), ID(OUTBUF_DIFF), ID(BIBUFF_DIFF), ID(TRIBUFF_DIFF), ID(CLKBUF_DIFF), + ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF))) { + for (auto bit : sigmap(cell->getPort(ID(PAD)))) handled_io_bits.insert(bit); } } @@ -65,14 +65,14 @@ static void handle_iobufs(Module *module, bool clkbuf_mode) IdString buf_type, buf_port; if (wire->port_output) { - buf_type = "\\OUTBUF"; - buf_port = "\\D"; + buf_type = ID(OUTBUF); + buf_port = ID::D; } else if (clkbuf_mode && clk_bits.count(canonical_bit)) { - buf_type = "\\CLKBUF"; - buf_port = "\\Y"; + buf_type = ID(CLKBUF); + buf_port = ID::Y; } else { - buf_type = "\\INBUF"; - buf_port = "\\Y"; + buf_type = ID(INBUF); + buf_port = ID::Y; } Cell *c = module->addCell(NEW_ID, buf_type); @@ -96,7 +96,7 @@ static void handle_iobufs(Module *module, bool clkbuf_mode) module->rewrite_sigspecs(rewrite_function); for (auto &it : pad_bits) - it.first->setPort("\\PAD", it.second); + it.first->setPort(ID(PAD), it.second); } static void handle_clkint(Module *module) @@ -108,13 +108,13 @@ static void handle_clkint(Module *module) for (auto cell : module->cells()) { - if (cell->type == "\\SLE") { - for (auto bit : sigmap(cell->getPort("\\CLK"))) + if (cell->type == ID(SLE)) { + for (auto bit : sigmap(cell->getPort(ID::CLK))) clk_bits.insert(bit); } - if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF", - "\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) { - for (auto bit : sigmap(cell->getPort("\\Y"))) + if (cell->type.in(ID(CLKBUF), ID(CLKBIBUF), ID(CLKBUF_DIFF), ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF), + ID(CLKINT), ID(CLKINT_PRESERVE), ID(GCLKINT), ID(RCLKINT), ID(RGCLKINT))) { + for (auto bit : sigmap(cell->getPort(ID::Y))) handled_clk_bits.push_back(bit); } } @@ -134,10 +134,10 @@ static void handle_clkint(Module *module) for (auto &bit : sig) { SigBit canonical_bit = sigmap(bit); if (clk_bits.count(canonical_bit)) { - Cell *c = module->addCell(NEW_ID, "\\CLKINT"); + Cell *c = module->addCell(NEW_ID, ID(CLKINT)); SigBit new_bit = module->addWire(NEW_ID); - c->setPort("\\A", new_bit); - c->setPort("\\Y", bit); + c->setPort(ID::A, new_bit); + c->setPort(ID::Y, bit); log("Added %s cell %s for clock signal %s.\n", log_id(c->type), log_id(c), log_signal(bit)); clk_bits.erase(canonical_bit); did_something = true; diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 749b1e0a7..f086291ab 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -302,7 +302,7 @@ CELLS = [ Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index ac4ad4e36..3021f6b5a 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -7072,6 +7072,7 @@ module IOBUFDS (...); output O; (* iopad_external_pin *) inout IO; + (* iopad_external_pin *) inout IOB; input I; input T; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8553efd6b..ac4f5bcf4 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -393,8 +393,6 @@ struct SynthXilinxPass : public ScriptPass run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')"); run("clean", " (skip if '-nosrl' and '-widemux=0')"); } - - run("techmap -map +/cmp2lut.v -D LUT_WIDTH=" + lut_size_s); } if (check_label("map_dsp", "(skip if '-nodsp')")) { @@ -460,6 +458,7 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("coarse")) { + run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=" + lut_size_s); run("alumacc"); run("share"); run("opt"); diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index 13a0b9b83..ac9b57fe1 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -146,12 +146,12 @@ struct XilinxDffOptPass : public Pass { if (cell->get_bool_attribute(ID::keep)) continue; if (cell->type == ID(INV)) { - SigBit sigout = sigmap(cell->getPort(ID(O))); - SigBit sigin = sigmap(cell->getPort(ID(I))); + SigBit sigout = sigmap(cell->getPort(ID::O)); + SigBit sigin = sigmap(cell->getPort(ID::I)); bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell); } else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) { - SigBit sigout = sigmap(cell->getPort(ID(O))); - const Const &init = cell->getParam(ID(INIT)); + SigBit sigout = sigmap(cell->getPort(ID::O)); + const Const &init = cell->getParam(ID::INIT); std::vector<SigBit> sigin; sigin.push_back(sigmap(cell->getPort(ID(I0)))); if (cell->type == ID(LUT1)) @@ -199,7 +199,7 @@ lut_sigin_done: continue; // Don't bother if D has more than one use. - SigBit sig_D = sigmap(cell->getPort(ID(D))); + SigBit sig_D = sigmap(cell->getPort(ID::D)); if (bit_uses[sig_D] > 2) continue; @@ -223,7 +223,7 @@ lut_sigin_done: bool worthy_post_r = false; // First, unmap CE. - SigBit sig_Q = sigmap(cell->getPort(ID(Q))); + SigBit sig_Q = sigmap(cell->getPort(ID::Q)); SigBit sig_CE = sigmap(cell->getPort(ID(CE))); LutData lut_ce = LutData(Const(2, 2), {sig_CE}); auto it_CE = bit_to_lut.find(sig_CE); @@ -247,7 +247,7 @@ lut_sigin_done: // Second, unmap S, if any. lut_d_post_s = lut_d_post_ce; if (has_s) { - SigBit sig_S = sigmap(cell->getPort(ID(S))); + SigBit sig_S = sigmap(cell->getPort(ID::S)); LutData lut_s = LutData(Const(2, 2), {sig_S}); bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool(); auto it_S = bit_to_lut.find(sig_S); @@ -269,7 +269,7 @@ lut_sigin_done: // Third, unmap R, if any. lut_d_post_r = lut_d_post_s; if (has_r) { - SigBit sig_R = sigmap(cell->getPort(ID(R))); + SigBit sig_R = sigmap(cell->getPort(ID::R)); LutData lut_r = LutData(Const(2, 2), {sig_R}); bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool(); auto it_R = bit_to_lut.find(sig_R); @@ -307,11 +307,11 @@ unmap: // Okay, we're doing it. Unmap ports. if (worthy_post_r) { cell->unsetParam(ID(IS_R_INVERTED)); - cell->setPort(ID(R), Const(0, 1)); + cell->setPort(ID::R, Const(0, 1)); } if (has_s && (worthy_post_r || worthy_post_s)) { cell->unsetParam(ID(IS_S_INVERTED)); - cell->setPort(ID(S), Const(0, 1)); + cell->setPort(ID::S, Const(0, 1)); } cell->setPort(ID(CE), Const(1, 1)); cell->unsetParam(ID(IS_D_INVERTED)); @@ -342,9 +342,9 @@ unmap: } lut_cell->attributes = cell_d->attributes; Wire *lut_out = module->addWire(NEW_ID); - lut_cell->setParam(ID(INIT), final_lut.first); - cell->setPort(ID(D), lut_out); - lut_cell->setPort(ID(O), lut_out); + lut_cell->setParam(ID::INIT, final_lut.first); + cell->setPort(ID::D, lut_out); + lut_cell->setPort(ID::O, lut_out); lut_cell->setPort(ID(I0), final_lut.second[0]); if (GetSize(final_lut.second) >= 2) lut_cell->setPort(ID(I1), final_lut.second[1]); diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys index 0bcc4e011..eb94177ad 100644 --- a/tests/arch/anlogic/fsm.ys +++ b/tests/arch/anlogic/fsm.ys @@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT2 -select -assert-count 5 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 select -assert-count 6 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D +select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys index a2db2ad98..aef720d46 100644 --- a/tests/arch/efinix/fsm.ys +++ b/tests/arch/efinix/fsm.ys @@ -10,7 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 6 t:EFX_FF -select -assert-count 15 t:EFX_LUT4 +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 6 t:EFX_FF select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys new file mode 100644 index 000000000..a3361ca43 --- /dev/null +++ b/tests/opt/opt_expr_alu.ys @@ -0,0 +1,63 @@ +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b0} + 1'b1; +endmodule +EOT + +alumacc +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b1} + 1'b1; +endmodule +EOT + +alumacc +select -assert-count 1 t:$alu +select -assert-count none t:$alu t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b1} - 1'b1; +endmodule +EOT + +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [3:0] y); +assign y = {a,3'b101} - 1'b1; +endmodule +EOT + +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [3:0] y); +assign y = {a,3'b101} - 1'b1; +endmodule +EOT + +alumacc +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys new file mode 100644 index 000000000..21439fd53 --- /dev/null +++ b/tests/opt/opt_expr_xor.ys @@ -0,0 +1,52 @@ +read_verilog <<EOT +module top(input a, output [3:0] y); +assign y[0] = a^1'b0; +assign y[1] = 1'b1^a; +assign y[2] = a~^1'b0; +assign y[3] = 1'b1^~a; +endmodule +EOT +design -save read +select -assert-count 2 t:$xor +select -assert-count 2 t:$xnor + +equiv_opt opt_expr +design -load postopt +select -assert-none t:$xor +select -assert-none t:$xnor +select -assert-count 2 t:$not + + +design -load read +simplemap +equiv_opt opt_expr +design -load postopt +select -assert-none t:$_XOR_ +select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ +select -assert-count 3 t:$_NOT_ + + +design -reset +read_verilog -icells <<EOT +module top(input a, output [1:0] y); +$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0])); +$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1])); +endmodule +EOT +select -assert-count 2 t:$_XNOR_ +equiv_opt opt_expr +design -load postopt +select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ +select -assert-count 1 t:$_NOT_ + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] w, x, y, z); +assign w = a^1'b0; +assign x = a^1'b1; +assign y = a~^1'b0; +assign z = a~^1'b1; +endmodule +EOT +equiv_opt opt_expr diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys index a29c29df6..0176f09c7 100644 --- a/tests/opt/opt_merge_init.ys +++ b/tests/opt/opt_merge_init.ys @@ -20,6 +20,7 @@ endmodule EOT opt_merge +select -assert-count 1 t:$dff select -assert-count 1 a:init=1'0 @@ -46,4 +47,31 @@ endmodule EOT opt_merge +select -assert-count 1 t:$dff select -assert-count 1 a:init=2'bx1 + + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, (* init = 1'b0 *) output o, /* NB: no init here! */ output p); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffo ( + .CLK(clk), + .D(i), + .Q(o) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffp ( + .CLK(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 2 t:$dff diff --git a/tests/opt/opt_merge_keep.ys b/tests/opt/opt_merge_keep.ys new file mode 100644 index 000000000..2a9202901 --- /dev/null +++ b/tests/opt/opt_merge_keep.ys @@ -0,0 +1,64 @@ +read_verilog -icells <<EOT +module top(input clk, i, output o, p); + (* keep *) + \$_DFF_P_ ffo ( + .C(clk), + .D(i), + .Q(o) + ); + \$_DFF_P_ ffp ( + .C(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 a:keep + + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output o, p); + \$_DFF_P_ ffo ( + .C(clk), + .D(i), + .Q(o) + ); + (* keep *) + \$_DFF_P_ ffp ( + .C(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 a:keep + + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output o, p); + (* keep *) + \$_DFF_P_ ffo ( + .C(clk), + .D(i), + .Q(o) + ); + (* keep *) + \$_DFF_P_ ffp ( + .C(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 2 t:$_DFF_P_ +select -assert-count 2 a:keep diff --git a/tests/select/no_warn_assert.ys b/tests/select/no_warn_assert.ys new file mode 100644 index 000000000..889315826 --- /dev/null +++ b/tests/select/no_warn_assert.ys @@ -0,0 +1,2 @@ +logger -expect-no-warnings +select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i diff --git a/tests/select/no_warn_prefixed_arg_memb.ys b/tests/select/no_warn_prefixed_arg_memb.ys new file mode 100644 index 000000000..596a6ed70 --- /dev/null +++ b/tests/select/no_warn_prefixed_arg_memb.ys @@ -0,0 +1,5 @@ +logger -expect-no-warnings +read_verilog ../../examples/igloo2/example.v +hierarchy +proc +select example/t:$add diff --git a/tests/select/no_warn_prefixed_empty_select_arg.ys b/tests/select/no_warn_prefixed_empty_select_arg.ys new file mode 100644 index 000000000..617e0d63e --- /dev/null +++ b/tests/select/no_warn_prefixed_empty_select_arg.ys @@ -0,0 +1,3 @@ +logger -expect-no-warnings +select n:foo/bar* +select t:$assert diff --git a/tests/select/run-test.sh b/tests/select/run-test.sh new file mode 100755 index 000000000..44ce7e674 --- /dev/null +++ b/tests/select/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.ys; do + echo "Running $x.." + ../../yosys -ql ${x%.ys}.log $x +done diff --git a/tests/select/warn_empty_select_arg.ys b/tests/select/warn_empty_select_arg.ys new file mode 100644 index 000000000..55aca8eb6 --- /dev/null +++ b/tests/select/warn_empty_select_arg.ys @@ -0,0 +1,3 @@ +logger -expect warning "did not match any module." 1 +logger -expect warning "did not match any object." 1 +select foo/bar diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v new file mode 100644 index 000000000..7236ac3a5 --- /dev/null +++ b/tests/simple/dynslice.v @@ -0,0 +1,12 @@ +module dynslice ( + input clk , + input [9:0] ctrl , + input [15:0] din , + input [3:0] sel , + output reg [127:0] dout +); +always @(posedge clk) +begin + dout[ctrl*sel+:16] <= din ; +end +endmodule diff --git a/tests/svtypes/enum_simple.sv b/tests/svtypes/enum_simple.sv index ccaf50da0..4e4d5871c 100644 --- a/tests/svtypes/enum_simple.sv +++ b/tests/svtypes/enum_simple.sv @@ -5,8 +5,9 @@ module enum_simple(input clk, input rst); typedef enum logic [1:0] { ts0, ts1, ts2, ts3 } states_t; - (states_t) state; - (states_t) enum_const = ts1; + states_t state; + (states_t) state1; + states_t enum_const = ts1; always @(posedge clk) begin if (rst) begin diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv index 577e484ad..37e63c1d0 100644 --- a/tests/svtypes/typedef_memory.sv +++ b/tests/svtypes/typedef_memory.sv @@ -1,7 +1,7 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); typedef logic [3:0] ram16x4_t[0:15]; - (ram16x4_t) mem; + ram16x4_t mem; always @(posedge clk) begin if (wen) mem[addr] <= wdata; diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv index f3089bf55..6d65131db 100644 --- a/tests/svtypes/typedef_memory_2.sv +++ b/tests/svtypes/typedef_memory_2.sv @@ -1,7 +1,7 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); typedef logic [3:0] nibble; - (nibble) mem[0:15]; + nibble mem[0:15]; always @(posedge clk) begin if (wen) mem[addr] <= wdata; diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv index b766f10cf..57a78c53a 100644 --- a/tests/svtypes/typedef_package.sv +++ b/tests/svtypes/typedef_package.sv @@ -5,8 +5,8 @@ endpackage module top; - (* keep *) (pkg::uint8_t) a = 8'hAA; - (* keep *) (pkg::enum8_t) b_enum = pkg::bb; + (* keep *) pkg::uint8_t a = 8'hAA; + (* keep *) pkg::enum8_t b_enum = pkg::bb; always @* assert(a == 8'hAA); always @* assert(b_enum == 8'hBB); diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv index ddbd471e0..d838dd828 100644 --- a/tests/svtypes/typedef_param.sv +++ b/tests/svtypes/typedef_param.sv @@ -6,12 +6,12 @@ module top; typedef logic [1:0] uint2_t; typedef logic signed [3:0] int4_t; typedef logic signed [7:0] int8_t; - typedef (int8_t) char_t; + typedef int8_t char_t; - parameter (uint2_t) int2 = 2'b10; - localparam (int4_t) int4 = -1; - localparam (int8_t) int8 = int4; - localparam (char_t) ch = int8; + parameter uint2_t int2 = 2'b10; + localparam int4_t int4 = -1; + localparam int8_t int8 = int4; + localparam char_t ch = int8; `STATIC_ASSERT(int2 == 2'b10); diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv index 1c45c7057..5507d84f2 100644 --- a/tests/svtypes/typedef_scopes.sv +++ b/tests/svtypes/typedef_scopes.sv @@ -4,32 +4,39 @@ typedef enum logic {s0, s1} outer_enum_t; module top; - (outer_uint4_t) u4_i = 8'hA5; - (outer_enum_t) enum4_i = s0; + outer_uint4_t u4_i = 8'hA5; + outer_enum_t enum4_i = s0; always @(*) assert(u4_i == 4'h5); always @(*) assert(enum4_i == 1'b0); typedef logic [3:0] inner_type; typedef enum logic [2:0] {s2=2, s3, s4} inner_enum_t; - (inner_type) inner_i1 = 8'h5A; - (inner_enum_t) inner_enum1 = s3; + inner_type inner_i1 = 8'h5A; + inner_enum_t inner_enum1 = s3; always @(*) assert(inner_i1 == 4'hA); always @(*) assert(inner_enum1 == 3'h3); if (1) begin: genblock typedef logic [7:0] inner_type; - parameter (inner_type) inner_const = 8'hA5; + parameter inner_type inner_const = 8'hA5; typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t; - (inner_type) inner_gb_i = inner_const; //8'hA5; - (inner_enum_t) inner_gb_enum1 = s7; + inner_type inner_gb_i = inner_const; //8'hA5; + inner_enum_t inner_gb_enum1 = s7; always @(*) assert(inner_gb_i == 8'hA5); always @(*) assert(inner_gb_enum1 == 3'h7); end - (inner_type) inner_i2 = 8'h42; - (inner_enum_t) inner_enum2 = s4; + inner_type inner_i2 = 8'h42; + inner_enum_t inner_enum2 = s4; always @(*) assert(inner_i2 == 4'h2); always @(*) assert(inner_enum2 == 3'h4); +endmodule + +typedef logic[7:0] between_t; +module other; + between_t a = 8'h42; + always @(*) assert(a == 8'h42); endmodule + diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv index 7e760dee4..8f89910e5 100644 --- a/tests/svtypes/typedef_simple.sv +++ b/tests/svtypes/typedef_simple.sv @@ -3,12 +3,12 @@ module top; typedef logic [1:0] uint2_t; typedef logic signed [3:0] int4_t; typedef logic signed [7:0] int8_t; - typedef (int8_t) char_t; + typedef int8_t char_t; - (* keep *) (uint2_t) int2 = 2'b10; - (* keep *) (int4_t) int4 = -1; - (* keep *) (int8_t) int8 = int4; - (* keep *) (char_t) ch = int8; + (* keep *) uint2_t int2 = 2'b10; + (* keep *) int4_t int4 = -1; + (* keep *) int8_t int8 = int4; + (* keep *) char_t ch = int8; always @* assert(int2 == 2'b10); diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys new file mode 100644 index 000000000..7c8a63692 --- /dev/null +++ b/tests/techmap/cmp2lcu.ys @@ -0,0 +1,52 @@ +read_verilog <<EOT +module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les); +assign gtu = a > b; +assign gts = $signed(a) > $signed(b); +assign ltu = a < b; +assign lts = $signed(a) < $signed(b); +assign geu = a >= b; +assign ges = $signed(a) >= $signed(b); +assign leu = a <= b; +assign les = $signed(a) <= $signed(b); +endmodule +EOT + +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=5 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + +design -load preopt +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=7 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + + +design -reset +read_verilog <<EOT +module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les); +wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]}; +wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]}; +assign gtu = c > d; +assign gts = $signed(c) > $signed(d); +assign ltu = c < d; +assign lts = $signed(c) < $signed(d); +assign geu = c >= d; +assign ges = $signed(c) >= $signed(d); +assign leu = c <= d; +assign les = $signed(c) <= $signed(d); +endmodule +EOT +design -save gold + +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=2 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + +design -load preopt +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=4 %i +select -assert-none t:$gt t:$ge t:$lt t:$le diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys index 25ea94dfc..df029b3a0 100644 --- a/tests/techmap/iopadmap.ys +++ b/tests/techmap/iopadmap.ys @@ -55,13 +55,19 @@ obuf b (.i(i), .o(tmp)); assign o = tmp; endmodule +module k(inout o, o2); +assign o = 1'bz; +endmodule + EOT opt_clean tribuf simplemap -iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j +iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j k opt_clean +hierarchy -check +check select -assert-count 1 a/t:ibuf select -assert-count 1 a/t:obuf @@ -140,6 +146,8 @@ select -assert-count 0 i/t:obuf select -assert-count 1 j/t:ibuf select -assert-count 1 j/t:obuf +select -assert-count 2 k/t:iobuf + # Check that \init attributes get moved from output buffer # to buffer input diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys index c2f42d50b..8403586bd 100644 --- a/tests/techmap/techmap_replace.ys +++ b/tests/techmap/techmap_replace.ys @@ -16,3 +16,21 @@ EOT techmap -map %techmap select -assert-any w:s0.asdf select -assert-any c:s0.blah + +read_verilog <<EOT +module sub(input i, output o, input j); +wire _TECHMAP_REPLACE_.asdf = i ; +barfoo _TECHMAP_REPLACE_.blah (i, o, j); +endmodule +EOT +design -stash techmap + +read_verilog <<EOT +module top(input i, output o); +sub s0(i, o); +endmodule +EOT + +techmap -map %techmap +select -assert-any w:s0.asdf +select -assert-any c:s0.blah diff --git a/tests/various/bug1781.ys b/tests/various/bug1781.ys new file mode 100644 index 000000000..60dcc0830 --- /dev/null +++ b/tests/various/bug1781.ys @@ -0,0 +1,33 @@ +read_verilog <<EOT + +module top(input clk, input rst); + +reg [1:0] state; + +always @(posedge clk, posedge rst) begin + if (rst) + state <= 0; + else + case (state) + 2'b00: state <= 2'b01; + 2'b01: state <= 2'b10; + 2'b10: state <= 2'b00; + endcase +end + +sub sub_i(.i(state == 0)); + +endmodule + + +(* blackbox, keep *) +module sub(input i); +endmodule + +EOT + +proc +fsm + +# Make sure there is a driver +select -assert-any t:sub %ci %a w:* %i %ci c:* %i diff --git a/tests/various/exec.ys b/tests/various/exec.ys new file mode 100644 index 000000000..0eec00719 --- /dev/null +++ b/tests/various/exec.ys @@ -0,0 +1,6 @@ +exec -expect-return 0 -- exit 0 +exec -expect-return 27 -- exit 27 +exec -expect-stdout nana -expect-stdout api -not-expect-stdout giraffe -- echo "bananapie" + +logger -expect error "stdout did have a line" 1 +exec -not-expect-stdout giraffe -- echo "giraffe" diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys new file mode 100644 index 000000000..408e16f05 --- /dev/null +++ b/tests/various/ice40_mince_abc9.ys @@ -0,0 +1,17 @@ +read_verilog <<EOT + +module top(input clk, ce, input [2:0] a, b, output reg [2:0] q); + + reg [2:0] aa, bb; + + always @(posedge clk) begin + if (ce) begin + aa <= a; + end + bb <= b; + q <= aa + bb; + end +endmodule +EOT + +synth_ice40 -abc9 -dffe_min_ce_use 4 diff --git a/tests/various/sv_defines.ys b/tests/various/sv_defines.ys new file mode 100644 index 000000000..8e70ee0ee --- /dev/null +++ b/tests/various/sv_defines.ys @@ -0,0 +1,33 @@ +# Check that basic macro expansions do what you'd expect + +read_verilog <<EOT +`define empty_arglist() 123 +`define one_arg(x) 123+x +`define opt_arg(x = 1) 123+x +`define two_args(x, y = (1+23)) x+y +`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y + +module top; + localparam a = `empty_arglist(); + localparam b = `one_arg(10); + localparam c = `opt_arg(10); + localparam d = `opt_arg(); + localparam e = `two_args(1,2); + localparam f = `two_args(1); + localparam g = `nested_comma(1, 2); + localparam h = `nested_comma({31'b0, (1'b0)}); + localparam i = `nested_comma(, 1); + + generate + if (a != 123) $error("a bad"); + if (b != 133) $error("b bad"); + if (c != 133) $error("c bad"); + if (d != 124) $error("d bad"); + if (e != 3) $error("e bad"); + if (f != 25) $error("f bad"); + if (g != 3) $error("g bad"); + if (h != 3) $error("h bad"); + if (i != 2) $error("i bad"); + endgenerate +endmodule +EOT diff --git a/tests/various/sv_defines_dup.ys b/tests/various/sv_defines_dup.ys new file mode 100644 index 000000000..38418ba8f --- /dev/null +++ b/tests/various/sv_defines_dup.ys @@ -0,0 +1,5 @@ +# Check for duplicate arguments +logger -expect error "Duplicate macro arguments with name `x'" 1 +read_verilog <<EOT +`define duplicate_arg(x, x) +EOT diff --git a/tests/various/sv_defines_mismatch.ys b/tests/various/sv_defines_mismatch.ys new file mode 100644 index 000000000..ab6e899de --- /dev/null +++ b/tests/various/sv_defines_mismatch.ys @@ -0,0 +1,5 @@ +# Check that we spot mismatched brackets +logger -expect error "Mismatched brackets in macro argument: \[ and }." 1 +read_verilog <<EOT +`define foo(x=[1,2}) +EOT diff --git a/tests/various/sv_defines_too_few.ys b/tests/various/sv_defines_too_few.ys new file mode 100644 index 000000000..295884809 --- /dev/null +++ b/tests/various/sv_defines_too_few.ys @@ -0,0 +1,7 @@ +# Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no" +# arguments actually passes 1 empty argument). +logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1 +read_verilog <<EOT +`define foo(x=1, y) +`foo() +EOT |