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-rw-r--r--passes/techmap/abc9.cc2
-rw-r--r--techlibs/xilinx/synth_xilinx.cc3
2 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 4e7bdfa8f..e234ab28d 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -29,7 +29,7 @@
"&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\
"&st; &if -g -K 6; &synch2; &if {W}; &save; &load"
#else
-#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; "*/"&retime; &dch -f; &ps -l; &if {W} {D} -v; "/*"&mfs; "*/"&ps -l"
+#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &st; &dch -f; &ps -l; &if {W} {D} -v; "/*"&mfs; "*/"&ps -l"
#endif
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index db43e13c1..d3f096220 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -25,7 +25,8 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-#define XC7_WIRE_DELAY "160"
+#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
+ // to one LUT6 (instead of a LUT5 + LUT2)
struct SynthXilinxPass : public ScriptPass
{