diff options
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 18 | ||||
| -rw-r--r-- | tests/various/hierarchy.sh | 56 | ||||
| -rwxr-xr-x | tests/various/run-test.sh | 10 |
3 files changed, 74 insertions, 10 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 332ebdfbb..f112e969e 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -523,15 +523,15 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db) // Is this an array instance if (celltype.substr(0, 7) == "$array:") { celltype = basic_cell_type(celltype); - // Is this cell is a module instance? - if (celltype[0] != '$') { - auto instModule = design->module(celltype); - // If there is no instance for this, issue a warning. - if (instModule == NULL) { - log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str()); - } - if (instModule != NULL) - score = max(score, find_top_mod_score(design, instModule, db) + 1); + } + // Is this cell a module instance? + if (celltype[0] != '$') { + auto instModule = design->module(celltype); + // If there is no instance for this, issue a warning. + if (instModule == NULL) { + log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str()); + } else { + score = max(score, find_top_mod_score(design, instModule, db) + 1); } } } diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh new file mode 100644 index 000000000..dcb4dc056 --- /dev/null +++ b/tests/various/hierarchy.sh @@ -0,0 +1,56 @@ +#!/usr/bin/env bash +# Simple test of hierarchy -auto-top. + +set -e + +../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module" + read_verilog << EOV + module TOP(a, y); + input a; + output [31:0] y; + + aoi12 p [31:0] (a, y); + endmodule + + module aoi12(a, y); + input a; + output y; + assign y = ~a; + endmodule + EOV + hierarchy -auto-top +EOY + +../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module" + read_verilog << EOV + module aoi12(a, y); + input a; + output y; + assign y = ~a; + endmodule + + module TOP(a, y); + input a; + output [31:0] y; + + aoi12 foo (a, y); + endmodule + EOV + hierarchy -auto-top +EOY + +../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module." + read_verilog << EOV + module aoi12(a, y); + input a; + output y; + assign y = ~a; + endmodule + + module noTop(a, y); + input a; + output [31:0] y; + endmodule + EOV + hierarchy -auto-top +EOY diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh index 67e1beb23..7cd1a8650 100755 --- a/tests/various/run-test.sh +++ b/tests/various/run-test.sh @@ -1,6 +1,14 @@ -#!/bin/bash +#!/usr/bin/env bash set -e for x in *.ys; do echo "Running $x.." ../../yosys -ql ${x%.ys}.log $x done +# Run any .sh files in this directory (with the exception of the file - run-test.sh +shell_tests=$(echo *.sh | sed -e 's/run-test.sh//') +if [ "$shell_tests" ]; then + for s in $shell_tests; do + echo "Running $s.." + bash $s >& ${s%.sh}.log + done +fi |