diff options
| -rw-r--r-- | frontends/verilog/preproc.cc | 10 | ||||
| -rw-r--r-- | tests/verilog/doubleslash.ys | 19 |
2 files changed, 29 insertions, 0 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 17f567587..883531e78 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -142,6 +142,16 @@ static std::string next_token(bool pass_newline = false) return_char(ch); } } + else if (ch == '\\') + { + while ((ch = next_char()) != 0) { + if (ch < 33 || ch > 126) { + return_char(ch); + break; + } + token += ch; + } + } else if (ch == '/') { if ((ch = next_char()) != 0) { diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys new file mode 100644 index 000000000..8a51f12c2 --- /dev/null +++ b/tests/verilog/doubleslash.ys @@ -0,0 +1,19 @@ +read_verilog -sv <<EOT +module doubleslash + (input logic a, + input logic b, + output logic z); + + logic \a//b ; + + assign \a//b = a & b; + assign z = ~\a//b ; + +endmodule : doubleslash +EOT + +hierarchy +proc +opt -full + +write_verilog doubleslash.v |