diff options
| -rw-r--r-- | techlibs/common/techmap.v | 3 | ||||
| -rwxr-xr-x | tests/techmap/run-test.sh | 2 | ||||
| -rw-r--r-- | tests/techmap/shiftx2mux.ys | 11 |
3 files changed, 14 insertions, 2 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 75a51e55e..be6530eb4 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -152,10 +152,11 @@ module _90_shift_shiftx (A, B, Y); localparam len = 2**(B_WIDTH-1); localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH; wire [len-1:0] T, F, AA; + wire [(A_WIDTH+Y_WIDTH2*2):0] Apad = {{Y_WIDTH2*2{extbit}}, A}; genvar i; for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2]; - assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}}; + assign T[i/2 +: Y_WIDTH2] = Apad[i+Y_WIDTH2 +: Y_WIDTH2]; assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2]; end wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index 96489ff15..c16f204d9 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x" + echo " @../../yosys -ql ${x%.ys}.log -e 'select out of bounds' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys index c13b5f600..eb29680f6 100644 --- a/tests/techmap/shiftx2mux.ys +++ b/tests/techmap/shiftx2mux.ys @@ -108,3 +108,14 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -reset +read_verilog <<EOT +module top(input [6:0] A, input [1:0] B, output [1:0] Y); +wire [7:0] AA = {1'bx, A}; +assign Y = AA[B*2 +: 2]; +endmodule +EOT +opt +wreduce +equiv_opt techmap |