diff options
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 8 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 6 |
3 files changed, 9 insertions, 7 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 39520bd51..9b43c250e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -431,7 +431,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "+:" { return TOK_POS_INDEXED; } "-:" { return TOK_NEG_INDEXED; } -".*" { return TOK_AUTOCONNECT_ALL; } +".*" { return TOK_WILDCARD_CONNECT; } [-+]?[=*]> { if (!specify_mode) REJECT; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 5ec8e66a6..2c7304cc4 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -138,7 +138,7 @@ struct specify_rise_fall { %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP -%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL +%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH @@ -1581,8 +1581,10 @@ cell_port: delete $3; free_attr($1); } | - attr TOK_AUTOCONNECT_ALL { - astbuf2->attributes[ID(implicit_port_conns)] = AstNode::mkconst_int(1, false); + attr TOK_WILDCARD_CONNECT { + if (!sv_mode) + frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode."); + astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false); }; always_comb_or_latch: diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c298a6600..fa4a8ea29 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -992,7 +992,7 @@ struct HierarchyPass : public Pass { if (wire->port_input && wire->attributes.count("\\defaultvalue")) defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue"); } - // Process SV implicit port connections + // Process SV implicit wildcard port connections std::set<Module*> blackbox_derivatives; std::vector<Module*> design_modules = design->modules(); @@ -1000,7 +1000,7 @@ struct HierarchyPass : public Pass { { for (auto cell : module->cells()) { - if (!cell->get_bool_attribute(ID(implicit_port_conns))) + if (!cell->get_bool_attribute(ID(wildcard_port_conns))) continue; Module *m = design->module(cell->type); @@ -1042,7 +1042,7 @@ struct HierarchyPass : public Pass { RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); cell->setPort(wire->name, parent_wire); } - cell->attributes.erase(ID(implicit_port_conns)); + cell->attributes.erase(ID(wildcard_port_conns)); } } |