diff options
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 284d5db31..d19d837ff 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -987,6 +987,7 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates) for (auto cell : candidates) { + if (cell->type != ID($dff)) continue; SigBit clock = cell->getPort(ID::CLK); bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool(); database[make_pair(clock, int(clock_pol))].insert(cell); |