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-rw-r--r--kernel/rtlil.h2
-rw-r--r--misc/py_wrap_generator.py2
2 files changed, 1 insertions, 3 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6170ea55e..f03f27617 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1339,7 +1339,6 @@ public:
RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
- RTLIL::SigSpec Bu0 (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
@@ -1520,7 +1519,6 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
std::vector<RTLIL::SwitchRule*> switches;
~CaseRule();
- void optimize();
bool empty() const;
diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 38bd6129e..2de3c1f99 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -997,7 +997,7 @@ sources = [
Source("kernel/cost",[])
]
-blacklist_methods = ["YOSYS_NAMESPACE::Pass::run_register", "YOSYS_NAMESPACE::Module::Pow", "YOSYS_NAMESPACE::Module::Bu0", "YOSYS_NAMESPACE::CaseRule::optimize"]
+blacklist_methods = ["YOSYS_NAMESPACE::Pass::run_register", "YOSYS_NAMESPACE::Module::Pow"]
enum_names = ["State","SyncType","ConstFlags"]