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-rw-r--r--tests/ecp5/adffs.ys8
-rw-r--r--tests/efinix/adffs.ys8
2 files changed, 8 insertions, 8 deletions
diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys
index b129419d3..c6780e565 100644
--- a/tests/ecp5/adffs.ys
+++ b/tests/ecp5/adffs.ys
@@ -3,7 +3,7 @@ design -save read
hierarchy -top adff
proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
@@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top adffn
proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
@@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
hierarchy -top dffs
proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
@@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
hierarchy -top ndffnr
proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys
index 791626428..1069c6c5c 100644
--- a/tests/efinix/adffs.ys
+++ b/tests/efinix/adffs.ys
@@ -3,7 +3,7 @@ design -save read
hierarchy -top adff
proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
@@ -15,7 +15,7 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top adffn
proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
@@ -27,7 +27,7 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffs
proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
@@ -40,7 +40,7 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
design -load read
hierarchy -top ndffnr
proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF