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-rw-r--r--manual/PRESENTATION_ExAdv.tex38
-rw-r--r--manual/PRESENTATION_ExAdv/Makefile5
-rw-r--r--manual/PRESENTATION_ExAdv/mulshift_map.v26
-rw-r--r--manual/PRESENTATION_ExAdv/mulshift_test.v5
-rw-r--r--manual/PRESENTATION_ExAdv/mulshift_test.ys7
5 files changed, 80 insertions, 1 deletions
diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index cf36d32cc..483389d84 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -361,6 +361,44 @@ this is known to work well.
\end{columns}
\end{frame}
+\subsubsection{Handling constant inputs}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and
+{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant
+input values to cells.
+\medskip
+\item The former contains 1-bits for all constant input bits on the port.
+\medskip
+\item The latter contains the constant bits or undef (x) for non-constant bits.
+\medskip
+\item Example use-cases:
+\begin{itemize}
+\item Converting arithmetic (for example multiply to shift)
+\item Identify constant addresses or enable bits in memory interfaces.
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname{} -- Example}
+\vbox to 0cm{
+\vskip5.2cm
+\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf}
+\vss
+}
+\vskip-0.6cm
+\begin{columns}
+\column[t]{6cm}
+\vskip-0.4cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v}
+\column[t]{4.2cm}
+\vskip-0.6cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys}
+\end{columns}
+\end{frame}
+
\subsubsection{TBD}
\begin{frame}{\subsubsecname}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 74f263270..3bbc239a4 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
@@ -13,3 +13,6 @@ sym_mul.pdf: sym_mul_*
mymul.pdf: mymul_*
../../yosys mymul_test.ys
+mulshift.pdf: mulshift_*
+ ../../yosys mulshift_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/mulshift_map.v b/manual/PRESENTATION_ExAdv/mulshift_map.v
new file mode 100644
index 000000000..4a3c2a062
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_map.v
@@ -0,0 +1,26 @@
+module MYMUL(A, B, Y);
+ parameter WIDTH = 1;
+ input [WIDTH-1:0] A, B;
+ output reg [WIDTH-1:0] Y;
+
+ parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
+ parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
+
+ reg _TECHMAP_FAIL_;
+ wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+ integer i;
+ always @* begin
+ _TECHMAP_FAIL_ <= 1;
+ for (i = 0; i < WIDTH; i=i+1) begin
+ if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin
+ _TECHMAP_FAIL_ <= 0;
+ Y <= B << i;
+ end
+ if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin
+ _TECHMAP_FAIL_ <= 0;
+ Y <= A << i;
+ end
+ end
+ end
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mulshift_test.v b/manual/PRESENTATION_ExAdv/mulshift_test.v
new file mode 100644
index 000000000..4b975f414
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_test.v
@@ -0,0 +1,5 @@
+module test (A, X, Y);
+input [7:0] A;
+output [7:0] X = A * 8'd 6;
+output [7:0] Y = A * 8'd 8;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mulshift_test.ys b/manual/PRESENTATION_ExAdv/mulshift_test.ys
new file mode 100644
index 000000000..c5dac49eb
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_test.ys
@@ -0,0 +1,7 @@
+read_verilog mulshift_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+ -map mulshift_map.v;;
+
+show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v