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-rw-r--r--passes/pmgen/xilinx_dsp.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 5af48e4d2..ce75be0e9 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -322,10 +322,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
opmode[5] = State::S1;
if (opmode[4] != State::S0) {
- //if (st.postAddMuxAB == "\\A")
- // st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool());
- //else
- // st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool());
+ if (st.postAddMuxAB == "\\A")
+ st.sigC.extend_u0(48, st.postAdd->getParam("\\B_SIGNED").as_bool());
+ else
+ st.sigC.extend_u0(48, st.postAdd->getParam("\\A_SIGNED").as_bool());
cell->setPort("\\C", st.sigC);
}