diff options
| -rw-r--r-- | techlibs/ecp5/.gitignore | 3 | ||||
| -rw-r--r-- | techlibs/ecp5/Makefile.inc | 15 | ||||
| -rw-r--r-- | techlibs/ecp5/bram.txt | 29 | ||||
| -rwxr-xr-x | techlibs/ecp5/brams_init.py | 22 | ||||
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 4 |
5 files changed, 73 insertions, 0 deletions
diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore new file mode 100644 index 000000000..84d260810 --- /dev/null +++ b/techlibs/ecp5/.gitignore @@ -0,0 +1,3 @@ +bram_init_1_2_4.vh +bram_init_9_18_36.vh +brams_init.mk diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 9d3247347..95d40fccf 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -5,4 +5,19 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) + +EXTRA_OBJS += techlibs/ecp5/brams_init.mk +.SECONDARY: techlibs/ecp5/brams_init.mk + +techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py + $(Q) mkdir -p techlibs/ecp5 + $(P) python3 $< + $(Q) touch $@ + +techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk +techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk + +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh)) diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt new file mode 100644 index 000000000..9d22e4afe --- /dev/null +++ b/techlibs/ecp5/bram.txt @@ -0,0 +1,29 @@ +bram $__ECP5_DP16KD + init 1 + + abits 10 @a10d18 + dbits 18 @a10d18 + abits 11 @a11d9 + dbits 9 @a11d9 + abits 12 @a12d4 + dbits 4 @a12d4 + abits 13 @a13d2 + dbits 2 @a13d2 + abits 14 @a14d1 + dbits 1 @a14d1 + + groups 2 + ports 1 1 + wrmode 1 0 + enable 2 1 @a10d18 + enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 + transp 0 2 + clocks 1 2 + clkpol 2 2 +endbram + +match $__ECP5_DP16KD + min bits 2048 + min efficiency 5 + shuffle_enable B +endmatch diff --git a/techlibs/ecp5/brams_init.py b/techlibs/ecp5/brams_init.py new file mode 100755 index 000000000..6f650b2a9 --- /dev/null +++ b/techlibs/ecp5/brams_init.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +with open("techlibs/ecp5/bram_init_1_2_4.vh", "w") as f: + for i in range(0, 0x40): + init_snippets = [] + for j in range(32): + init_snippets.append("INIT[%4d*8 +: 8]" % (32 * i + j)) + init_snippets.append("3'b000" if (j % 2 == 1) else "1'b0") + init_snippets = list(reversed(init_snippets)) + for k in range(8, 64, 8): + init_snippets[k] = "\n " + init_snippets[k] + print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f) + +with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f: + for i in range(0, 0x40): + init_snippets = [] + for j in range(16): + init_snippets.append("INIT[%3d*18 +: 18]" % (16 * i + j)) + init_snippets.append("2'b00") + init_snippets = list(reversed(init_snippets)) + for k in range(8, 32, 8): + init_snippets[k] = "\n " + init_snippets[k] + print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index c89fde1b1..3e7e83aac 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -472,6 +472,10 @@ module DP16KD( parameter CSDECODE_A = "0b000"; parameter CSDECODE_B = "0b000"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + + parameter GSR = "ENABLED"; parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; |