diff options
| -rw-r--r-- | techlibs/common/mul2dsp.v | 40 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 8 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
3 files changed, 14 insertions, 38 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 60b180ac0..6dcdcf226 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -146,17 +146,8 @@ module _80_mul (A, B, Y); // reduction' approach also exists...
if (i == 0)
assign partial_sum[i] = partial[i];
- else begin
- // Rewrite the following statement explicitly in order
- // to save on a call to 'opt_expr -fine' which would
- // optimise away the '<<' op and trim size of adder
- //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
- if (A_SIGNED && B_SIGNED)
- assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]);
- else
- assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)];
- assign partial_sum[i][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
- end
+ else
+ assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
end
\$__mul #(
@@ -170,12 +161,7 @@ module _80_mul (A, B, Y); .B(B),
.Y(last_partial)
);
- //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
- if (A_SIGNED && B_SIGNED)
- assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]);
- else
- assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)];
- assign partial_sum[n][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
+ assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
assign Y = partial_sum[n];
end
else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
@@ -211,17 +197,8 @@ module _80_mul (A, B, Y); // reduction' approach also exists...
if (i == 0)
assign partial_sum[i] = partial[i];
- else begin
- // Rewrite the following statement explicitly in order
- // to save on a call to 'opt_expr -fine' which would
- // optimise away the '<<' op and trim size of adder
- //assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
- if (A_SIGNED && B_SIGNED)
- assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]);
- else
- assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
- assign partial_sum[i][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
- end
+ else
+ assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
end
\$__mul #(
@@ -235,12 +212,7 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]),
.Y(last_partial)
);
- //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
- if (A_SIGNED && B_SIGNED)
- assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]);
- else
- assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
- assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
+ assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
assign Y = partial_sum[n];
end
else begin
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 98d3e44e3..694782e5b 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -276,9 +276,11 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("wreduce t:$add", " (if -dsp)"); - run("ice40_dsp", " (if -dsp)"); - run("chtype -set $mul t:$__soft_mul","(if -dsp)"); + run("opt_expr -fine a:mul2dsp", " (if -dsp)"); + run("wreduce a:mul2dsp", " (if -dsp)"); + run("ice40_dsp", " (if -dsp)"); + run("setattr -unset mul2dsp a:mul2dsp", "(if -dsp)"); + run("chtype -set $mul t:$__soft_mul", " (if -dsp)"); } run("alumacc"); run("opt"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ca108e9d6..b87fa9f6f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -346,7 +346,9 @@ struct SynthXilinxPass : public ScriptPass "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); - run("wreduce t:$add"); + run("opt_expr -fine a:mul2dsp"); + run("wreduce a:mul2dsp"); + run("setattr -unset mul2dsp a:mul2dsp"); run("xilinx_dsp"); run("chtype -set $mul t:$__soft_mul"); } |