diff options
| -rw-r--r-- | kernel/rtlil.cc | 6 | ||||
| -rw-r--r-- | kernel/rtlil.h | 8 | ||||
| -rw-r--r-- | passes/pmgen/ice40_dsp.cc | 3 | ||||
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 34 |
4 files changed, 36 insertions, 15 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 909f60dd9..fade0bc36 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3299,7 +3299,7 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) check(); } -RTLIL::SigSpec& RTLIL::SigSpec::remove_const() +void RTLIL::SigSpec::remove_const() { if (packed()) { @@ -3333,7 +3333,6 @@ RTLIL::SigSpec& RTLIL::SigSpec::remove_const() } check(); - return *this; } void RTLIL::SigSpec::remove(int offset, int length) @@ -3429,7 +3428,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) check(); } -RTLIL::SigSpec& RTLIL::SigSpec::extend_u0(int width, bool is_signed) +void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { cover("kernel.rtlil.sigspec.extend_u0"); @@ -3446,7 +3445,6 @@ RTLIL::SigSpec& RTLIL::SigSpec::extend_u0(int width, bool is_signed) append(padding); } - return *this; } RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 16fd852ba..37b5f984c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -754,8 +754,8 @@ public: inline int size() const { return width_; } inline bool empty() const { return width_ == 0; } - inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return index >= 0 ? bits_.at(index) : bits_.at(width_ + index); } - inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return index >= 0 ? bits_.at(index) : bits_.at(width_ + index); } + inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); } + inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); } inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } @@ -787,7 +787,7 @@ public: void remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other); void remove(int offset, int length = 1); - RTLIL::SigSpec& remove_const(); + void remove_const(); RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other = NULL) const; @@ -797,7 +797,7 @@ public: void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); - RTLIL::SigSpec& extend_u0(int width, bool is_signed = false); + void extend_u0(int width, bool is_signed = false); RTLIL::SigSpec repeat(int num) const; diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index bb45b8a4e..66f70399d 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -23,9 +23,10 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -template<class T> bool includes(const T &lhs, const T &rhs) { +template<class T> inline bool includes(const T &lhs, const T &rhs) { return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end()); } +#include <set> #include "passes/pmgen/ice40_dsp_pm.h" void create_ice40_dsp(ice40_dsp_pm &pm) diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index c59c5d20a..cda7535f3 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -2,6 +2,7 @@ pattern ice40_dsp state <SigBit> clock state <bool> clock_pol +state <std::set<SigBit>> sigAset sigBset state <SigSpec> sigA sigB sigCD sigH sigO sigOused state <Cell*> addAB muxAB @@ -10,6 +11,15 @@ match mul select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10 endmatch +code sigAset sigBset + SigSpec A = port(mul, \A); + A.remove_const(); + sigAset = A.to_sigbit_set(); + SigSpec B = port(mul, \B); + B.remove_const(); + sigBset = B.to_sigbit_set(); +endcode + code sigH if (mul->type == $mul) sigH = mul->getPort(\Y); @@ -22,9 +32,9 @@ endcode match ffA if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool() - if !port(mul, \A).remove_const().empty() + if !sigAset.empty() select ffA->type.in($dff) - filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set()) + filter includes(port(ffA, \Q).to_sigbit_set(), sigAset) optional endmatch @@ -45,9 +55,9 @@ endcode match ffB if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool() - if !port(mul, \B).remove_const().empty() + if !sigBset.empty() select ffB->type.in($dff) - filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set()) + filter includes(port(ffB, \Q).to_sigbit_set(), sigBset) optional endmatch @@ -192,18 +202,30 @@ endcode match ffO_lo if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2 select ffO_lo->type.in($dff) - filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set()) optional endmatch +code + SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())); + O.remove_const(); + if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set())) + reject; +endcode + match ffO_hi if GetSize(sigOused) > 16 if nusers(sigOused.extract_end(16)) == 2 select ffO_hi->type.in($dff) - filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set()) optional endmatch +code + SigSpec O = sigOused.extract_end(16); + O.remove_const(); + if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set())) + reject; +endcode + code clock clock_pol sigO sigCD if (ffO_lo || ffO_hi) { if (mul->type == \SB_MAC16) { |