diff options
| -rw-r--r-- | manual/command-reference-manual.tex | 12 | ||||
| -rw-r--r-- | passes/opt/opt_mem_priority.cc | 2 |
2 files changed, 2 insertions, 12 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index d9a2f8dc1..28d2b6107 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -3163,7 +3163,7 @@ for removal of the read port. opt_mem_priority [selection] This pass detects cases where one memory write port has priority over another -even though they can never collide with each other — ie. there can never be +even though they can never collide with each other -- ie. there can never be a situation where a given memory bit is written by both ports at the same time, for example because of always-different addresses, or mutually exclusive enable signals. In such cases, the priority relation is removed. @@ -3661,11 +3661,6 @@ Additional -D<macro>[=<value>] options may be added after the option indicating the language version (and before file names) to set additional verilog defines. - read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. - -Load the specified VHDL files. (Requires Verific.) - - read {-f|-F} <command-file> Load and execute the specified command file. (Requires Verific.) @@ -7480,11 +7475,6 @@ The macros SYNTHESIS and VERIFIC are defined implicitly. Like -sv, but define FORMAL instead of SYNTHESIS. - verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. - -Load the specified VHDL files into Verific. - - verific {-f|-F} <command-file> Load and execute the specified command file. diff --git a/passes/opt/opt_mem_priority.cc b/passes/opt/opt_mem_priority.cc index 49ece570b..a9b145bea 100644 --- a/passes/opt/opt_mem_priority.cc +++ b/passes/opt/opt_mem_priority.cc @@ -34,7 +34,7 @@ struct OptMemPriorityPass : public Pass { log(" opt_mem_priority [selection]\n"); log("\n"); log("This pass detects cases where one memory write port has priority over another\n"); - log("even though they can never collide with each other — ie. there can never be\n"); + log("even though they can never collide with each other -- ie. there can never be\n"); log("a situation where a given memory bit is written by both ports at the same\n"); log("time, for example because of always-different addresses, or mutually exclusive\n"); log("enable signals. In such cases, the priority relation is removed.\n"); |