aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--backends/aiger/xaiger.cc69
-rw-r--r--frontends/aiger/aigerparse.cc41
-rw-r--r--techlibs/xilinx/abc_ff.v6
-rw-r--r--techlibs/xilinx/abc_xc7.box4
-rw-r--r--techlibs/xilinx/ff_map.v12
5 files changed, 59 insertions, 73 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index dbf9b9750..87dca014d 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -233,49 +233,40 @@ struct XAigerWriter
}
RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
- bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
- if (inst_flop) {
- toposort.node(cell->name);
-
- for (const auto &c : cell->connections()) {
- auto is_input = cell->input(c.first);
- auto is_output = cell->output(c.first);
- log_assert(is_input || is_output);
- RTLIL::Wire* port = inst_module->wire(c.first);
- if (is_input && port->attributes.count("\\abc_flop_d")) {
- SigBit d = c.second;
- SigBit I = sigmap(d);
- if (I != d)
- alias_map[I] = d;
- unused_bits.erase(d);
- }
- if (is_output && port->attributes.count("\\abc_flop_q")) {
- SigBit q = c.second;
- SigBit O = sigmap(q);
- if (O != q)
- alias_map[O] = q;
- undriven_bits.erase(O);
- ff_bits.emplace_back(q);
- }
- }
- log_assert(inst_module->attributes.count("\\abc_box_id"));
- abc_box_seen = true;
- }
- else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
+ if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
abc_box_seen = true;
toposort.node(cell->name);
- for (const auto &conn : cell->connections()) {
- if (cell->input(conn.first)) {
- // Ignore inout for the sake of topographical ordering
- if (cell->output(conn.first)) continue;
- for (auto bit : sigmap(conn.second))
- bit_users[bit].insert(cell->name);
- }
+ auto abc_flop_d = inst_module->attributes.at("\\abc_flop_d", RTLIL::Const());
+ if (abc_flop_d.size() == 0) {
+ for (const auto &conn : cell->connections()) {
+ if (cell->input(conn.first)) {
+ // Ignore inout for the sake of topographical ordering
+ if (cell->output(conn.first)) continue;
+ for (auto bit : sigmap(conn.second))
+ bit_users[bit].insert(cell->name);
+ }
- if (cell->output(conn.first))
- for (auto bit : sigmap(conn.second))
- bit_drivers[bit].insert(cell->name);
+ if (cell->output(conn.first))
+ for (auto bit : sigmap(conn.second))
+ bit_drivers[bit].insert(cell->name);
+ }
+ }
+ else {
+ auto abc_flop_q = inst_module->attributes.at("\\abc_flop_q");
+
+ SigBit d = cell->getPort(RTLIL::escape_id(abc_flop_d.decode_string()));
+ SigBit I = sigmap(d);
+ if (I != d)
+ alias_map[I] = d;
+ unused_bits.erase(d);
+
+ SigBit q = cell->getPort(RTLIL::escape_id(abc_flop_q.decode_string()));
+ SigBit O = sigmap(q);
+ if (O != q)
+ alias_map[O] = q;
+ undriven_bits.erase(O);
+ ff_bits.emplace_back(q);
}
}
else {
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 5a6db8481..60cbde857 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -737,11 +737,13 @@ void AigerReader::post_process()
log_assert(box_module);
RTLIL::Module* flop_module = nullptr;
- if (box_module->attributes.count("\\abc_flop")) {
+ auto flop_module_name = box_module->attributes.at("\\abc_flop", RTLIL::Const());
+ RTLIL::IdString flop_past_q;
+ if (flop_module_name.size() > 0) {
log_assert(flop_count < flopNum);
- log_assert(box_module->name.begins_with("$__ABC_"));
- flop_module = design->module("\\" + box_module->name.substr(7));
+ flop_module = design->module(RTLIL::escape_id(flop_module_name.decode_string()));
log_assert(flop_module);
+ flop_past_q = box_module->attributes.at("\\abc_flop_past_q").decode_string();
}
else if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
@@ -778,8 +780,6 @@ void AigerReader::post_process()
}
}
- RTLIL::Wire *d = nullptr;
- RTLIL::Wire *q = nullptr;
// NB: Assume box_module->ports are sorted alphabetically
// (as RTLIL::Module::fixup_ports() would do)
for (auto port_name : box_module->ports) {
@@ -789,14 +789,6 @@ void AigerReader::post_process()
for (int i = 0; i < GetSize(port); i++) {
RTLIL::Wire* wire = nullptr;
if (port->port_input) {
- if (flop_module && port->attributes.count("\\abc_flop_d")) {
- log_assert(!d);
- d = outputs[outputs.size() - flopNum + flop_count];
- log_assert(d);
- log_assert(d->port_output);
- d->port_output = false;
- }
-
log_assert(co_count < outputs.size());
wire = outputs[co_count++];
log_assert(wire);
@@ -804,14 +796,6 @@ void AigerReader::post_process()
wire->port_output = false;
}
if (port->port_output) {
- if (flop_module && port->attributes.count("\\abc_flop_q")) {
- log_assert(!q);
- q = inputs[piNum - flopNum + flop_count];
- log_assert(q);
- log_assert(q->port_input);
- q->port_input = false;
- }
-
log_assert((piNum + ci_count) < inputs.size());
wire = inputs[piNum + ci_count++];
log_assert(wire);
@@ -820,13 +804,24 @@ void AigerReader::post_process()
}
rhs.append(wire);
}
- if (!flop_module || !port->attributes.count("\\abc_discard"))
+
+ if (!flop_module || port_name != flop_past_q)
cell->setPort(port_name, rhs);
}
+
if (flop_module) {
+ RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
+ log_assert(d);
+ log_assert(d->port_output);
+ d->port_output = false;
+
+ RTLIL::Wire *q = inputs[piNum - flopNum + flop_count];
+ log_assert(q);
+ log_assert(q->port_input);
+ q->port_input = false;
+
flop_count++;
cell->type = flop_module->name;
- //module->addFfGate(NEW_ID, d1 q);
module->connect(q, d);
}
}
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index abf4ac093..e95602ab2 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,11 +23,11 @@
module \$__ABC_FF_ (input C, D, output Q);
endmodule
-(* abc_box_id = 6, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE ((* abc_flop_q *) output Q, input C, CE, (* abc_flop_d *) input D, (* abc_flop_q_past, abc_discard *) input Q_past, input R);
+(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
+module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
- assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : Q_past);
+ assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 42f563898..9aef37545 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -41,8 +41,8 @@ RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - -
-# Inputs: C CE D Q_past R
-# Outputs: Q_next
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
FDRE 6 1 5 1
- - - - -
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index bd36c78fc..5ad73aa63 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -27,9 +27,9 @@ module \$_DFF_P_ (input D, C, output Q);
`ifndef _ABC
FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
`else
- wire Q_next;
- \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
- \$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
+ wire \$nextQ ;
+ \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(1'b1), .R(1'b0));
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
`endif
endmodule
@@ -38,9 +38,9 @@ module \$_DFFE_PP_ (input D, C, E, output Q);
`ifndef _ABC
FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
`else
- wire Q_next;
- \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(E), .R(1'b0));
- \$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
+ wire \$nextQ ;
+ \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(E), .R(1'b0));
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
`endif
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-19 23:06:11 +0000