diff options
| -rw-r--r-- | passes/techmap/techmap.cc | 8 | ||||
| -rw-r--r-- | tests/techmap/autopurge.ys | 62 |
2 files changed, 69 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index cf40b2f17..1d0362ad6 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -224,7 +224,7 @@ struct TechmapWorker for (auto bit : sigmaps.at(tpl)(it.second)) if (bit.wire != nullptr) - autopurge_tpl_bits.insert(it.second); + autopurge_tpl_bits.insert(bit); } } IdString w_name = it.second->name; @@ -359,6 +359,12 @@ struct TechmapWorker for (auto &attr : w->attributes) { if (attr.first == ID(src)) continue; + auto lhs = GetSize(extra_connect.first); + auto rhs = GetSize(extra_connect.second); + if (lhs > rhs) + extra_connect.first.remove(rhs, lhs-rhs); + else if (rhs > lhs) + extra_connect.second.remove(lhs, rhs-lhs); module->connect(extra_connect); break; } diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys new file mode 100644 index 000000000..1eb99ec37 --- /dev/null +++ b/tests/techmap/autopurge.ys @@ -0,0 +1,62 @@ +# https://github.com/YosysHQ/yosys/issues/1381 +read_verilog <<EOT +module sub(input i, output o, (* techmap_autopurge *) input j); +foobar f(i, o, j); +endmodule +EOT +design -stash techmap + +read_verilog <<EOT +(* blackbox *) +module sub(input i, output o, input j); +endmodule + +(* blackbox *) +module foobar(input i, output o, input j); +endmodule + +module top(input i, output o); +sub s0(i, o); +endmodule +EOT + +techmap -map %techmap +hierarchy +check -assert + +# https://github.com/YosysHQ/yosys/issues/1391 +design -reset +read_verilog <<EOT +module sub(input i, output o, (* techmap_autopurge *) input [1:0] j); +foobar f(i, o, j); +endmodule +EOT +design -stash techmap + +read_verilog <<EOT +(* blackbox *) +module sub(input i, output o, input j); +endmodule + +(* blackbox *) +module foobar(input i, output o, input j); +endmodule + +module top(input i, output o); +sub s0(i, o); +endmodule +EOT + +techmap -map %techmap +hierarchy +check -assert + +read_verilog -overwrite <<EOT +module top(input i, output o); +wire j; +sub s0(i, o, j); +endmodule +EOT + +techmap -map %techmap +hierarchy |