diff options
| -rw-r--r-- | passes/hierarchy/submod.cc | 20 | ||||
| -rw-r--r-- | tests/various/submod.ys | 25 |
2 files changed, 44 insertions, 1 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index ec242aa1f..982558fb2 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -20,6 +20,7 @@ #include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/log.h" +#include "kernel/sigtools.h" #include <stdlib.h> #include <stdio.h> #include <set> @@ -32,6 +33,7 @@ struct SubmodWorker CellTypes ct; RTLIL::Design *design; RTLIL::Module *module; + pool<Wire*> outputs; bool copy_mode; std::string opt_name; @@ -125,7 +127,7 @@ struct SubmodWorker if (wire->port_input) flags.is_ext_driven = true; - if (wire->port_output) + if (wire->port_output || outputs.count(wire)) flags.is_ext_used = true; bool new_wire_port_input = false; @@ -219,6 +221,22 @@ struct SubmodWorker ct.setup_stdcells_mem(); ct.setup_design(design); + SigMap sigmap(module); + for (auto port : module->ports) { + auto wire = module->wire(port); + if (!wire->port_output) + continue; + auto sig = sigmap(wire); + for (auto c : sig.chunks()) { + if (!c.wire) + continue; + if (c.wire == wire) + continue; + outputs.insert(c.wire); + log_dump(c.wire->name); + } + } + if (opt_name.empty()) { for (auto &it : module->wires_) diff --git a/tests/various/submod.ys b/tests/various/submod.ys new file mode 100644 index 000000000..271a8edef --- /dev/null +++ b/tests/various/submod.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT +module top(input a, output [1:0] b); +wire c; +(* submod="bar" *) sub s1(a, c); +assign b[0] = c; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +flatten +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |